Historical Document · 1978
US Patent 4,074,351: Variable Function Programmed Calculator (Boone and Cochran)
Texas Instruments' patent on a single-chip programmed calculator: filed 24 February 1977, granted 14 February 1978.
Historical Document · 1978
Texas Instruments' patent on a single-chip programmed calculator: filed 24 February 1977, granted 14 February 1978.
United States Patent 1 Boone et al. 4,074,351 Feb. 14, 1978 1083) [45] [54] VARIABLE FUNCTION PROGRAMMED Attorney, Agent, or Firm—James T. Comfort; John G. CALCULATOR Graham [75] Inventors: Gary W. Boone, Sunnyvale, Calif.; (57] ABSTRACT Michael J, Cochran, Richardson, A variable function calculator utilizes a fixed program Tex. memory array such as a programmed read only mem- . ory in which a number of programs are stored depend- [73] Assignee: Texas Instruments Incorporated, ing upon the desired functions of the calculator. The Dallas, Tex. calculator also includes a program counter, an instruc- . ~ tion register, control decoders, jump-condition circuits, [21] Appl. No.: 771,498 a clock generator, a timing generator, digit and FLAG [22] Filed: Feb, 24, 1977 mask decoders, key input logic, a register and FLAG data storage array, a decimal and FLAG arithmetic D logic unit, an output decoder, and a digit scanner which Related U.S. Application scans both the keyboard and display outputs. Aside [60] Continuation of Ser. No. 529,251, Dec. 2, 1974, from providing basic desk top calculator functions, the abandoned, which is a division of Ser. No. 420,999, read only memory may be programmed so that the Dec. 3, 1973, which is a continuation of Ser. No. system provides metering functions, arithmetic teaching 163,565, July 19, 1971, abandoned. functions, control functions, etc. A preferred embodi- [51] Int. CL GO6F 15/04 ment of the invention is capable of being fabricated as a [52] U.S Cc. _ 364/200 monolithic integrated semiconductor system utilizing [58] Field of Search ” ” 364/200 contemporary metal-insulator-semiconductor _ tech- niques. Primary Examiner—Gareth D. Shaw Assistant Examiner—C. T. Bartz 20 Claims, 76 Drawing Figures 218 LS 210 r 225 DELAY 204 seugcror NS £210 7 oe bs) T as 217 c/s L.| seme avoer—] COND uu 19 seteeron 6 2105 210 j230 192 BN (711 4 REGISTERS, aig ! if 224. x pz AU NA t 21 , 210: 24 DELAYS pe BY c 210 cy 1 210 223 215 216 CONSTANT- (PUT U.S. Patent Feb. 14, 1978 Sheet 1 of 65 4,074,351 202 201 f PROGRAM (ROM) CONTROL (PLA) al KC a TIMING . DATA | | a) 204 ‘a 7 (DSR, PLA) (RAM & ALU) | | 205 Vv / ie T | DISPLAY OUTPUT | & (DSR, PLA) | KEYBOARD Loe U.S. Patent Feb. 14, 1978 Sheet 2 of 65 4,074,351 POT ~T | | | | | | | | ROM | | 208 jn | | 190 HHH -—= Madea -209 | r Licomatt = oo | HHH PE LS f 7 controt| == | j 191 | DECODERS | —E SS = FLAC ALU | 203 = + rook Loam m4 an _~, | ms—[s]s| me | | | 590~ §— lorconens badd He HY HH tHE dt La | | ieg_fo JE] of ECTS H-| « | EN ~ | key TGEN pod RAM = & | ~Inputl = -/ 208 =| = | KP _ LOSic | =| | | | ~ CGEN 8 | KQ p93 ~ 96-7 |___p L | DIGIT z=[sec pecopER| =| 4, | OUTPUT | | SA = D:AA = t ee | 42 | ° Bey 4 Bs MY eee AM SJ | Pe ee ~<a U.S. Patent Feb. 14, 1978 Sheet 3 of 65 4,074,351 218g (210 Fi, 3 Y 225 1g: |_-DELAY “<¢ . 204 SELECTOR || NS 210 SB c2 210 ms 211 T : c/B|_.| JUMP ADDER—— COND SELECTOR 210L 7 5 A 219 RS Pp 210 Jor0 192 EA 711 A REGISTERS 210U I 224 5 p210 AU NA ik | nd 210 EX 2107 aNw 2147 N INPUT G poecars SELECTOR \ 220 ] 212 a { a reseree 210 BV B B [ t = 5 210 213 Lous mae a C REGISTER 22 I 210 210 223 MS C ( cu WW NC | 215 216 210 CONSTANT’ / (220 INPUT INPUT — 214 SELECTOR DELAY 204 208 230 a cruae LOGIC 228 FLAG A REGISTER A 192 Z SITTITITiT til ry sup | 29 FA 730 L 30) FFLG +7 me DEL asd, RFLG JUMP 227 228 ) SFLG COND FLAG FB \ XFLG —LLCLIIIITtIttt4j FLAG B REGISTER 230 230| 8B \ U.S. Patent Feb. 14, 1978 Sheet 4 of 65 4,074,351 Fig.5 202 230 231 233 7 7 7 y 1 H JUMP ' 1 IMIM, IM. !Mal] S [RLTRL IR. [2 ai7 bl [conn u c 4 7 v v 192 M (232) R (234) = (235) OSMS9 (232) ASMSF (232) r _A ~ — \ r REGISTER FLAG I (230) 4 OPERATIONS OPERATIONS cr JUMP IF JUMP IF = CONDITION CONDITION 1(230) ~ IS TRUE IS FALSE M, {231} M, (231) 4,074,351 Sheet 5 of 65 U.S. Patent Feb. 14, 1978 SHSVW LIOId AIdWNVXa — | | | | 9614 | | | | | | 7 | SULVLS ri\ aa | sf TSU SL LLYN, eee ee ge ™ 292 | Sf LULL aay “wz ATAUDURERURUUPURURUSUPORURERUDUREDOROUUIUgEQUSUREDRSUARBUDOVUDERERUREDO ROT EUER I mA Novz su90'19 tor U.S. Patent Feb. 14, 1978 Sheet 6 of 65 4,074,351 Fig, 7 203 U.S. Patent Feb. 14, 1978 Sheet 7 of 65 4,074,351 203 60 2 \ 513 $12 S11 S10 S9 S8 S87 S6_ S5 S4 S3_ S2_ SI 8 o;{,oj};o0 jo 1 o}oOj1 oj; ojo {oO 0 4 o]/oj;]o jo of; i170 40 oOo; 1 o ;0 0 REGISTERS AIBIC 2tololo {1 | of ofa fo | 1] ofo fo J 4 r1}o{}ofol1 {| ofo]fia fi] 1} o0]o]o |] o OVF MSD LSD EXPDPT Lo MANTISSA ———>+TAc-+| (M) (T) DECIMAL PT (DPT) Jz |e |s [+ fs [2] ]o| EXPONENT (E) o 1 ols la | [6 |7 261 1 opin Dio D9 D8 D7 D6 DS D4 D3 D2 Di DISPLAY 3 is |a [3 | 9 fs. ] 4] 0 DPT=0010 262 FA FLAGS FB E Fig. 8 U.S. Patent Feb. 14, 1978 Sheet 8 of 65 4,074,351 [ [) ih SI I ' LS m —4 I 5 me L min 7 ) TNEG Jol=Isfieol slo |ois| U.S. Patent Feb. 14, 1978 Sheet 9 of 65 4,074,351 Cel=is bode lalolslat) 28 PIN PACKAG) VYVYVV V |. wees Tox) K- NOT USEDON SEVEN SEc- ) MENT DISPLAYS | ro Ln z>—> LO 2>—f>4 mu >_> U.S. Patent Feb. 14, 1978 Sheet 10 of 65 4,074,351 Fig. 13 | | on { | : oo 4 Fig. 1/4 U.S. Patent Feb. 14, 1978 Sheet 11 of 65 4,074,351 15 on =r on , 6 2 I T T T I I I L I ec Kya H LH SA Oo ee ee a os ee oe ees T } I L I J ] 1 I r+ Oo + > eH sHseHh3sH2z2h: HOF I im I L i I L I I Lyk H HO H H RH H ROH WF ow O10 Ds ps o7 D4 03 D2 or Fig./6 U.S. Patent Feb. 14, 1978 Sheet 12 of 65 4,074,351 Fig. /7A Fig.17B Fig.17C Fig. 170 Fig I7E Fig. 17F Fig. 17H Fig. 171 Fig./7Jd Fig. 17K Fig ¢7L Fig: /7M Fig. 17N Fig.170 Fig. 17P Figs 17Q Fig. 17R Fig. (7T Fig./7U Fig. /7X Fig. 17 Fig 17¥ Fig A7Z 4,074,351 Sheet 13 of 65 U.S. Patent Feb. 14, 1978 77 ~ a= F wes <7 z 1a mi Dy Dey Z — 1 Y ba OF cr. IT RTT wt ites U t é vi oan t —_—/—— — a) gél y & 2S crEE sores ee go Re WIIIDIG LNIWOW 109 rs" £e¢S VL/ ‘bly 4,074,351 Sheet 14 of 65 U.S. Patent Feb. 14, 1978 GZl'bi4 s| G ’ or 29 | 2185 fa I _poiesvn ves t or 18 \ OF HG \ | ia oes Ipoh’ ty ; Ors a Sheet 15 of 65 4,074,351 Feb. 14, 1978 U.S. Patent ee na We _| C pt-Fa nv 2a |, Tv iy add £g5 fk zn ess L bGS oN asin, FSS pH AW — os 2218/4 $lé U.S. Patent Feb. 14, 1978 Sheet 16 of 65 4,074,351 Ls 3 am n3 | ar Te Ly ua Thy a ley '» s| A Y { N R va } = vt & 8 8 © yt S f . 5 © © 4S [S < ££ —e U.S. Patent Feb. 14, 1978 Sheet 17 of 65 4,074,351 Fig. /7E 1968 Ley 605 | b— 8a op Sey J od 220 | r y sre tee (i Ur [1H L}Yy Li (ty [i [ }4 Li US 4,074,351 Sheet 18 of 65 U.S. Patent Feb. 14, 1978 | l ' | | ~ ol or \ bi | ' +9 Zes | \ M4 (“8 —4 ! | \ - fen phe on ol ol ods on | | vy apd in o/ ol ees oo I | [%) |9e8 bes a | parr pest > ! 7 a ol LES co | 2a | I Hi ol 9£5 | ol i | ev | a (a's iz 4/61 : H U.S. Patent Feb. 14, 1978 Sheet 19 of 65 4,074,351 Ss + te 8 8 — <j}-— + 71S 2 S&S > J La > NR led 2? ~ 8] e 7° D ty © T “U u s ¢ U © 2 z s se Ay*S (le Le 3-48 3 a ry 2 x x s < hg, ) {\ is ey Ve AS | fe )fS La | 7 rT Ty L_——— 4,074,351 Sheet 20 of 65 U.S. Patent Feb. 14, 1978 H21'b14 $95 sooo § wo| 1% -— 095] Ls tr if i 659 $gg Cl | \ 85S Se. ly P PLL q o<} ls IGG" 09 tC $99 Qe - - Us J y ! 996 = | +— |, Cr “<hr (998 U.S. Patent Feb. 14, 1978 Sheet 21 of 65 4,074,351 ray he a —_—_—__—_— and hy QDOSODOS IS ta a bad ~ ~ < < — re iS Im nN wv 1g = x peuse . oo joe [08 SOON TOR MOT Hla or onstmn aga aqaqqnaaa Fig. 471 4,074,351 Sheet 22 of 65 U.S. Patent Feb. 14, 1978 7c iio | o or v4 996 oo abr} L a 908) in 7 | tL. 01 o! | gg “es a imi phe, , ia pots J TY 08) _ meuee Lae pobsbl ee "| U.S. Patent Feb. 14, 1978 Sheet 23 of 65 4,074,351 N ~s > re — _ x — & L T x ¢ B ro © n FS U)\Z)\S) a Ta 3] [2 & 2 ATS = 3 w i * S s S we N NOES 8 \ fea) (2 We ) (8%. (4 ics ‘2 U.S. Patent Feb. 14. 1978 Sheet 24 of 65 4,074,351 TFLE ® \z IW ~ t N _$ ~ 4 > he w]e] ef} eo) of 2) 9 2 eae Bhd ds a 3/8] e]8] 8/3) 8) a] 3 32 ES HB ge na & N KB] s U.S. Patent Feb. 14, 1978 Sheet 25 of 65 4,074,351 Fig.17M U.S. Patent Feb. 14. 1978 Sheet 26 of 65 sus FFLG RFLG SFLG X FLO 4,074,351 =] | FMSK GB YL LY 9 8 2 229 __| Fig. /7N a A 8 N w * | by U.S. Patent Feb. 14, 1978 Sheet 27 of 65 4,074,351 —_—_— eo Swe % 7T7— ~ ao | 2 ~ Ih & 4 s ~ % Sh | ewes a g 1 | 9 ' | 8 eT S I | wk ie SVyey | Ww " es Nl VE 1 TC “ | 3 | & ©. _ S<oisligist} fig. /70 U.S. Patent Feb. 14, 1978 Sheet 28 of 65 4,074,351 \jo58 want Prt 4 a t ie a4 apen: p+ _ 11-4 4 d L +? > > J Do ] i cay 4 € se ae) aneiy L q 4 q Oy Ss q _ae ie Bi a a 4 ae * eK a 1] ~~ Qa Fig. /7P e s- 4,074,351 Sheet 29 of 65 U.S. Patent Feb. 14, 1978 gL ---- a ee Lees q ad 1 Tt ° | Iw “+ ri 4 ° ° a 7m i @ | Is 1 0 ° ay 7 <<] tie | ~~ Lo | 1 Tt: | Zs ° SS CE = 4 | Y¥ cos! | | | | | | 4 ~, 71 | 9994 20s\ | i 4 | wou | -|-|------- 4 aor | | | | | | OLI Bly 609 A I 4 4,074,351 Sheet 30 of 65 U.S. Patent Feb. 14, 1978 = im 1p 9 lL Tey —]-|- c-Rel | grox | UL + ky ,! bls] Ls RRR us a 1 ee Ht Ps WS | = | h =I | $8g LL | zs | ‘ne Tee i | foes | \ | ! | i | 1 | il YL/6)4 | ___ | bas t \ Loo NOILIGNOD INN 1 U.S. Patent Feb. 14, 1978 Sheet 31 of 65 4,074,351 - | Il (525 519 [ 1-517 5/3 Fig. 7S U.S. Patent Feb. 14, 1978 Sheet 32 of 65 4,074,351 ey 2 K N ~ bal ~ 5 ‘ > 2 Ww pe ae t & LF 3 Wat] Sa Ve) a Z & bed % S 7 we Xz a; | os 3} yj 3 3 2 . a © an © uf-7-[-/—]-}-]-]-]-]— lI 4,074,351 Sheet 33 of 65 U.S. Patent Feb. 14, 1978 fo aes | ———— [| err Cs eee ee .sc—T TTT | ! ss 4 — = | | Sn) Thao ! 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Ay & bes e AB ida n Yt 8 %® I 4,074,351 Sheet 35 of 65 U.S. Patent Feb. 14, 1978 [te Ve Ww ue an La "Dy Moz lea NNN w ig BIg 48 [so \\ | é ele | aS —_ a je_le-|j--|--J--]-—-]--|-- _-|--|———-]-]-]-| -—-—aRo MZI'O14 U.S. Patent Feb. 14, 1978 Sheet 36 of 65 4,074,351 BASIC CLOCK 143 76 ct Fig. /17X 4,074,351 Sheet 37 of 65 U.S. Patent Feb. 14, 1978 76s | tél) je | SEH 08 es Bas omususss Bes | | ; as = ttt eee aan ES }~-e- > 7 6s eyyayeyt 7@a MAD d Seo ig ie _ )_ ee Sse OE 4,074,351 Sheet 38 of 65 U.S. Patent Feb. 14, 1978 21907 wIHlo wor AN WOTMITAd P SILVO UUSWAL BOF Shy egy Teg 1) NGEG -_ a \Sa374n8 771d Hsnd 1 1 WE ng 7) ngs T T T Tv mm ah 190 | 20 209 Te £b/ HIOTD §=FSVHd-£ Bag 2oe 18D ZL 'b14 U.S. Patent Feb. 14, 1978 Sheet 39 of 65 4,074,351 ea [>< cc a - Fig: /8A U.S. Patent Feb. 14, 1978 Sheet 40 of 65 4,074,351 U.S. Patent Feb. 14, 1978 Sheet 41 of 65 4,074,351 Yop Vv 4 552 GG c c A B B Yop A 553 4 c Cc A B B Yop 554 4% A —_— c O c A B B , 44 A Vac 555 | c — B + c a s A O c 556 c B - a Ne B— —/ Fig. 18C U.S. Patent Feb. 14, 1978 Sheet 42 of 65 4,074,351 Figeh /8D fo Yoa Yop Voc Yop Yoa Yop eee] Vv GG Yop Voc Yop + Yop Voc Yop ca Let ety SN) oad a ; ud eh U.S. Patent Feb. 14, 1978 Sheet 43 of 65 4,074,351 AOORESS LINE 4 r vy wo ¥ Meo, i L549 al —) | [fa | oe j U.S. Patent Feb. 14, 1978 Sheet 44 of 65 4,074,351 Fig.2/ moa Yop Yac’pp Yaa Ypp Idd bd Yea Yop Yoa ee” Fs ag ag aa —G uA por B Vac Yop ae an Lic GauGnw - LAT Ly - r tT Gebeee ageSue Vv aa Wy, We, c + a Qa | ag I rid L ane ag ane Geawene ag Gnu iw] 8 U.S. Patent Feb. 14, 1978 Sheet 45 of 65 4,074,351 LABEL; CONNECTIVES TO FROM OTHER FIGURE A+ B—B REGISTER ASSIGNMENT OPERATION RESET B7 FLAG ASSIGNMENT OPERATION PREV OP 1 TEST OPERATION YES BRANCH CONDITIONAL NO Fig.22A WAIT OPERATIONS LABEL U.S. Patent Feb. 14, 1978 040 TOGGLE SIGN A 041 Le} RESET 044 CURR OP 1 DISPLAY NORM 051 O50 O4F EXCHANGE CURR OP 12 056 § Sheet 46 of 65 Q SET CURR OP 2 047 SET CURR OP 1 O4E SET DISPLAY RESET DPT OP3 4,074,351 Fig.228 U.S. Patent Feb. 14, 1978 058 RESET DPT 022 y RESET DISPLAY RESET SIGN Ae Sheet 47 of 65 4,074,351 03E 000 SET CLEAR DPT FA oor CLEAR FB oo ¥ O-A osB oo3 MY TOGGL OGGLE onc SIGN A osc Fig. 22C U.S. Patent Feb. 14, 1978 Sheet 48 of 65 4,074,351 Fig.22D U.S. Patent Feb. 14, 1978 Sheet 49 of 65 4,074,351 U.S. Patent Feb. 14, 1978 034 SET ERR Sheet 50 of 65 Fig, 22F 4,074,351 U.S. Patent Feb. 14, 1978 Sheet 51 of 65 4,074,351 060 < + 061 z - A B 062 A B O6E EXCHANGE ° 063 EXCHANGE |O6F | y ¥ EXCHANGE j070 AB 067 EXCHANGE 068 7 A+tR-Ce. | 073 U.S. Patent Feb. 14, 1978 Sheet 52 of 65 4,074,351 A B 077 O6B | EXCHANGE 078 SIGN Fig, 22H A-B-A 0738 A+ B-A,, [070 7 (=) U.S. Patent Feb. 14, 1978 Sheet 53 of 65 4,074,351 Fig. 221 +1 Msp? 080 SU By 081 094 oO 083 1 087 093 084 . AtipoAL Amt AE oss 086 U.S. Patent Feb. 14, 1978 Sheet 54 of 65 4,074,351 oss A+ I-An AW 1 Ag 092 OAI SET OVERFLOW OAD OA2 SLL Am Fig.22d U.S. Patent Feb. 14, 1978 Sheet 55 of 65 4,074,351 OA4 y oA a cA ons B-c¢ oag EXCHANGE E SIGN OAA Bio OAR OAF PREV OF 1 TOGGLE oac BIO OBO OAD 1 1 > ° ° Fig. 22K U.S. Patent Feb. 14, 1978 Sheet 56 of 65 4,074,351 OP4 Fig. 22L CURR OP 1 123 A B WE On-A te ( Dit ) 120 126 KPCD ( oi ) 127 SocP 122 U.S. Patent Feb. 14, 1978 Sheet 57 of 65 4,074,351 wag fig,22M 131 i SRL Au 129 At+1—A 132 ft A B A B SLL Bag 135 12c SRL By 136 12D SLL Any SLL Ay U.S. Patent Feb. 14, 1978 Sheet 58 of 65 4,074,351 OB7 RESET ¢ CONST OB! PREV Op2 ie) [ @ fo]=}] KacD OBA OBB SET c CONST AB FA;FB SIGN OoBD ops ¥ EXCHANGE 8 1 OBF SET Fig. 22N U.S. Patent Feb. 14, 1978 Sheet 59 of 65 4,074,351 Fig. 229 2 ocs 4 < | a Y oc TOGGLE 9 A+B-Ae ocs v oD3 A+B—A, TOGGLE 9 Le U.S. Patent Feb. 14, 1978 4,074,351 Sheet 60 of 65 ODA ODB c-B Cy A+ti-A. ops ops Fig, 22P ODE oD U.S. Patent Feb. 14, 1978 Sheet 61 of 65 4,074,351 A+BA BAy “ . OFS = ore OFA SRL A,, ; v M5 oF? ¢-1' Cisp Fig. 22@ U.S. Patent Feb. 14, 1978 Sheet 62 of 65 4,074,351 Fig. 22R oED a A-! Ac SLL Aw OEF ( C10 ) OoFO / , OF! SLL C,, A+i Ap oEC OF2 v v U.S. Patent Feb. 14, 1978 Sheet 63 of 65 4,074,351 108 109 104 10A A:T SRL Ay >< POST 108 105 27 , Ale <7 106 10F 6 Ag —7—~Ag ° 106 Ap ~!-Ap 10D ¥ ' SET OVERFLOW 110 Fig. 228 U.S. Patent Feb. 14, 1978 Sheet 64 of 65 4,074,351 41 RESET AE SIGN 12 OVERFLOW HA ; Fig, 22T U.S. Patent Feb. 14, 1978 Sheet 65 of 65 4,074,351 4,074,351 1 VARIABLE FUNCTION PROGRAMMED CALCULATOR This application is a continuation of Ser. No. 529,251, filed 12/2/74 (now abandoned) which was a division of 5 Ser. No. 420,999, filed 12/3/73 which is a continuation of Ser. No. 163,565, filed 7/19/71 (now abandoned). This invention relates to calculators and, more partic- ularly, to a variable function fixed program calculator capable of being fabricated as a monolithic integrated semiconductor system utilizing contemporary semicon- ductor technology. It is an object of the present invention to provide a system which functions as a basic desk top calculator. More particularly, it is an object of the invention to provide such calculator function including primitive decimal operations, such as add, subtract, multiply and divide with floating decimal point entry and either floating or fixed decimal point results on multi-digit operands. This object is accomplished in accordance with the present invention by providing, for example, a dynamic charge storage random access memory shift- ing array for registration of numeric and control data. The calculator includes a control memory such as a programmable logic array (PLA), a program memory such as a read only memory (ROM) and means for performing arithmetic and logic modification of regis- tered data including binary coded decimal (BCD), bit- parallel digit-serial decimal arithmetic, and set-reset- toggle (SRT) FLAG data modification. Another object of the invention is to provide a calcu- lator system which is capable of being fabricated as a monolithic integrated semiconductor system. More particularly, it is an object of the invention to provide such calculator system which is capable of being fabri- cated as a monolithic integrated metal-insulator-semi- conductor system utilizing contemporary metal-insula- tor-semiconductor technology. This object is accom- plished in accordance with the present invention by providing a random access memory shift register system which requires approximately one-third the area of conventional shift register systems, providing internal generation of multiphase clocks from a single phase input clock which is included in the calculator but which is external to the monolithic structure and by providing a common programmed scanning system in the monolithic structure to provide both keyboard en- coding and display decoding with minimum external connections between the monolithic system and the keyboard and display. The total number of connections from the monolithic structure to other calculator sub- systems such as the keyboard, display and power supply are therefore minimized so that the monolithic structure is capable of being packaged in a conventional twenty- eight or forty pin package. It is a further object of the present invention to pro- vide a versatile calculator system in which the calcula- tor function and input and output interfaces can be varied without changing the basic calculator structure, and particularly without changing the basic calculator structure as an integrated semiconductor system. This object is accomplished with the present invention by providing a programmable read only memory which provides a fixed program for the calculator system in accordance with the desired function of the calculator system and by providing programmable logic arrays for decoding and encoding the input, output and operating data by masking such data to any desired format. The 25 40 45 50 35 60 65 2 programmable read only memory and the programma- ble logic arrays are easily modified by changing only the gate-insulator mask for the metal-insulator-semicon- ductor integrated system embodiment during the fabri- cation process. Yet another object of the invention is to provide a calculator with improved means for encoding keyboard commands and status information and which also func- tions as a direct interface means between a display de- coder and a display for segmented and/or individual- decimal-numerical displays. This object is accom- plished in accordance with the invention by providing a programmed scanning system to service both the key- board input and display output, thereby minimizing hardware requirements for the key input system. Four keyboard input pins combine with eleven scanner out- put pins to allow a total of forty-four distinct keys and- /or switches. The programmed routine residing in the read-only memory encodes the input from the keyboard array under program control. The scanning system operates at a slow enough rate to eliminate the need for any external keyboard drive circuitry and allows direct drive of large capacitance loads with response consis- tent to the scan rate. The scan program includes an encoding routine to effectively defeat transient noise and key bounce types of interference from the key- board. An additional advantage of the keyboard scan- ning system then is that it requires few diodes, no ampli- fiers and simple switches which need not be low resis- tance or low bounce time switches. The display output includes internal segment or digit decoding, digit-blank- ing and zero suppression logic and utilizes the same scanning system as the keyboard. The display itself may be comprised of light-emitting diodes, liquid crystal, cold cathode gas discharge display elements, fluores- cent display elements, multi-digit singie-envelope cold- cathode gas-discharge tubes, incandescent display ele- ments, etc. The multiple display capability is provided by the generally defined digit scanning and segment or numeral decoding system and by providing for an inter- digit blanking signal which is variable in terms of lead- ing and trailing edge blanking intervals and in terms of its application to either the segment drivers or the digit drivers or both. The output decoder is comprised of a programmable logic array segment decoder circuit which can be programmed to accommodate any seven, eight, nine, ten segment or ten digit numerical display font plus a right or left decimal point. In this manner the calculator system of the present invention is essentially insensitive to the selection of a display which is utilized in conjunction with it. It is still a further object of the invention to provide internal means for suppression of insignificant leading zeros in the calculator display. This object is accom- plished by the programmed scanning system which provides scanning of the most significant output digits first and minimizes hardware means for detecting and suppressing leading zeros. Another object of the invention is to allow both con- stant-operand and chained-intermediate-result type of calculations in a fully algebraic manner. This object is accomplished by providing an operator selectable con- trol or mode switch to distinguish the constant-operand mode from the chained-intermediate-result mode of operation and by providing a fixed program decision routine in the read only memory array to detect the desired mode and effect it. 4,074,351 3 It is yet a further object of the invention to provide a calculator system which includes means for providing an automatic round-off solution for high accuracy in calculation. This object is accomplished in accordance with the present invention by utilizing a fixed program routine stored in the read only memory which adds the numeral five to the least significant digit which is to be lost. In this manner, a one is added to the second least significant digit which is to be kept when the least sig- nificant digit which is to be lost is greater than or equal to five. Another object of the invention is to provide a calcu- lator system with minimum power dissipation in order to provide a uniquely portable desk top calculator with good battery life. This object is accomplished in accor- dance with the present invention by provision of special control circuits to turn off dissipating functional ele- ments except when such functional elements are actu- ally being used and by provision of special pre-charge ratioless circuits within an metal-insulator-semiconduc- tor embodiment of the read only memory, programma- ble logic array and arithmetic logic unit functional sub- systems. For example, the instruction output from the read only memory need be detected only once per in- struction cycle; a power control is applied to the read only memory decoder effecting a duty cycle of 2/13ths of the nominal static power dissipation to eliminate DC currents so that only transient CV?f power is disipated. Still further objects and advantages of the invention will be apparent from the following detailed description and claims and from the accompanying drawings illus- trative of the invention wherein: FIGS. 1 and 2 are block diagrams illustrating the calculator system of the present invention; FIG. 3 is a block diagram functionally describing data block 204 of one embodiment of the calculator system of the invention; FIG. 4 is a block diagram of the FLAG registers illustrating the operation thereof; FIG. 5 is a symbolic representation of the basic com- mand word format and instruction map utilized in an embodiment of the calculator system; FIG. 6 is a graph illustrating the basic instruction cycle timing for the calculator system; FIG. 7 is a graph representing the scan cycle timing for the keyboard and display scan and relates the scan cycle to the instruction cycle timing period; FIG. 8 is a representation of the data format for the A register, B register, C register, FA FLAG register, FB FLAG register and display; FIG. 9 is a graph representing the keyboard program timing showing that the input-sensing program provides protection against transient noise, double-entry, lead- ing-edge bounce and trailing-edge bounce; FIGS. 10 and 11 are planar diagrams showing exem- plary calculator keyboards utilized in conjunction with the present calculator system; FIG. 12 is a circuit diagram of the display element showing the input and output connections to the digit scanning circuits; FIG. 13 is a diagram showing a representative display font of a display utilized in conjunction with an embodi- ment of the present invention; FIG. 14 is a graph showing how the segment drive includes the digit drive of an embodiment of the inven- tion; 4 FIG. 15 is a circuit diagram of an interface circuit * between the display elements and the scanning circuits in an embodiment of the present invention; FIG. 16 is a circuit representation of a keyboard 5 utilized in conjunction with the described calculator embodiment including the interconnections to the scan- ning circuits; FIG. 17 is a logic and circuit diagram of a metal- insulator-semiconductor embodiment of the calculator system of the invention which is further comprised of FIGS. 17A-Z; FIGS. 18A-D are diagrams showing the metal- insulator-semiconductor circuit equivalents of various logic gates shown in FIG. 17; FIG. 19 is a circuit diagram illustrating the metal- insulator-semiconductor equivalent circuits of shift reg- ister cells $41 utilized in the commutator of the random access memory array shift register system utilized in the embodiment of FIG. 17; FIG. 20 is a circuit diagram illustrating the metal- insulator-semiconductor driver circuit for the shift reg- ister cells of FIG. 19; FIG. 21 is a diagram illustrating the circuit equiva- lents of the programmable logic arrays (PLA) utilized in the embodiment of FIG. 17; FIGS. 22A-T are flow charts showing the programs stored in the programmable read only memory of an embodiment of the calculator system to provide desk top calculator functions including floating decimal point operation, input routines and output routines; and FIG. 23 is a planar view of the packaged monolithic structure showing terminal interconnects to the key- board, display drivers and power supply. According to the present invention a variable func- tion programmed calculator which includes a fixed program stored in a read only memory is capable of being fabricated as a monolithic integrated semiconduc- tor system. In particular, the described embodiment is capable of being fabricated as a monolithic integrated: metal-insulator-semiconductor system utilizing contem- porary metal-insulator-semiconductor technology. The calculator system may be programmed to perform desk top calculator functions including floating decimal point operation or may be programmed to perform other useful operations. A monolithic structure of the calculator system includes a fixed program which is programmed in the programmable read only memory by modifying one of five or seven masks (the gate- insulator mask) during the fabrication process. In addi- tion, the input, output and operating format of data within the calculator system is programmable in pro- grammable logic arrays by altering the same masks. In the following sections the calculator system is first de- scribed in terms of the functional relationship between its various subsystems, then in terms of specific circuits and finally in terms of the fixed programs stored in the read only memory. FUNCTIONAL DESCRIPTION OF THE CALCULATOR SYSTEM Referring to FIGS. 1 and 2, the calculator system of the present invention is illustrated in terms of the func- tional dependence among five internal functional sub- systems of the calculator system and the relation be- tween the internal functional subsystems and external functional elements. Program block 201 comprises a read only memory (ROM) 208 for storing fixed pro- grams to operate the calculator in a desired manner and 30 35 45 65 4,074,351 5 program counter (PC) 209. Control block 202 com- prises instruction register (IR) 190 for storing a control instruction, control decoders 191 for decoding control instructions and jump condition circuit 192. Timing block 203 comprises a clock generator 143, a timing generator 194, digit and FLAG mask decoders 195, and key input logic 196. Data block 204 comprises random access memory shift register system and FLAG data storage array 206, decimal arithmetic unit 207 and FLAG logic unit 229 (see FIG. 17N). Output block 205 comprises segment output decoder 198 and digit scan- ner outputs 197. DATA BLOCK’ 204 Referring to FIG. 3, a functional description of data block 204 is described in detail. Data block 204 includes means for providing decimal or hexadecimal data stor- age and means for providing basic operations. The stor- age structure of the present embodiment is parallel for decimal or hexadecimal digits; therefore, each intercon- nect 210 coupling the various functional elements sym- bolize four physical interconnections. A register 211, B register 212 and C register 213 of memory array shift register system 206 comprise the primary decimal or hexadecimal storage means for the calculator logic unit. 1-bit dynamic shift register delay circuits 214 are uti- lized to provide recirculating refresh of primary regis- ters 211, 212 and 213. The outputs of A register 211 and C register 213 are input to the U selector 215. The out- put of B register 212 and a constant N provided by means 223 are input to V selector 216. A binary or binary coded decimal (BCD) adder 217 calculates the sum or difference between U and V, i.e, U + V or U — YV. U is the plus side of the adder; V is the minus side of the adder. A = data selector 218 provides means for short and long path shifting operations. An output from adder 217 to an input of = data selector 218 corresponds to the normal path in which no shift is provided. The delayed adder input 225 to = data selector 218 corre- sponds to the long path in which a left shift is provided. The UV logical OR-gate 224 input to 2 data selector 218 corresponds to a short path which provides for a right shift. Data selector 219 selects the input to A register 211 as either the = output of data selector 218 or the delayed B register 212 output or the delayed A register output. Data selector 220 selects the input to the B register as either the £ output of % data selector 218 or the delayed A register 211 output or the delayed B register 212 output. Data selector 221 selects the input to the C register as either the = output of 2 data selector 218 or the delayed C register 213 output. Jump condi- tion latch circuit 192 is loaded with the carry-borrow output of adder 217. A register 211, B register 212 and C register 213 each provide dynamic recirculating storage for thirteen deci- mal or hexadecimal digits in the present embodiment. Adder 217, U data selector 215, V data selector 216, = data selector 218, A data selector 219, B data selector 220 and C data selector 221 provide means for arithme- tic and logical modification of the contents of registers 211, 212 and 213 by synchronous operation of selector and adder controls which is henceforth described in detail in the section describing control block 202. Referring to FIG. 4, the contents of data block 204 is illustrated with respect to 1-bit status or FLAG element storage and operation. The coupling of the functional elements is indicated by interconnects 230. Two 12-bit registers FA register 226 and FB register 227 provide 15 20 25 35 45 55 65 6 means for storage of status or FLAG information. The outputs of FA register 226 and FB register 227 are delayed by 1-bit by means of dynamic shift register elements 228 before being input to FLAG operation logic unit 229. The A and B outputs of FLAG operation logic unit 229 are coupled to FLAG registers 226 and 227. Operations of FLAG operation logic unit 229 in- clude recirculation, set, reset and toggle of individually addressed FLAGs; and, exchange and compare of FA and FB pairs of FLAGs. Controls SUB, FFLG, RFLG, SFLG, SLAG, and XFLAG are generated to perform the desired operation on a particular addressed FLAG or pair of FLAGs. The operation compare FLAG and the operation test FLAG result in an output from FLAG operation unit 229 to condition circuit 192. The control mechanism for these FLAG operations are henceforth described in detail in the section describing control block 202 below. CONTROL BLOCK 202 The functions of control block 202 are to accept instruction words from program control block 201, interpret the instruction word and a condition flip-flop as a command word for a subsequent instruction cycle and decode certain controls which operate data selec- tors and logic units in data block 204, program block 201 and output block 205. The basic command word format and instruction map are illustrated in FIG. 5. Referring to FIG. 5, I-bit 230 distinguishes jump from non-jump instructions. When I-bit 230 is a logical 0, then the instruction is a jump instruction and M-bit 231 distinguishes between true and false conditional jumps while the remaining bits of M field 232, S field 233, R field 234 and & field 235 contain the absolute address associated with the jump. When the instruction is a jump instruction (as indicated by a logical 0 being in the I-bit), but the jump condition is not satisfied, then ordinary incrementation of the program counter is effected. When the I-bit is a logical 1, then either a register or a FLAG operation is de- coded; the entire M field 232 is used to distinguish regis- ter from FLAG operations as detailed in TABLE I below. When the binary code contained in M field 232 is between 0 and 9, a register operation is decoded; when the binary code contained in M field 232 is be- tween 10 and 15, a FLAG operation is decoded. In the case of register operations, the 10 codes M = O through M = 9 are used to select one of 6 digit masks in combination with one of 3 constant values (N). The assignment of the 6 masks and 3 constants depends upon the desired data word format. The selections shown in TABLE I are utilized in the programming of a floating point decimal calculator function in accordance with the present invention. In the case of the FLAG operation, the 6 codes M = 10 through M = 15 are used to distinguish 6 FLAG codes, that is, compare, exchange, set, reset, toggle and test. S-bit 233 of the command word controls three func- tional elements in data block 204. S-bit 233 distinguishes add from subtract in binary or BCD adder 217, distin- guishes left shift from right shift in the = shift logic and distinguishes A from B in the FLAG operation logic. Add, shift and FLAG operations are exclusive opera- tions and therefore require no further decoding. R field 234 distinguishes among arithmetic, exchange and key- board input instructions as described in conjunction with TABLE II below. When the binary value con- 4,074,351 7 tained in R field 234 is between 1 and 5, an arithmetic operation is indicated and U data selector gate 215 and V data selector gate 216 are controlled to enable the variables indicated in TABLE II as inputs to adder 217. When the binary value contained in R field 234 is equal 5 to 6, an exchange of A and B, without digit masking is enabled, bypassing adder 217 and the 2 gate 218. When the binary value contained in R . TABLE I 10 REGISTER FLAG M MASK N OPERATION 0 ALL 1 EXPONENT 2 MANTISSA 3. LSD 1-LSD 15 4 MANTISSA —L-LSD 5 MANTISSA —L-MSD 6 EXPONENT —|-EXPONENT 7 DPT 1-DPT 8 DPT 8-DPT 9 EXPONENT — 8-EXPONENT A COMPARE 20 B EXCHANGE c SET D RESET E TOGGLE F TEST 25 TABLE II ARITHMETIC EXCHANGE R U v AB 0 30 r A N 2 0 B 3 c N 4 A B 5 c B 6 A-B 7 35 TABLE III DATA SELECTORS z A B c 40 0 A B c 1 z B c 2 A z c 3 A B z 45 field 234 is 0 or 7, then an arithmetic no-op (no opera- tion) is indicated, providing means for implementation of a special class of instructions for keyboard synchroni- zation and encoding. = field 235 determines the selection of the output from = data selector 218 to A register 211, B register 212, C register 213 or none of these 2 data selector outputs. As shown in TABLE III, three codes are de- coded to enable the output of 2 data selector 218 to be input to A register 211, B register 212 and C resister 213; and the fourth code provides means for a no-op code to enable a class of keyboard synchronization and encoding instructions. Condition circuit 192 reflects the status of the calcula- tor at any given point in the execution of its fixed pro- gram. It is combined with the contents of Ma-bit 231 to determine if a jump instruction is to be executed or skipped. Condition circuit 192 is loaded with a carry- borrow (C/B) result of an arithmetic operation, the contents of any FLAG test or comparison (FA:FB) of 65 any pair of FLAGs with a common (FMSK) address, the scanned conductance (closed equals 1) of key matrix cross-points of the keyboard switches in normal scan- 35 8 ning sequence, or the value of a particular digit scanner state, for example, D11. The carry-borrow and FLAG inputs to the condition circuit provide means for convenient branch operations whereby the sequential program execution can be made dependent on results of data, on arithmetic register operations, and on the current status of the calculator system as indicated by any of a plurality of status memo- ries (FLAGs) as for example in the illustrated embodi- ment in which 26 FLAGs are available. The key matrix and digit scanner inputs to the condi- tion circuit provide means for convenient and efficient synchronization and encoding under program control of a plurality of keyboard inputs, as for example in the present illustrated embodiment, 44 inputs are available. TABLE IV shows the coding and operation of these instructions. The WAIT operations provide control means to recirculate program counter (PC) 209 at its current value (not incremented) until the WAIT condi- tion (D11, KN, or KP) is satisfied. In addition, a register operation which subtracts the numeral 1 from the man- tissa of A register 211 can be associated with the D11 WAIT condition and is associated with the KN and KP WAIT condition instructions. The logical shift and FLAG initialization instructions are also shown in TABLE IV. TIMING BLOCK 203 The function of the subsystem within timing block 203 is to generate three phase internal clocking (internal being within the monolithic structure of the preferred MOS embodiment) from an external single phase oscil- lator voltage, generate internal state and digital timing based upon the clocking inputs and provide digit and FLAG masking decoders. The basic instruction cycle timing for the calculator is illustrated in FIG. 6. The @ system timing input 240 is a square wave provided by an oscilator with approximately 50% duty cycle. The 3. internal clocks ¢,, 6) and $; provide signals 241, 242 and 243, respectively, which are derived from the system clock by means of a recirculating ring counter. With binary coded decimal parallel arithmetic utilized in accordance with the present invention, each digit of add or subtract calculation utilizes one full set of clock pulses ,, $,, and $3. The full set of clock pulses is considered a state; consider for example the first state S1 with a corresponding signal 244. There are 13 such states S1-S13 corresponding to the 13 digit circulation of registers 211-213 in data block 204. The 13 states are generated by means of a feedback shift counter. Al- though the 13 states and 13 digit registers will allow storage of 13-digit numbers, a generalized floating point notation which is more convenient from the standpoint of program storage and manipulation of data is utilized in accordance with the present invention. This is ac- complished by the masking or sub-addressing of regis- ters 211-213 to mask or isolate 6 particular fields as follows: Mantissa field 245 which has N digits, the first of which is the least significant digit (LSD), the last of which is the overflow digit (