Historical Document · 1973
The delay-line timing of the Friden calculators: a gated clock resynchronised by a sync pulse on every pass, the 16-column, 6-register, 16-bit data train, and pulse-count digits.
United States Patent (19) (11 Ragen 3,778,778 (45) Dec. 11, 1973 54) CALCULATOR WITH SELF-SYNCHRONOUS RECIRCULATING Primary Examiner-Raulfe B. Zache Attorney-Patrick J. Schlesinger, Charles R. Lep MEMORY 75) inventor: Robert A. Ragen, Hayward, Calif. 73) Assignee: The Singer Company, New York, chinsky, Warren P. Kujawa and Jay M. Cantor N.Y. (57) (22 Filed: Dec. 22, 1970 (2) Appl. No.: 100,761 ABSTRACT A self-synchronous recirculating memory for use in an electronic calculator. A serial data train having a spe cial synchronizing pulse at the leading end is continu ously recirculated through a recirculating memory Related U.S. Application Data (62) Division of Ser. No. 779,666, Nov. 29, 1968, which is comprising a dynamic storage device and portions of a division of Ser. No. 319,704, Oct. 29, 1963, Pat, No. 3,546,676. the calculator arithmetic unit. Each reappearance of the leading sync pulse at the output of the storage de 52) U.S. Cl.............................................. 340/172.5 5) Int. Cl............................................. G06f 13/02 58 Field of Search.................................. 340/172.5 vice starts the operation of the calculator timing unit. The timing unit is provided with circuitry for automat ically stopping the timing unit once a predetermined count is reached. Special circuitry places a sync pulse in the recirculating memory when no data is present (56) 3,064,241 References Cited UNITED STATES PATENTS therein. 7 Claims, 6 Drawing F 1 1/1962 Schneider.................... 3401 172.5 X aims, 6 Drawing Figures 60 - - - - - - - - - - - - - - - - - - - - - - - " " - a-- - - - - 54 - - - - - , - - - - -- - - - - - - - - - - - - 3. BIT COUNTER - - - T : ADO : LOGIC - - -y CoN Roll unt 120 - ---- --- - TT MemRY - - - UNIT / 29 - - - 2 56 454 DELAY WRITC 23 AMP t NTRY > COUNTER PHASE l SUBI. | LOGIC i ! Joe. DEC D : -33 I COUNTR PT. - - - - -- - - -- COUNTER Display unit - 9 T T.44 - - - - - - - --- First D-CT 4Tl VISUAL conney controly READOUT PATENTED DEC 11 1973 3,778,778 SHEET 2 OF 4 Z. ud DIGIT POSITIONS 52 ci, C. c.3 c.2 cl cocco C1 cec, Cacs cocco --------- - - - - ----------------- (?) ?? F. OATA FLOW -- C C4 C1 C2Cr ICO C9 LC3 C2C CO HOMC C7 - --- ---- (RAIR3 Rai| R. Ros B17 Big B3 B3, Bostol 1665 B4 by 36, 8 - - - -- - - R. d. - - --- - - -- --- - PATENTED DEC 1973 3,778,778 SET 3 Of 4 TMN ( SIGNALS C T ME - 2 R$ v go l -80 -- R J N82 R2 —- m MM w. --- - - - M - mm -------24 R2, R4 B5 l ly-95 mau--n --- n.26 — — 66 67 --- --- % - - - BO — - - - - —- PATENTED DEC 1973 3,778,778 SHEET . Of 4 — LTNITWN?IOQ §¡NWITWI.T +— – · – ~---- ----~~<!---- 1 3,778,778 CALCULATOR WITH SELF-SYNCHRONOUS RECIRCULATING MEMORY 2 Dec. 8, 1970, and assigned to the assignee of the pres ent invention, the disclosure of which is hereby incor porated by reference, In FIG. 1, the six basic units are indicated by broken This application is a division of U.S. Pat. application 5 rectangles, while the major components included in Ser. No. 779,666, filed Nov. 29, 1968, which is a divi each basic unit are indicated by solid rectangles. Inter sion of U.S. Pat, application Ser. No. 319,704 filed Oct. connections between the various components and units 29, 1963, now U.S. Pat. No. 3,546,676 issued Dec. 8, are generally indicated in FIG. 1 by solid arrowed lines. 1970. The actual structure and specific interconnections of O the components can be ascertained by reference to the SUMMARY OF THE INVENTION sections and figures of the aforementioned Ragen pa This invention comprises a self-synchronous recircu tent indicated below. In the ensuing description of FIG. lating memory for use in an electronic desktop calcula 1, those referenced figures which comprise portions of tor. The recirculating memory comprises a dynamic the logic diagram (Section 16.1) are enclosed in paren storage device, preferably an acoustic delay line, a 15 theses, while those figures which comprise portions of write means for writing data into the storage device, a the more detailed circuit diagram (Section 14.4) are read means for reading data out of the storage device, not. and a plurality of intercoupled single character regis As shown in FIG. 1, an entry unit 10 is coupled to a ters, which preferably comprise a portion of the calcu control unit 20, an arithmetic unit 30, and a display lator arithmetic unit, coupled between the read and 20 unit 40. Entry unit 10 comprises a keyboard 12 and an write means. The above elements are interconnected to encoder 14. As shown in FIGS. 182-185 (FIGS. 297, provide for serial transfer of data from the storage 298), keyboard 12, which enables operator entry of nu means via the read means to the first single character meric data and control of functions to be performed by register, parallel transfer between the single character the calculator, comprises a plurality of digit keys 0, 1, registers, and serial transfer via the write means to the 25 . . . 9, a plurality of function keys, e.g., ADD, SUB store means, all in cyclical fashion. A timing unit pro TRACT, CLEAR ALL, etc., and their associated vides data entry and recirculation timing signals for switches. Encoder 14, which serves to translate the ac controlling machine operation. tuation of various keys into signals which enable se The timing unit comprises a free running oscillator lected components of control unit 20, arithmetic unit coupled through a gate to a clock flip-flop which drives 30 30, and display unit 40, comprises the components a series of counters. A control circuit responsive to the specified in Section 16.1.5 and shown in detail in FIGS. generation of at least one of the timing signals closes 182-189, 196, 197, 225-234, and 246 (FIGS. 297, this gate. This gate is reopened by the occurrence of 298). the leading data pulse, or synchronizing pulse, at the Control unit 20, which generally produces control output of the storage device. In this way, the timing unit 35 signals which direct the flow of data through arithmetic and recirculating memory are automatically synchro unit 30 comprises a decimal point counter 22, a sub nized once for each complete pass of data through the tract logic circuit 24, an entry phase counter 26, an add recirculating memory. Further, variations in the recir logic circuit 28, and a shift control logic circuit 29. The culation period due, e.g., to thermal variations of the 40 inputs of the first four of these components are each pulse propagation time in an acoustic delay line, and coupled to encoder 14, while their outputs are each variations in the period of the timing unit due to oscilla coupled to shift control logic 29. Shift control logic 29 tor drift, have no effect on the operation of the system. is coupled to arithmetic unit 30, to display unit 40, and Special circuitry places a sync pulse into the recirculat to the input side of decimal point counter 22. The out ing memory when no data is present therein. put of entry phase counter 26 is additionally coupled to For a fuller understanding of the nature and advan 45 intensity control circuit 42 of display unit 40. tages of the invention, reference should be had to the Decimal point counter 22, which provides control following description taken in conjunction with the ac signals to shift control logic 29 during decimal align, companying drawings. multiply, and divide, comprises four flip-flops intercon 50 nected as shown in FIG. 240 (FIG. 302)) and having BRIEF DESCRIPTION OF THE DRAWINGS inputs as specified in these figures. The outputs of the FIG. 1 is a block diagram of a calculator embodying decimal point counter flip-flops are connected to vari the invention; ous portions of shift control logic 29, e.g., to the inputs FIG. 2 illustrates the data organization utilized in the of gate 40 as shown in FIG. 243 (FIG. 302). calculator of FIG, 1; Entry phase counter 26, which provides sequence FIG. 3 shows the serial data train utilized in the cal 55 control signals to add logic 28, subtract logic 24, shift culator of FIG. 1; control 29, and intensity control 42, comprises three FIGS. 4A and 4B show appropriate timing signals flip-flops interconnected as shown in FIG. 238 (FIG. used to control the operation of the calculator; and 301) and having inputs as specified in these figures. FIG. 5 is a block diagram illustrating the operation of 60 The toggle input, e.g., to EPC1 flip-flop of entry phase a preferred embodiment of the invention. counter 26 is obtained from AND-gate 28, shown in FIG. 239 (FIG. 302) which produces a toggle signal DESCRIPTION OF PREFERRED EMBODIMENT when HOME signal is generated by a timing unit 60 de FIG. 1 is a block diagram of a calculator embodying scribed below. The outputs of the entry phase counter the invention. In the ensuing description, reference is 65 flip-flops are connected to portions of add logic 28 and made to several sections and figures contained in U.S. subtract logic 24 as shown in FIG. 228, and to various Pat. application Ser. No. 319,704 filed Oct. 29, 1963 portions of shift control logic 29, e.g., to gates 74 and by R. A. Ragen, now U.S. Pat. No. 3,546,676 issued 76 which are coupled to gates 80 and 82, respectively, STATEMENT OF RELATED CASES 3 3,778,778 as shown in FIGS. 254, 255, and 257 (FIGS. 304,306). 4 in FIG. 98, is coupled to A counter 32 of arithmetic unit 30 via gate 90 as shown in FIGS. 260 and 261 Add logic 28 and subtract logic 24, which provide en abling signals to shift control logic 29 during ADD and (FIG. 306). Read amplifier 56 is also coupled to D SUBTRACT operations, comprise an add flip-flop and counter 38 of arithmetic unit 30 via gate 89 as shown a subtract flip-flop whose inputs are connected as 5 in FIGS. 260 and 261 (FIG. 306). Timing unit 60, which provides timing signals to the shown in FIG. 228 to the specified outputs of encoder 12 and entry phase counter 26, and gate 6, the inputs other five basic units, comprises six major component to which are the set outputs of the add and subtract s-an oscillator 62, a clock 64, a bit counter 66, a regis flip-flops as shown in FIG. 233. The outputs of add ter counter 67, a column counter 68, and a display logic 28 and subtract logic 24 are coupled to shift con O counter 69. Oscillator 62, shown in detail in FIG. 200, trol logic 29, e.g., via gates 15, 26, and 48 to gate 78 is coupled to clock 64 via gate 99 as shown in FIG. 284. Clock 64, in turn, is coupled to the first of a series of as shown in FIGS. 236, 239, 247, and 256 (FIGS. 30, interconnected flip-flops, the first four of which com 303, 306). Shift control logic 29, which provides several shift prise bit counter 66, as shown in FIG. 286. Bit counter control signals which control the path of data through 15 66 is coupled to register counter 67, which comprises arithmetic unit 30 during the various states of the cal the next three interconnected flip-flops as shown in culator as described below, comprises numerous logic FIGS. 286 and 288. Register counter 67 is coupled to column counter 68, which comprises the succeeding elements which are interconnected as shown in FIGS. 255-294 of the above-mentioned circuit diagram 20 four interconnected flip-flops as shown in FIG. 290. (FIGS. 297-313 of the logic diagram). For example, Column counter 68 is coupled to display counter 69 via gates 84, 86, 85, and 81 of shift control logic 29 are gates 120 and 122 as seen in FIG. 291 and gate 123 as coupled to A counter 32, B counter 34, C counter 36, shown by FIG. 293. The interconnections between the and D counter 38, respectively, as shown in FIGS. 257, various components of timing unit 60 and the other 258, and 263-275 (FIGS. 305-309). Also, gate 81 of basic units are schematically portrayed in the logic dia shift control logic 29 is coupled to the horizontal stair 25 gram (FIGS. 297-313) and specifically shown in the case generator portion of deflection control circuit 44, circuit diagram, FIGS, 225-294. Portions of timing unit 60 necessary for an understanding of the present inven as shown in FIGS. 211, 212, and 257 (FIGS. 306, 313). Arithmetic unit 30, which is coupled to the other tion are shown in FIG. 5. basic units as noted above, comprises four digisters 32, 30 Memory unit 50 together with portions of arithmetic 34, 36, and 38. As employed herein, the term digister unit 30 comprise a recirculating memory. Data repre is understood to mean any device capable of accepting senting numerical information is written onto delay line a transfer of and capable of storing a representation of 54 in the form of acoustic pulses by write amplifier 52. a digit. Such devices include shift registers and binary After traversing the delay line, the data is converted to counters adapted to receive serial or parallel digit 35 electrical pulses by read amplifier 56 and presented in transfers, whether magnetic core, conventional, cryo this form to arithmetic unit 30. In IDLE mode, when no tronic, thin film or semiconductor integrated construc arithmetic or functional operations are being per tion is employed in fabricating them. In the preferred formed, the electrical data pulses are serially read into embodiment shown in FIG. 1, digisters 32, 34, 36 and A counter 32, parallel transferred into B counter 34, 38 are counters. Each counter comprises five flip-flops 40 then parallel transferred into C counter 36, and serially interconnected in a special way and associated gates. written back onto delay line 54 by write amp 52. This Alternate interconnections are provided between the A counter 32-B counter 34-C counter 36 route through various counters so that a digit may be transferred be the arithmetic unit is termed the normal path. Data fol tween interconnected counters. The flip-flop intercon lows other paths through arithmetic unit 30 when arith nections for A counter 32, B counter 34, C counter 36, 45 metic or other functional operations are being per formed, as discussed below under the heading GEN D counter 38, as well as the between counter intercon nections, are shown in FIGS. 261-265, 266-268, ERAL OPERATION. 272-274, and 269-271, respectively. As discussed DATA ORGANIZATION more fully below, the output of read amplifier 56 of The organization of data within the recirculating memory unit 50 is coupled to the input of A counter 32 50 memory of the calculator depicted in FIG. 1 is illus and D counter 38. Further, the output of C counter 36 is coupled to write amplifier 52 of memory unit 50 via trated in FIGS. 2 and 3. FIG. 2 shows an organization gates 101 and 102 as shown in FIGS. 275 and 276 of a plurality of registers RS, RO, R1, R2, R3, and R4, each having a plurality of digit positions C0 through (FIGS. 308, 309). Display unit 40 comprises intensity control circuit 42 55 C15. As will be apparent to those skilled in the art, this which is coupled to deflection control circuit 44 and organization may be achieved in various ways. In the visual readout device 46. Intensity control circuit 42 preferred embodiment of this invention, the register or and deflection control circuit 44 comprise the compo ganization of FIG. 2 is realized by a serial data train which is recirculated through the recirculating mem nents shown in detail in FIGS. 194, 195, 207-224, and 277-283 (FIGS. 310,313), while visual readout device 60 ory. Each register is considered to be composed of a 46 comprises a cathode ray tube, the schematic for plurality of recirculating space-time compartments called cells, each of which contains a digit word of zero which is shown in FIG. 283, Memory unit 50 comprises a write amplifier 52, a to nine pulses. Each cell is associated to two groups: a delay line 54, and a read amplifier 56. Write amplifier column group and a register group. This serial data 52, which is shown in detail in FIG. 201, is coupled to 65 train is arranged, as shown in FIG. 3, with the digit posi delay line 54 as shown in FIG. 276. Delay line S4 is tions of the registers interlaced so that the cells of a coupled to read amplifier 56 in the manner illustrated given column are all located adjacent each other, while in FIG. 276. Read amplifier 56, which is shown in detail the cells of a given register are spaced at regular inter 3,778,778 5 6 vals. The order of serial progression of the cells is from for the register R2 control signal 84 of FIG. 4A. FIGS. C0 to C15 and RS to R4. This arrangement is schemati 4A and 4B thus illustrate control signals that may cor cally portrayed in FIG. 3 wherein the direction of data respond to each of the 16 time spaces B0-B15 of each flow is considered to be to the right as indicated by the register digit position and each digit position CO-C15 arrow. Column group C9, for example, includes the of each register. As will be evident to those skilled in like order digit positions of each register RS, RO, R1, the art, the total number of column, register and bit R2, R3, and R4, with the lowermost register RS digit timing signals may be selected to provide more or less position occurring first and the uppermost register R4 column cells C, register cells R, or bit cells B. In this digit position occurring last. Also, by way of example, way, the data organization may be altered to provide register group R1 includes cells COR1, C1R1, C2R1, 1 O more or less recirculating registers, registers having ad . . . , C15R1 all separated by six cells, with the lower ditional columns, etc. most column C0 digit position occurring first and the GENERAL OPERATION uppermost column C15 digit position occurring last. Each complete occurrence of the data train C0 through The general operation of the preferred embodiment C15 is followed by a HOME period 19 during which 1 5 of FIG. 1 can be best understood by assuming a prob time no signals or data occur and after which the entire lem, for example addition of the digits "2" and '7". To data train is repeated. begin, the operator actuates the digit "2" key on key In the above organization, the first column C0 con board 12. This keyboard information is translated into tains a sync pulse or signal which indicates the end of machine instruction signals by encoder circuit 14 and the HOME period and the beginning of a new serial 2 O presented to the input circuit of D counter 38 but does data train, CO-C15. The contents of column C1 digit not enter the D counter at this time. Encoder circuit 14 position are the individual sign bits corresponding to also presents decimal alignment information to decimal each numeral, if any, in associated registers RS, R0, point counter 22 and causes entry phase counter 26 to R1, R2, R3, and R4. In the preferred embodiment, a begin cycling through a predetermined program. one bit in the C1 digit position specifies a negative 2 5 If the digit "2" is the first digit of a number to be en number, while a zero bit in this position specifies a posi tered (which is true in this case), entry phase counter tive number. The digit positions of each of the remain 26 initiates a SHIFT UP, by actuating shift control logic ing columns C2-C15 contain the digits of the number, circuit 29, whereby the contents of the recirculating if any, in each associated register. registers R1, R2, R3, and R4 of the delay line memory In the preferred embodiment, each digit position uti 3 O are shifed up. This step requires a single phase of the lizes a pulse count notation such as is illustrated in FIG. field word through arithmetic unit 30 and, as discussed 3 for the ninth order C9 of the register R1. Each digit in detail, in Section 16.7.5, results in all zeros in regis position contains sixteen B0-B15 time spaces, only ter R1. The SHIFT UP is accomplished by transfer of nine of which, B2-B10, are used to provide pulse nota 3 5 the data from A counter 32 to D counter 38, and simul tions for each of the digits, zero through nine. For ex taneously from the D counter to B counter 34 during ample, a one is denoted by a pulse in the time period every R1, R2, R3, and R4 register time. It is noted that B2, a two denoted by a pulse in each time period B2 during SHIFT UP, there is no direct transfer from A and B3, a three is denoted by a pulse in each time pe counter 32 to B counter 34 during any of these register riod B2, B3, and B4, etc., with a zero being indicated times. Also, during RS and R0 register times, data fol by an absence of a pulse in the time periods B2-B10. 4. O lows the normal path from A counter 32 to B counter Thus, FIG. 3 illustrates an eight in the C9 digit position 34 to C counter 36. of the register R1. Entry phase counter 26 next initiates a SHIFT LEFT The register organization illustrated in FIG. 3 is ac R1 by actuating shift control logic 29, whereby the con cessed in an interlaced, serial manner as shown in FIO. tents of register R1 are shifted one column to the left, 4 by means of recurring control and timing signals such 4. 5 As discussed more fully in Section 16.4, this SHIFT as illustrated by FIGS 4A and 4B, Referring now to LEFT R1 first causes the data (the digit "2"), that was FIG. 4A, there is illustrated a single column C signal initially presented to the input circuit of D counter 38 80. For purposes of simplicity and clarity, only one col to be entered into the D counter, and then causes this umn signal is illustrated. As will be apparent to those data to be inserted into the memory loop at the C2R1 skilled in the art, however, the column signals will 5 O position, i.e., during Column 2, Register 1 time. SHIFT occur sequentially, there being one such signal for each LEFT R1 is accomplished by initiating a transfer from of the columns Co-C15. For each column signal, there A counter 32 to D counter 38 and simultaneously from are six independently occurring register signals 81-86, the D counter to B counter 34 during each R1 register one for each of the six registers RS, R0, R1, R2, R3, 5 5 time. At such time, there is no direct transfer from A and R4, respectively, with the register RS control signal counter 32 to B counter 34. During the remaining reg 81 occurring first in time and the register R4 control ister times (RS. R0, R2, R3, and R4) data follows the signal 86 occurring last in time as shown in FIG. 4A. As normal path. As with the SHIFT UP step, SHIFT LEFT will now be apparent, the simultaneous occurrence of R1 takes place during one pass or cycle through arith a column C signal and one register signal determines metic unit 30, the occurrence, or accessibility, of a particular digit po O After the SHIFT LEFT R1 step, the calculator re sition CO-C15 of a particular register with like order turns to the IDLE condition. Digit "2" now appears in register digit positions occurring consecutively for each the C2R1 position of the recirculating information. column. During the SHIFT UP and SHIFT LEFT procedures As discussed above, each register digit position in 6 5 and during any rearrangement or modification of the cludes sixteen B0-B15 time spaces. Access to such data contained in the respective register positions, vi time spaces is accomplished by 16 independent and sual readout device 46 is blanked. Blanking is achieved consecutively occurring signals as illustrated in FIG. 4B by applying a blanking signal from entry phase counter 3,778,778 7 26 to display intensity control circuit 42. It should be noted that, as discussed more fully in Sections 16.3 and 16.11, the register contents are displayed by visual readout device 46 during the cleared and the IDLE conditions only. At other times, entry phase counter 26 8 28 so that addition can be performed by arithmetic unit 30, Addition is performed by adding like-order digits of the data contained in registers R0 and R1 after the above-described SHIFT DOWN action. For each or der, this is accomplished by transferring the R0 digit serves to blank readout device 46. into A counter 32, inhibiting reset of the A counter, The operation of the calculator during DISPLAY and then transferring the R1 digit into A counter 32 on mode is as follows. When data which is to be displayed of the R0 digit. To illustrate, using the above exam appears in A counter 32, the data is shifted by parallel top the R0 digit "7" is first sequenced into A counter transfer or broadsiding into D counter 38. While in the 10 ple 32 from read amplifier 56. Next, the normal between D counter, this data controls display intensity control resetting of the A counter to zero is inhibited circuit 42, so that the proper segments that are neces transfer shift control logic 29 in response to an enabling sig sary to trace out the digit on the screen of the cathode by ray tube display are selected and intensified for visual 15 nal from add logic 28. Then, the R1 digit "2" is se quenced into A counter 32. Since A counter 32 still readout. the count of seven at the beginning of this lat Display deflection control circuit 44 deflects the contains ter step, of this latter sequencing is a count electron beam of the cathode ray tube display so that of nine (7ther-result 2 = 9) in the A counter. This resulting the beam traverses the configuration of a figure eight the sum of the two digits, is then transferred in the and a decimal point for each column position of each 20 digit, normal way to B counter 34, then to C counter 36, etc. register to be displayed. However, only those segments The sequence A-inhibit reset A-sequence A that correspond to the digit in the D counter will be in actionabove is followed for all orders C2-C14 to the RO and tensified, while the other segments or strokes of the R1 register digits, and is accomplished in one pass of electron beam will be blanked. Display intensity con the field word through the arithmetic unit 30. Upon trol circuit 42 acts to energize the cathode ray tube, 25 conclusion of the operation, the calculator re whereas display deflection control circuit 44 serves to turns automaticallyADD to IDLE condition and DISPLAY deflect the electron beam generated by the cathode ray tube. For a more detailed discussion of machine opera mode. For a more detailed discussion of machine oper ation during ADD, see Section 16.7.9. tion during the DISPLAY mode, see Section 16.11. After entry of the digit "2", the ENTER key of the 30 To simplify illustration of the SUBTRACT operation, keyboard is depressed. Actuation of this key establishes assume that digit words representing a minuend and a have already been entered in registers R2 that the last digit of a number has been entered into the subtrahend and R1, respectively, and decimal aligned, in the man memory unit. In this example, "2" is the first and last digit of the number. Entry phase counter 26 then ner described above. The operator then actuates the function key, which action is translated by causes shift control logic 29 to deciaml align the num 35 SUBTRACT encoder circuit 14 into machine commands. One out ber now entered in register R1. The operator next inserts the next digit word, which put signal from encoder circuit 14 triggers entry phase counter 26, which causes the decimally aligned con in this example is the digit "7", and the calculator fol tents of registers R1,R2, R3, and R4 to be shifted down lows the same format as set forth above. In this case, one register in the same manner as has been de during the SHIFT UP step, the digit word "2" is shifted 40 by above in the discussion of the ADD operation up from register R1 to the next register R2, and then scribed so that the minuend and subtrahend are shifted into the the digit word "7" is entered into register R1. R1 and R0 (M/D) registers, respectively. Next, entry The operator then actuates the ADD function key in phase counter 26 actuates subtract logic circuit 24 so order to effectuate a summation of the digits '2' and subtraction can be performed by arithmetic unit "7". When the ADD key is actuated, encoder circuit 45 that 30, 14 translates this action into machine commands. One is performed by complementary addition ouptut signal from encoder circuit 14 triggers entry ofSubtraction like-order R0 and R1 digits, that is, each R1 digit is phase counter 26 to cycle through a predetermined added to the complement of each like-order R0 digit. program, which is built into the machine. accomplished as follows. In response to an en The first step of the ADD program is decimal align SO This is signal from subtract logic 24, shift control logic ment, if necessary. This alignment is controlled by shift abling 29 causes the digit from read amp 56 to sequence control logic 29 and decimal point counter 22. Shift D counter 38. R0 as described in Section 16.2.6, D control logic 29 shifts information in the R1 register to counter 38 is aSince, recedable this sequencing of the left, until decimal point counter 22 determines that the D counter results in the digister, complement of the R0 digit the number in register R1 is decimally aligned. For a 55 being developed in D counter 38. The complemented more detailed discussion of machine operation during R0 digit is then parallel transferred or broadsided into decimal alignment, see Section 16.6. A counter 32. The R1 digit is next sequenced into the Entry phase counter 26 next causes the information counter on top of the complemented R0 digit. The in Registers R1, R2, R3, and R4 to be shifted down by Aresulting digit, representing the remainder or differ one register. The SHIFT DOWN action is controlled by 60 ence between the original, like-order R1 and R0 digits, shift control logic 29, which causes a direct transfer is then transferred in the normal way to B counter 34, from A counter 32 to C counter 36 during R1, R2, R3, then to C counter 36, This action is followed for all and R4 register times. As a result, the two digit words orders C2-C14 of theetc. R0 and R1 register digits and is or numbers '2' and '7' which are to be added are in one pass of the field word through placed in the R1 and R0 (M/D) registers, respectively. 65 accomplished unit 30. For a more detailed discussion of machine operation arithmetic the end of this pass, if originally the subtrahend during this SHIFT DOWN action, see Section 16.7.3. wasAtlarger than the minuend, the contents of the R1 Entry phase counter 26 then activates add logic circuit 3,778,778 9 10 register will represent the complement of the desired SHIFT LEFT R1 and SHIFT LEFT R2, after the origi answer. In such a case, shift control logic 29, in re nal LSDR2 has been placed in D counter 38 and the D sponse to an enabling signal from subtract logic 24, counter has been receded to zero, the product of the causes R1 data to be complemented and the arithmetic original multiplier and multiplicand will be located in sign to be changed during a second pass of the field 5 register R2. word through arithmetic unit 30. The arithmetic sign of Entry phase counter 26 then causes shift logic 29 to the R1 data is changed by adding one to the C1R1 digit shift down the contents of registers R2, R3, and R4 by position (the sign digit position). The R1 data is com one register. With the product now located in register plemented by sequencing D counter 38 directly from R1, and the MULTIPLY operation completed, the cal read amplifier 56 for each R1 digit. As noted above, se O culator returns automatically to IDLE condition and quencing the D counter causes the complement of the DISPLAY mode. For a more detailed discussion of ma sequencing digit to be developed in D counter 38. This chine operation during MULTIPLY, see Sections complemented digit is then parallel transferred to B 16.7.4 and 16.8. counter 34, while the normal A counter to B counter To simplify illustration of the DIVIDE operation, as transfer is simultaneously inhibited by shift logic 29. 15 sume that digit words representing a dividend and a di From B counter 34, the complemented R1 digit is visor have already been entered in registers R2 and R1, transferred to C counter 36 in the normal way. After respectively, decimal aligned. The operator then the R1 data has been complemented, the calculator re actuates the and DIVIDE function key, which action is turns automatically to IDLE condition and DISPLAY translated encoder circuit 14 into machine com mode. For a more detailed discussion of machine oper 20 mands. Onebyoutput signal from encoder circuit 14 trig ation during SUBTRACT, see Sections 16.7.10 and gers entry phase counter 26, which directs shift control 16.7.1. logic 29 to shift the decimally aligned contents of regis To simplify illustration of the MULTIPLY operation, ter down into the R0 register, and clear the R1 reg assume that digit words representing a multiplier and a ister.R1This in the same manner as discussed 25 multiplicand have already been entered in registers R2 above in theis achieved description of the MULTIPLY operation, and R1, respectively, and decimal aligned. The opera Division is performed by subtraction of the tor then actuates the MULTIPLY function key, which divisor in register R0 from repeated the dividend which is pro action is translated by encoder 14 into machine com gressively shifted from register R2 into register R1 and mands. One output signal from encoder circuit 14 trig gers entry phase counter 26, which directs shift control 30 counting the number of successful subtractions. Sub traction is performed by complementary addition as de logic 29 to shift the decimally aligned contents of regis scribed in the discussion of the SUBTRACT ter R1 down into the R0 register, and clear the R1 reg operation.above During the DIVIDE operation, the contents ister. This is achieved by transferring data from A counter 32 to C counter 36 during each R1 register of register R0 are subtracted from the contents of regis 35 ter R1 and "1" is added to register R2 whenever the re time and is discussed in detail in Section 16.7.12. Multiplication is performed by repeated addition of mainder in register R1 is positive. When the remainder the multiplicand in register R0 to the contents of regis is negative, entry phase counter 26 causes add logic cir ter R1 a number of times which is controlled by the cuit 28 to restore the former contents of register R1 by multiplier in register R2. This is accomplished by shift adding R0 to R1. Next, entry phase counter 26 causes ing R2 data left, leaving the highest order or most sig 40 shift logic 29 to shift the contents of register R2 one nificant R2 digit (MSDR2) in D counter 38, and using column to the left during one pass of the field word this digit to control the number of ADD cycles. During through arithmetic unit 30, leaving MSDR2 in D each ADD cycle, the contents of register R0 (the multi counter 38 at the end of the pass. Shift logic 29 then plicand) are added to the contents of register R1 (ini 45 causes the contents of register R1 to be shifted left dru tially zero). D counter 38 is sequenced after each ADD ing the next pass of the field word through arithmetic cycle is completed. When the digit in the D counter has unit 30. At the beginning of this data pass, the digit in been receded or counted down to zero, shift logic 29 D counter 38 (MSDR2) is placed in the least significant causes the contents of register R1 to be shifted one col digit position of register R1 (C2R1 position). After this umn to the left during one pass of the field word SO SHIFT LEFT R1 step, repetitive subtraction of R0 through arithmetic unit 30, leaving the highest order or from R1 is again performed, "1" is added to register R2 most significant R1 digit (MSDR1) in D counter 38 at for each successful subtraction until the remainder in the end of the pass. Shift logic 29 then causes the con register R1 again is negative, after which the contents tents of register R2 to be shifted left during the next of register R1 are restored and the above shifting oper pass of the field word through arithmetic unit 30. At 55 ations are again performed. the beginning of this data pass, the digit in D counter Successive series of repetitive SUBTRACT cycles 38 (MSDR1) is placed in the least significant digit and SHIFT LEFT R2 and SHIFT LEFT R1 steps are (LSD) position of register R2 (the C2R2 position), performed until the least significant digit of register R2 while the most significant R2 digit (MSDR2) is left in has been shifted into the least significant digit position the D counter at the end of this pass. This digit is then 60 of register R1, successive subtract cycles have been used to control the number of ADD cycles as described performed, a negative remainder in register R1 has above. been obtained, and the contents of register R1 have Successive series of repetitive ADD cycles and been restored. Since "1" has been added to register R2 SHIFT LEFT R1 and SHIFT LEFT R2 steps are per for each successful SUBTRACT cycle and since this formed until each digit of the original multiplier in reg 65 sum has been shifted left once during each SHIFT ister R2 has been used to control the repetitive ADD LEFT R2 step, after the final restoration of the con cycles. Since MSDR1 is relocated in LSDR2 once for tents of register R1, the quotient of the original divi each series of ADD cycles of the combined action of dend and divisor will be located in register R2. 11 3,778,778 12 Entry phase counter 26 next causes shift logic 29 to prise a scale of six counter, the permutation from the SHIFT DOWN the contents of register R2, R3, and R4 normal count of eight being provided by coupling the by one register. With the quotient now located in regis reset output of GFF 216 to the set input of FFF 215 via ter R1, and the DIVIDE operation completed, the cal an inverter 139 (FIG. 288). The various outputs of EFF culator returns automatically to IDLE condition and 214, FFF 215, and GFF 216 are sampled via gating cir cuitry, which has been omitted for clarity, to provide DISPLAY mode. For a more detailed discussion of ma chine operation during DIVIDE, see Sections 16.7.4 the six register signals 81-86 shown in FIG, 4A. The output of register counter 67, which comprises and 16.9. In addition to the above-described data handling the reset output of GFF 216, is coupled to the toggle operations and suboperations, which set forth calcula 10 input of HFF 217, the first of four serially connected tor operation during the four basic arithmetic opera flip-flops comprising column counter 68 indicated by tions of ADD, SUBTRACT, MULTIPLY, and Dl the broken lines. As will be evident to those skilled in VIDE, the calculator is also capable of performing the art, HFF 217, JFF 218, KFF 219, and LFF 220 other operations and suboperations such as RECALL (FIG. 290) comprise a scale of 16 counter. The various and STORE which are not vital to an understanding of 5 outputs of HFF 217, JFF 218, KFF 219, and LFF 220 are sampled via gating circuitry, only one of which is the simplified FIG. 1 block diagram. shown, to provide the 16 column signals Co-C15. Each SELF-SYNCHRONIZATION column signal is similar to the single column C signal FIG. 5 illustrates those portions of timing unit 60 uti 80 illustrated in FIG. 4A. The reset outputs of HFF lized to generate the timing signals of FIGS. 4A and 4B, 20 217, JFF 218, KFF 219, and LFF 220 comprise the in as well as the circuit elements which provide a self puts of inverting AND-gate 222 (FIG.291). The output synchronous recirculating memory insensitive to oscil of this gate, labeled CO SGS for CO signal source, is lator drift or thermal variation of the pulse propagation utilized to stop the timing unit in the manner described time of delay line 54 of FIG. 1. In the ensuing descrip 25 below. The elements comprising display counter 69 of tion, the reference numerals used to identify the logic timing unit 60 of the calculator of FIG. 1 are not neces gates and inverters shown in FIG. 5 have been derived sary for an understandi