Historical Document · 1972

US Patent 3,654,612: Display System Using a Cathode-Ray Tube (Takachiho Koheki, Descal)

The Descal ASI-500 display: slope and step sweeps with a ROM blanking the unused parts of each digit.

Author: Ohara and Matsuzawa / Takachiho Koheki
Year: 1972
Type: Historical Document
Credit: US Patent and Trademark Office, via Google Patents. Public domain.

O United States Patent (15) Ohara et al. (45) Apr. 4, 1972 54) DISPLAY SYSTEM USINGA CATHODERAY TUBE (72) Inventors: Katsuhiko Ohara; Kazuchiyo Matsuzawa, both of Tokyo, Japan (73) Assignee: Takachiho Koeki Kabushiki Kaisha, Komatsubara-machi, Kita-ku, Ohsaka-shi, Japan Attorney-Robert E. Burns and Emmanuel J. Lobato y 57) Japana s P & & a P a n w a 44/23982 52) U.S. Cl...........................340/172.5,340/324 A, 315/18 (51) Int Cl...................G05f 5/00, G05b 11/ 14.99gk 15/20 58) Field of Search................ 340/172.5, 324A; 315/: ife (56) 3,483,425 12/1969 Yanishevsky........... ...35/18 3,488,551 1/1970 Bryden....................................315/18 Primary Examiner-Paul J. Henon Foreign Application Priority Data Mar. 29, 1969 3,453,601 7/1969 Bogert et al........................ 340/172.5 3,476,973 1 1/1969 Chesarek et al.........................315/18 3,479,552 al................... 315/18 3,479,553 111/1969 1/1969 Tomaszewski Yanishevsky etetal... 315/18 Assistant Examiner-Jan E. Rhoads 22 Appl. Filed: No.: 22,639 Mar. 25, 1970 (21) (30) f O References Cited UNITED STATES PATENTS ABSTRACT A display system for displaying information patterns on the screen of a cathode-ray tube obtained in a logical operation device, such as a calculator, where counters and registers are commonlydevice used for the logical operation the logical operation andboth the display operation of theofsystem. The average DC values of the inputs to the vertical signal amplifier and the horizontal signal amplifier for the cathode-ray tube are maintained at stable values at both a period of the logical operation and a period of the display operation in order to eliminate the disturbance and fluctuation of the displayed pat tern during the transition - an instant when the operation mode of the system is switched - from logical operation to the display operation. Slope signals forthe displaying each digit 2,931,022 3/1960 Triest.................................340/324 A ....340/172.5 .340/32 A 3,403,286 9/1968 Carlock et al........................... 315/18 3,419,750 12/1968 Rothschild et al.......................315/18 3.248,725 4/1966 Low et al..... 3,320,595 5/1967 Yanishevsky..... are afterforaapredetermined time from the start of the digitgenerated display time displayed unit-pattern. 5 Claims, 16 Drawing Figures 2 BCOUNTER CONTROL CIRCUIT L-- 3,654,612 3 (). COUNTER g 4. VERTICAL S. -- 20 3. Eise SOURCE 25 15 WERICAL 2Rf to BUFFER AMP is BUFFER - 24 VERTICAL gy 2 4. 27 AMP 2 7 ORIZON ASPE 2 BUFFER GEN. AMP KEYBOARD 26 HORIZowa. SIGNAL AMR f8 horizonth P.tl. at Step COUNTER GEN. DECODER 5 19 MEMORY 12 BLANKING CIRCUIT PATENTED APR 4 1972 3, 654, 6l. 2 SHEET 1 OF 5 4.2 -92 &#300307| H_LOTNOJ 10&#10 KATSUHIKO OHARA and KAZUCHYO MATSUZAWA INVENTORS "G2.6% Atty. PATENTED APR 4 1972 3, 654, 62 SHEET 2 OF 5 DISPLAY (u-) 2 SCALE-OF-4 COUNTER SCALE-OF-20 Fig. 2 COUNTER 72 // 9./2 SCALE-OF-16 COUNTER 76 P3 T DISPLA rad 22 ? DIS PLAY(4) B Té ce ADDER-1 O/ DISPLAY (4) - VV DISPLAY (4) OV - - - - td --- - - - -- to --td ------ KATSUEITKO OHARA and KAZUCHIYO MATSUZAWA INVENTORS PATENTED APR 4 1972 3, 654, 62 SHEET 3 OF 5 | | | i | } | | | | H | | | | | | ! | + | # | | | { | | | ! ! | | | { | | | | ! | + -- -- (00) | KATSUHKO OHARA and KAZUCHIYO MATSUZAWA INVENTORS BY 64-76624, Atty. PATENTED APR 4 1972 3,654,612 SHEET 4 OF 5 Fig. 5E KATSUIHIKO. OHARA and KAZUCHIYO MATSUZAWA INVENTORS "Gavé4. Atty. PATENTED APR 4 1972 3, 654, 6, 2 SHEET S OF 5 INVENTORS KATSUHKO OHARA KAZUCHIYO MATSUZAWA 3,654,612 DISPLAYSYSTEMUSINGA CATH ODE-RAY TUBE 2 FIG. 1 is a block diagram illustrating an embodiment of this invention; BACKGROUND OF THE INVENTION FIG. 2 is block diagram illustrating an example of control This invention relates to a display system using a cathode means for counters in the system of this invention; ray tube and more particularly to a display system for display FIG. 3A is a diagram explanatory of a standard pattern used ing on the screen of a cathode-ray tube pattern information, in the system of this invention; such as numerals, corresponding to input information in a log FIG. 3B shows patterns indicative of numerals which are ical operation device, such as a calculator. displayed in the system of this invention; 10 FIG. 3C shows time charts explanatory of slope waves used DESCRIPTION OF THE PRIOR ART in the system of this invention; Display systems of this type can display a large amount of FIG. 4A is a circuit diagram illustrating an example of an information and have a display screen which is within the field adder used in the system of this invention; of view of the operator. However, the cost of the display FIG. 4B shows time charts explanatory of the logical opera system of this type is higher than the price of other display 15 tion time and the display time in the system of this invention; systems using indicator tubes, such as a Nixie tube. Ac FIGS.5A, 5B, 5C, 5D, 5E and 5F are time charts explanato cordingly, display systems of this type are usually employed in ry of the operations of the system of this invention more sophisticated calculators, whose high prices may be at FIG. 6 shows time charts explanatory of the operations of tributed to the following reasons. In a case where a cathode the system of this invention at the logical operation mode; and ray tube is employed to display numerals for a calculator etc., 20 FIGS. 7A and 7B show time charts explanatory of the registers and counters used solely for the display operation are operations of the system of this invention at an instant when provided to eliminate disturbances and fluctuations of pat the operation mode of the system is switched from the logical terns displayed on the screen of the cathode-ray tube. Other operation to the display operation. wise deflecting circuits for the cathode-ray tube comprise direct-coupling amplifiers. However, these direct-coupling 25 DESCRIPTION OF THE PREFERRED EMBODIMENTS amplifiers are necessarily provided to eliminate "drift,' with At first, the principle of the system of this invention will be complicated compensation circuitry for eliminating fluctua described. With reference to FIG. 1, the operation of the tions by deviation of temperature(i.e., a temperature-compen system of this invention is started by controlling a keyboard 5 sating network). Accordingly, the deflecting circuits become to instruct a control circuit 1 to control counters 2, 3 and 4 so 30 expensive. as to perform logical operations and display operations. In this SUMMARY OF THE INVENTION case, the counter 2 is a scale-of-four counter, the counter 3 a scale-of-20 counter, and the counter 4 a scale-of-16 counter. An object of this invention is to provide a display system Input data are applied from the keyboard 5 to a register 9 using cathode-ray tube for a logical operation device capable 35 under control of the counters 2, 3 and 4 to store the input data of reduction to practice by the use of a set of counters and re in the register 9. If instruction for calculation 'A' x 'B' (= gisters commonly used for the logical operation and the dis "C') is generated by way of example, values"A" and "B" are play operation in an alternately switched manner. respectively stored in registers 7 and 8, while the result "C" of Another object of this invention is to provide a display this calculation is stored in the register 9. A register 6 is a system using a cathode-ray tube for logical operation device 40 memory temporarily storing necessary data. Each of these capable of displaying patterns necessary for the logical opera registers for and 8 has a capacity of 16 bits. After the above tion by the use of non-direct-coupled deflection-amplifiers mentioned6, 7logical operation, the operation condition of this without fluctuation and disturbance of the displayed pattern. system is changed the operation under control of In the display system of this invention, standard pattern the control circuitto1.display Accordingly, one grand cycle of the signals, each indicative of a predetermined standard pattern, 45 operation of this invention comprises"logical operation time" are successively generated, and necessary patterns relating to and "display time' which are indicated by notations "t' and logical operations performed by the use of counters and re td respectively. counters 2, 3 and 4 are originally provided gisters are displayed on the screen of a cathode-ray tube by for the logical The operation conventional systems. However, blanking the respective standard pattern signals so as to obtain these counters 2, 3 and 4 in are used both for the logical opera the necessary patterns. In accordance with a feature of this in 50 tion and the control of display operation in the system of this vention, the aforementioned counters and registers are com invention. monly employed for the display operation and the above-men display time t, the contents of the registers 6, 7, 8 tioned logical operation, and the display function of the andIn9the are displayed on the screen of a cathode-ray tube 27 in cathode-ray tube is interrupted during the period of the logical four lines. For this display, a vertical slope wave w and a operation. However, the direct-current voltages applied 55 horizontal slope wave W. are at first generated, by the use of respectively to the deflection amplifiers at the logical opera the output pulses of the counter 3, at a vertical slope generator tion time are respectively adjusted so as to be equal to the 11 and a horizontal slope generator 12 respectively as stan respective average DC value of the voltages applied to the dard pattern signals which are successively generated and deflection amplifiers at the display time. Moreover, the 60 each representative of a standard pattern generating time of each of the standard pattern signals is determined so as to be shorter than a display time for a unit displayed pattern and so as to be slightly delayed from the shown in FIG. 3A. The output pulses of the counter 3 are start of the display time. As a result of the above construction, synchronized with successive changes of the counting state of fluctuations on the displayed pattern are effectively 65 the counter 3. The vertical slope wave w is applied through a eliminated, and deflecting circuitry can be constructed buffer amplifier 15 to a V-adder 20 and added to a vertical without use of the aforementioned direct-coupling amplifiers step wave wa of four steps which is generated at a vertical step having such defects. generator 14 in response to the output pulses of the counter 2. BRIEF DESCRIPTION OF THE DRAWENGS These output pulses of the counter 2 are synchronized with 70 successive changes of the counting states of this counter 2. The principle of the invention will be better understood vertical step wave wa is employed to successively switch from the following more detailed discussion in conjunction The lines of the displayed pattern of numerals. On the other hand, with the accompanying drawings, in which the same or the slope wave w, is applied through a buffer ampli equivalent parts are designated by the same or equivalent nu fier horizontal 17 to a H-adder 22 and added to both the vertical slope 75 merals, characters, and symbols, and in which: wave wi applied through a buffer amplifier 16 and a horizontal 3 3,654,612 4. step wave w of 16 steps which is generated at a horizontal step generator 18 in response to the output pulses of the second counting pulse train P, are applied from the terminal Ts and a terminal Ts. The outputs of the AND gates Ga and G counter 4. These output pulses of the counter 4 are are to the counter 3 through the OR circuit OR. At synchronized with successive changes of the counting states of the applied input side of the counter 4 (i.e., a scale-of 16 counter), this counter 4. The horizontal step wave w is employed to AND gates Gs and G8 and an OR circuit ORs are provided. To switch digits of the displayed pattern of numerals. The vertical the AND gate Gs, the signal DISPLAY (ws), the clock pulses slope wave w applied to the H-adder 22 is employed to incline CP and the carry output of the counter 3 are applied from the the displayed patterns of numerals with respect to the vertical terminals T, and the counter 3 respectively. To the direction of the displayed pattern. The output of the V-adder AND gateTGs,and the signal DISPLAY (ws) and a third counting 20 and the output of the H-adder 22 are applied to deflection 10 pulse train Pa are applied from the terminal Ta and a terminal coils of a cathode-ray tube 27 through a vertical signal amplifi Ts. The outputs of the AND Gs and Gs are applied to the er 25 and a horizontal signal amplifier 26 respectively to dis counter 4 through the OR gates gate OR3. above-mentioned play standard patterns on the screen of the cathode-ray tube AND gates G, G, G, G, G and Gs,The the OR circuits OR, 27 without blanking signals. and ORs and the terminals T, T2, Ta, T, Ts and Ts are On the other hand, the contents of the registers 6,7,8 and 9 15 OR provided in the control circuit 1 shown in FIG. 1. are successively read out, for one digit of four bits, to a buffer Operations of the counter 2,3 and 4 at the logical operation register 10 from the least significant bit positions of each re time to are as follows. At this time, the signal DISPLAY (ws) gister and applied to a decoder 13, in which each digit read are applied to the AND gates G, G and Gs, so that all the out is decoded. The decoded output of the decoder 13 is ap 20 AND gates G, G and Gs are opened. The terminal T, is cou plied to a read-only memory 19 storing blanking signals, so pled with terminal T in the control circuit 1, so that the that one of the stored blanking signals corresponding to the first pulse the train Pi corresponds to the clock pulses CP. Ac decoded output of the decoder 13 is applied from the read cordingly, the counter 2 counts the number of clock pulses only memory 19 to a blanking circuit 23. This blanking circuit CP. Four counting states (BC-1, BC=2, BC-3 and BC=4) are 23 controls the cathode-ray tube 27 to blank the unnecessary 25 employed to indicate four bits of each digit. For example, a parts (shown by dotted line in each numeral pattern in FIG. digit designated by one true at the counting state BC-Fi and 3B) of the above-mentioned standard pattern so as to obtain a the three falses at the counting states BC-2, BC=3 and BC=4 pattern of numeral (shown in FIG. 3B) corresponding to the corresponds to a decimal number '1', while a digit designated digits read out from of the registers 6, 7, 8 or 9. by one true at the counting state "BC=2' and three falses at In the above-mentioned operations, the displayed patterns 30 the counting states BC=1, BC-3 and BC= 4 corresponds to a of numerals are disturbed or fluctuated at the switching in number "2." The carry pulses of the counter 2 are ap stant from the logical operation time to to the display time to decimal plied to the terminal Ts as the second pulse train P. in the con due to the time constants of the deflection circuits (25 and 26) trol circuit 1. The number of pulses of the second pulse train and the deflection coil of the cathode-ray tube 27. To P is counted by the counter 3. Twenty counting states eliminate the disturbance and fluctuation of the displayed pat 35 (DC-1, ... DC-20) of the counter 3 are employed to tern, a signal DISPLAY (ws) shown in FIG. 4B is applied to an determineDC-2, ordinal numbers of digits. For example, serial date inverter 21 to obtain a signal DISPLAY (ws) shown in FIG. obtained at the outputs of the registers 6,7,8 and 9 at the 4B. The signal w is applied to both the V-adder 20 and the H counting state (DC-1) are determined as a first digit. adder 22 to maintain, at respective stable values, the respec Similarly, serial date obtained at outputs of the registers 6,7,8 tive direct-current average voltages of the inputs of the 40 and 9 at the counting (DC-16) are determined as a 16th horizontal signal amplifier 26 and the vertical signal amplifier digit. The counter 4 isstate employed counting the number of 25 at both the logical operation time to and the display time tip. shifts so as to detect how many for digits are shifted in the re Moreover, the starts of the slope waves w and we are delayed gisters from lower to higher. Accordingly, the pulse train P is by four clock pulses from the start of a display time to for a dis applied to the terminal Ts from the control circuit 1 when the played unit-pattern, so that a digit to be displayed at a just-suc 45 number of shifts is to be detected. The 16 counting states of ceeding digit display time t is read out to the buffer register the counter 4 are called as SC=0, SC=1,... and SC-15. 10 from one of the register 6, 7, 8 and 9. Thus the principal Moreover, the counter 4 is reset to the counting states SC=0 feature of this invention is that the signal DISPLAY (ws) and except necessary times. In FIG. 6 time charts for the counting its inverted signal DISPLAY (ws) are applied to the adders 20 50 states of the counters 2,3 and clock pulses CP are shown. In and 22 so as to maintain, at respectively stable values, the the display the counters 2, 3 and 4 operates as men respective average DC value of voltages of the inputs of the tioned below.time, FIGS. 7A and 7B show the clock pulses CP, horizontal signal amplifier 26 and the vertical signal amplifier states the counters 2,3 and 4 and the signal DISPLAY (ws) 25 at both the logical operation time to and the display time to, at an ofinstant the operation mode of the system is and that a digit to be displayed at a succeeding digit display 55 switched from when the logical operation time to to the display time t is read out to the buffer register 10 at the delayed time operation time tip. When states and BC-4 are timed it (e.g., a time of four clock pulses) to eliminate the effect with one of the clock pulses CP DC-20 at the logical operation time caused by the time constant of the deflection circuit of the after completion of operations caused by instructions by the cathode-ray tube 27. The operation of this construction will keyboard 5, the signal DISPLAY (ws) and the signal DIS. be described in detail below. PLAY (ws) become true and false respectively. Accordingly, With reference to FIG. 2, operations of the counters 2, 3 60 the gates G2, G4 and G6 are closed white the gates G. Ga and and 4 will be described in detail. At the input side of the counter 2 (i.e., a scale-of-4 counter), AND gates G and G2 Gs are opened. The scale-of-20 counter 3 counts the clock pulses CP ap and an OR gate OR are provided. To the AND gate G1, the plied the AND gate Ga opened by the signal DIS signal DISPLAY (ws), clock pulses CP, and the carry outputs 65 PLAYthrough (ws). In this case, a time for the four counting states of the counters 3 and 4 are applied from terminals T, and T. representative of “1,'"2' '3' and "4" (hereinafter called as and counters 3 and 4 respectively. To the AND gate G2, the DCs, DC-2, DC-3 and DC-4) of this counter 3 cor signal DISPLAY (ws) and a first counting pulse train P are responds to the time t, for out a digit from one of the applied from terminals Ta and T. The outputs of the AND registers 6, 7, 8 and 9 to thereading buffer register 10. A time for the gates G and G, are applied to the counter 2 through the OR 70 thirteen counting states representative of “5” to "17' gate OR. At the inputside of the counter 3 (i.e.; a scale-of-20 next (hereinafter called as DC-5, ... DC-17) of this counter 3 is counter), AND gates Ga and G and an OR gate OR2 are pro the display time to for generating the slope waves w and wa, vided. To the AND gate Ga, the signal DISPLAY (ws) and the while a time for the last three counting states representative of clock pulses CP are applied from the terminals T and T2 “18," "19" and "20" (i.e.; DC=18, DCs19, and DC-20) of respectively. To the gate G, the signal DISPLAY (ws) and a 75 the counter 3 corresponds to an idle time t. Accordingly, a S 3,654,612 carry pulse of the counter 3 indicates the completion of dis play for one digit. The carry output of the counter 3 is applied to the AND gate Gs together with the signal DISPLAY (ws) and the clock pulses CP. Accordingly, the scale-of-16 counter 4 counts the 6 The adder 22 comprises an ADDER-1 and and ADDER-2. The ADDER-1 comprises a diode D, resistors R and R con nected together to a common junction J, to combine the signal DISPLAY (ws) supplied from a terminal Ts (connected to the inverter 21), the horizontal step wave w applied from a ter minal T (connected to the horizontal step generator 18) as pulses of the counter 3. Accordingly, the count-up of the counter 4 indicates the completion of display for sixteen digits shown in FIG. 5A, and the horizontal slope wave w, applied from a terminal To (connected to the buffer amplifier 17). displayed in one line of the displayed pattern. The carry output of the counter 4 is applied to the AND 10 The output of the buffer amplifier 16 is applied to the com gate G together with the signal DISPLAY (ws), the clock pull mon junction J through a resistor. However, this connection ses CP and the carry output of the counter 3. Accordingly, the means is not shown in FIG. 4A for simple illustration. The signal DISPLAY (ws) assumes zero volt (OV) at the display scale-of-4 counter 2 counts the number of lines of the dis time to and a predetermined plus voltage (+VV) at the logical played pattern by counting the number of carry pulses of the operation time to as shown in FIG. 4B. The combined output counter 4. The four counting states of the counter 2 are em 15 ployed for designating respectively the registers 9, 8, 7 and 6 of the ADDER-1 is further combined with the signal DIS supplied from a terminal T (connected to the to be read out to the buffer register 10. Accordingly, a carry PLAYof(ws) the inverter 21) at the ADDER-2 which comprises a pulse of the counter 4 indicates the completion of display for input resister R and a series-connection of a diode D, and a resistor four lines of the displayed pattern. Rs. The resistor R and the series-connection are connected As mentioned above, the lines of displayed pattern are 20 together to a common junction J. The signal DISPLAY (ws) switched successively in response to each of the carry pulses assumes zero volt (0V) at the display time tip and a predeter of the counter 4. In this case, the bias potential in the vertical mined minus voltage (- VV) at the logical operation time to signal applied from the vertical signal amplifier 25 to the respectively. cathode-ray tube 27 must be deviated, by a large deviation voltage, in response to each of successive switching of the dis 25 As the result of the above construction of the ADDER-1 the ADDER-2, a wave on which the horizontal step wave played lines. In other words, a bias current flowing through the and w (shown in FIG. 5A) and the horizontal slope wave vertical deflection coil of the cathode-ray tube is deviated, by w(shown FIG. 3C) are combined to each other as shown in a large deviation current, in response to successive switching FIG. 5C isinobtained at the output of the ADDER-1 at the dis of the displayed lines. This deviation current has the largest time tip since the signal DISPLAY (ws) assumes the zero value at the switching from the highest line to the lowest line 30 play volt at this display time to. On the other hand, since the signal of the displayed pattern. However, the step change of the bias DISPLAY assumes also the zero volt at this display time current cannot be perfectly carried out due to transient by the tip, the wave(ws) shown in FIG. 5C is also obtained at the output of time constant of the deflection circuit and the delay of change the ADDER-2 at this display time to. of a current flowing through the vertical deflection coil. Ac If the condition of the system is changed from the display cordingly, numerals displayed at the beginning part of the 35 time to to the logical operation time to under control of the switched line are disturbed and fluctuated by the above-men control circuit 1 started in response to the keying of any key tioned transient at the switching to the next line. To eliminate on the keyboard 5, the signal DISPLAY (ws) assumes the volt these undesirable phenomena, the slope waves w and we are age --VV as shown in FIGS. 5B and 5D since the diode D generated after four clock pulses from the switching instant 40 becomes Accordingly, the output of the ADDER changed to the next line of the displayed pattern. Moreover, 1 assumesconductive. the voltage --VV as shown in FIG. 5D. On the other four bits of information can be transfered to one of the re hand, the output of the ADDER-2 assumes a constant voltage gisters 6, 7, 8 and 9 to the buffer register 10 at the time t, of determined by the resistances of the resistors Ra and R as four clock pulses. shown in FIG. 5E since voltage +VV and - VV are applied to As mentioned above, the counters 2, 3 and 4 and the re respective terminals of the resistors R and Ra through the gisters 6, 7, 8 and 9 are commonly used both for the logical 45 diodes D, and D, respectively. Accordingly, if the respective operation and for the display operation in the system of this in resistances of the resistors R and R are so determined that vention. Accordingly, the patterns are not at all displayed on the of the ADDER-2 at this logical operation time t is the screen of the cathode-ray tube 27 at the keying operation equaloutput to the average direct-current value of voltage (i.e., of the keyboard 5 for instructing data to the calculating means 50 -AV) of output of the ADDER-2 at the display time tip as illustrated in FIG. 1 by chain lines or at the logical operation in shown in the FIG. 5F, disturbance of the displayed pattern caused the above-mentioned calculating means. However, if the at the changing time from the logical operation time t to the system is so designed that the logical operation time is shorter display time tip can be eliminated. as far as possible, an operator can manipulate this system What we claim is: without embarrassment since the blanking time of the dis 55 1. A display system for displaying an information pattern in played pattern becomes very short. operation device, comprising: Next, change of condition of this system from the logical a logical a keyboard for generating instructions of an operation mode operation time to to the display time to will be described. At of a logical operation device, this time of the change of condition, if the deflection circuit for performing said logical operation in ac (25, 26) of the cathode-ray tube 27 is constructed by am 60 counters cordance with said instructions comprising a first counter plifiers without use of direct-coupling (e.g., a capacitive for generating a first timing pulse train and carry pulses, a coupling amplifier), complete change to the normal display second counter for generating carry pulses and a second condition of the entire display system is delayed due to the timing pulse train timed with each digit of the displayed time constant determined in accordance with the condition of pattern by stepping said carry pulses of the first counter, the deflection means of the cathode-ray tube 27. This delay 65 and a third counter for generating a third timing pulse for changing to the normal display condition of the entire dis train timed with each line of the displayed pattern by play system disturbs the displayed pattern, so that eyes of the stepping said carry pulses of the second counter, operators are fatigued with this disturbance of the displayed a plurality of registers for temporarily storing digital infor pattern. mation indicative of process results of said logical opera To eliminate the above-mentioned disturbance of the dis 70 tion, played pattern at the change of condition from the logical means for switching the inputs of said counters, operation time to to the display time tip, each of the adders 20 means for generating a vertical slope wave in response to and 22 are constructed as shown in FIG. 4A by way of exam the first timing pulse train, ple. In the following, the adder 22 is mainly described. How means for generating a horizontal slope wave in response to ever, the adder 20 is similar, in principle, to the adder 22. 75 the first timing pulse train, number of digits displayed by counting the number of carry 3,654,612 7 8 means for generating a vertical step wave stepped-up in 2. A display system according to claim 2, in which four of time with each pulse of the third pulse train, registers are to store four lines of said displayed pattern, means for generating a horizontal step wave stepped-up in said and the third counter is used as a scale-of-four counter. time with each pulse of the second pulse train, 3. A display system according to claim 1, in which the first a first adder for combining the vertical step wave with the 5 counter is a scale-of-20 counter with which the first four vertical slope wave, counting states are employed to read out said one digit to the a second adder for combining the horizontal step wave with buffer register, the next thirteen counting states are employed the horizontal slope wave, for generating the vertical slope wave and the horizontal slope means for maintaining the average voltages of the respec wave, and the last three counting states are employed as an tive outputs from said first and second adders at respec- 10 idle time. tively stable values irrespective of the presence of a verti 4. A display system according to claim 1, in which the cal step wave, a vertical slope wave, a horizontal slope second counter is a scale-of-n counter, so that "n" digits are wave, or a horizontal step wave at the respective inputs to displayed on one line of the displayed pattern. said first and second adders, 5. In a display system for displaying on the screen of a a cathode-ray tube comprising vertical deflection means, 15 cathode-ray tube pattern information in a logical operation horizontal deflection means, and a brightness modulation device, an improvement comprising: counters and registers means, used in common for both a logical operation of the logical a vertical signal amplifier of a non-direct coupling type for operation device and the display operation of the system, amplifying the output of said first adder for application to means for alternately switching said counters and registers the vertical deflection means of the cathode-ray tube, between periods of the logical operation and the display a horizontal signal amplifier of a non-direct coupling type operation, means for maintaining the average voltages of for amplifying the output of the second adder for applica respective inputs of a vertical signal amplifier and a horizontal tion to the horizontal deflection means of the cathode-ray signal amplifier for the cathode-ray tube at stable values in tube, both the period of logical operation and the period of the dis a buffer register for temporarily storing one digit read out 25 play operation, means for delaying, by a predetermined time, from any of said registers within a predetermined time start of slope waves for each digit from the start of a digit dis synchronized with pulses of the first timing pulse train, play time, and means for temporarily storing digital informa and tion indicative of a just-succeeding displayed digit in said means for generating a blanking signal corresponding to the predetermined time, whereby disturbance and fluctuation of digit read out of said buffer register for application to the 30 the displayed pattern at an instant when the operation mode of brightness-modulation means of the cathode-ray tube the system is switched from the logical operation to the display operation are effectively eliminated. thereby to obtain a desired display pattern on the screen of the cathode-ray tube. sk k sk. k & 35 40 45 50 55 60 65 70 75