Historical Document · 1972
A division of Ragen's master patent: the delay-line organisation, register roles and automatic decimal alignment.
United States Patent - - - 72 Inventor Robert A. Ragen 1 Appl. N E. Calif. 3. (56) References Cited UNITED STATES PATENTS 3,021,066 2/1962 Martens....................... 3,074,635 l/1963 Borne et al................... E" (1968 (45) Patented jani 1972 73 Assignee the singer Company g (11) 3,634,666 HT 235/160 235/156 2,783,455 2/1957 Hindall......................... 235/165 X A application 8 Original Oct. 29, 1963, Ser. No. 3, 166,636 3,391,391 1/1965 Simpson, Rutland etSral................ 7/1968 235/156X 235/160 X 319,704, now Patent No. 3,546,676, dated 3330546 7/1967 Scuitto Wva as . . . . . . . . . . . . . . 235/160 Dec. 8, 1970. Divided and this application Nov. 29, 1968, Ser. No. 779,666 374,106 3/1565 Urban. & F. Dal . . . . . . . . . . . . . . . . . . . . . . . . Primary Examiner-Malcolm A. Morrison 235/160 X Assistant Examiner-David H. Malzahn 54 AELECTRONIC DESK TOPCALCULATOR HAVING DELAY LINE AND AUTOMATIC DECIMAL Attorney-Charles R. Lepchinsky ALIGNMENT 27 Claims, 4 Drawing Figs. ABSTRACT: An electronic desktop calculator having a recir culating memory and an arithmetic unit comprising a plurality of single character registers, which are shared with the 52 U.S. Clorgi it. 51) int. Cl 50) Field of search . . . . . . . . . . a w8 8v8 a G06f 7/38 memory. Data shifting operations, as well as some arithmetic 235/156 operations, are performed by shifting data entered into an "56160,165, 67; 340/172 s ' ' ' '' TMNG UNIT entry register a number of digit order positions controlled by the setting in a decimal point counter. The decimal point counter is controlled by a multiposition switch and other cir cuitry actuatable by a decimal point key, -6O 62 -- 64 66 BIT 67 68 REGISTER COLUMN --- DISPLAY coUNTER counTER counTER counTER ENTRY Nii) ----- ICONTROL UNT,20, NEMORY UNIT 50 ENTRY PHASE COUNTER 94FT CONTROL A B COUNTER COUNTER LOGIC D C COUNTER - NTENSTY -- 69 DEFLECT YSUAL CONTROL e CONTROL READOUT - PATENTED JAN 1972 3,634,666 SHEET 1 OF 3 -2V (R, S DECMA POSITION THUMBWHEEL ON KEYBOARD DECMAL POSITON SGNAL GENERATOR EF B EXAMPLE OF NOTATION P(2-9)P = "THE DECIMAL POINT S IN THE SECOND OR NINTH PLACE" AI7 (2) AI7 (5) P(5-9-3)P EG - L. S. 'A PATENTEDIAN 1972 3.634,666 SHEET 3 OF 3 FIG.373 DCIMAL POSTION SIGNAL GNC2ATO2 INVENTOR. fobert (L. Ragen 3,634,666 ELECTRONIC DESK TOPCALCULATORHAVINGA DELAY LINE AND AUTOMATIC DECIMALALIGNMENT Description of the Preferred Embodiment FIG. 372 is a block diagram of a calculator embodying the invention. In the ensuing description, reference is made to several sections and figures contained in U.S. Pat. application, Ser. No. 319,704 filed Oct. 29, 1963 by R. A. Ragen now Pat. No. 3,546,636 and assigned to the assignee of the present in Statement of Related Cases This application is a division of U.S. Pat, application, Ser. No. 319,704, filed Oct. 29, 1963 now U.S. Pat. No. 3,546,676 vention, the disclosure of which is hereby incorporated by issued Dec. 8, 1970. Summary of the Invention 2 reference. 10 In FIG. 372, the six basic units of the calculators are in dicated by broken rectangles, while the major components in cluded in each basic unit are indicated by solid rectangles. In terconnections between the various components and units are The invention comprises a novel electronic desktop calcu lator having several novel features. In a first aspect, the calcu generally indicated in FIG. 372 by solid arrowed lines. The ac lator is provided with a recirculating memory for serially recir 15 tual structure and specific interconnections of the com culating a field word of data, and an arithmetic unit for per ponents can be ascertained by reference to the sections and forming data handling and arithmetic operations on the data. of the aforementioned Ragen Patent indicated below. The arithmetic unit comprises a plurality of single character figures In the ensuing description of FIG. 372, those reference figures registers, a subplurality of which are connected to provide a which comprise portions of the logic diagram (Section 16.1) normal path for progression of data through the arithmetic 20 are enclosed in parentheses, while those figures which com unit so that data cyclically emerges from the memory, nor prise portions of the more detailed circuit diagram (Section mally progresses through the arithmetic unit via this normal 14.4) are not. path, and reenters the memory, all under control of a timing As shown in FIG. 372, an entry unit 10 is coupled to a con unit. trol unit 20, an arithmetic unit 30, and a display unit 40. Entry Remaining ones of the plurality of single character registers 25 unit 10 comprises a keyboard 12, and an encoder 14. As provide alternate data paths for modifying data. One such data shown in FIGS. 182-185 (FIGS. 297, 298), keyboard 12, which enables operator entry of numeric data and control of path is provided by inserting an additional single character re gister into the normal path between two parallel connected functions to be performed by the calculator, comprises a plu single character registers. By timing this insertion properly, 30 rality of digit keys 0, 1, ... 9, a plurality of function keys, e.g., SUBTRACT, CLEAR, etc., and their associated SHIFT UP and SHIFT LEFT of various portions of the data is ADD, switches. Encoder 14, which serves to translate the actuation effected. Another such alternate data path is provided by of various keys into signals which enable selected components removing one of the single character registers from the normal control unit 20, arithmetic unit 30, and display unit 40, data path. By timing this removal properly, SHIFT DOWN of of comprises the components specified in Section 16.1.4 and various portions of the data is effected. Still other alternate 35 shown in detail in FIGS. 82-189, 196, 97, 225-234, and data paths are provided by various combinations of the single 246 (FIGS. 297,298). character registers to effect other modifications of the data. Control unit 20, which generally produces control signals In a second aspect, the calculator is provided with a decimal which direct the flow of data through arithmetic unit 30 com point control system for decimal alignment of data. All data 40 prises a decimal point counter 22, a subtract logic circuit 24, enters the calculator via an entry register. A keyboard mounted switch establishes the desired number of decimal an entry phase counter 26, an add logic circuit 28, and a shift control logic circuit 29. The inputs of the first four of these components are each coupled to encoder 14, while their out puts are each coupled to shift control logic 29. Shift control digit positions in the entry register. Actuation of any one of several function keys after digit entry causes a counter to be set to the N's complement of the number specified by the 45 logic 29 is coupled to arithmetic unit 30, to display unit 40, and to the input side of decimal point counter 22. The output keyboard switch, where N equals the total number of possible of entry phase counter 26 is additionally coupled to intensity states of the counter. Shift control logic then shifts the data in circuit 42 of display unit 49. the entry register, incrementing the counter for each order control Decimal point counter 22, which provides control signals to shift. When the counter reaches a predetermined state, the shift control logic 29 during decimal align, multiply, and di shift control logic is disabled by the counter output and 50 vide, comprises four flip-flops interconnected as shown in decimal alignment of the data is complete. FIG. 240 (FIG. 302) and having inputs as specified in these The decimal point control system further includes a figures. The outputs of the decimal point counterflip-flops are manually actuatable decimal point key for setting the counter connected to various portions of shift control logic 29, e.g., to in the manner noted above and enabling the counter to be in 55 the inputs of gate 40 as shown in FIG. 243 (FIG. 302). cremented for each decimal digit entered thereafter into the Entry phase counter 26, which provides control signals to register. add logic 28, subtract logic 24, shift control 29, and intensity A decimal interlock circuit is also provided which prevents control 42, comprises three flip-flops interconnected as shown entry of more decimal digits than the desired number of in FIG. 238 (FIG. 301) and having inputs as specified in these decimal digit positions specified by the above-noted keyboard 60 FIGS. The outputs of the entry phase counter flip-flops are switch. connected to portions of add logic 28 and subtract logic 24 as For a fuller understanding of the nature and advantages of shown in FiG. 228, and to various portions of shift control logic 29, e.g., to gates 74 and 76 which are coupled to gates 80 the invention, reference should be had to the following description taken in conjunction with the accompanying and 82, respectively, as shown in FIGS. 254, 255, and 257 drawings. Brief Description of the Drawings FIG.372 is a block diagram of the calculator embodying the 65 (FIGS. 304,306.) Add logic 28 and subtract logic 24, which provide enabling signals to shift control logic 29 during ADD and SUBTRACT operations, comprise an add flip-flop and a subtract flip-flop whose inputs are connected as shown in F.G. 228 to the invention; 70 specified outputs of encoder 12 and entry phase counter 26, FIG. 373 is a diagram illustrating the decimal point control and gate 6, the inputs to which are the set outputs of the add system; and and subtract flip-flops as shown in FIG. 233. The outputs of FIGS. 190 and 19 show the circuit and block symbol illus add logic 28 and subtract logic 24 are coupled to shift control trating the preferred embodiment of the decimal position logic 29, e.g., via gates 15, 26, and 48 to gate 78 as shown in 75 FIGS. 236,239,247, and 256 (FIGS. 301,303,306). signal generator. 3 3,634,666 Shift control logic 29, which provides several shift control signals which control the path of data through arithmetic unit 30 during the various states of the calculator as described below, comprises numerous logic elements which are inter connected as shown in FGS. 225-294 of the above-men tioned circuit diagram (FIGS. 297-313 of the logic diagram). For example, gates 84, 86, 85, and 81 of shift control logic 29 are coupled to A counter 32, B counter 34, C counter 36, and D counter 38, respectively, as shown in FIGS. 257, 258, and 4. counter 38 but does not enter the D counter at this time. En coder circuit 14 also presents decimal alignment information to decimal point counter 22 and causes entry phase counter 26 to begin cycling through a predetermined program. If the digit "2" is the first digit of a number to be entered (which is true in this case), entry phase counter 26 initiates a SHIFT UP, by actuating shift control logic circuit 29, whereby the contents of the recirculating registers R1, R2, R3, and R4 of the delay line memory are shifted up. This step requires a 263-275 (FIGS. 305-309). Also, gate 81 of shift control logic 10 single pass of the field word through arithmetic unit 230 and, 29 is coupled to the horizontal staircase generator portion of as discussed in detail, in Section 6.7.5, results in all zeros in deflection control circuit 44, as shown in FGS. 211, 212, and register R1. The SHIFT UP is accomplished by transfer of the 257 (FIGS. 306,313). data from A counter 32 to D counter 38, and simultaneously Arithmetic unit 30, which is coupled to the other basic units from the D counter to B counter 34 during every R1,R2, R3, as noted above, comprises four digisters 32, 34, 36, and 38 15 and R4 register time. It is noted that during SHIFT UP, there is which in the preferred embodiment are counters. Each no direct transfer from A counter 32 to B counter 34 during counter comprises five flip-flops interconnected in a special any of these register times. Also, during RS and RO register way and associated gates. Alternate interconnections are pro times, data follows the normal path from A counter 32 to B counter 34 to C counter 36. vided between the various counters so that a digit may be transferred between interconnected counters. The flip-flop in Entry phase counter 26 next initiates a SHIFT LEFT R1 by terconnections for A counter 32, B counter 34, C counter 36, actuating shift control logic 29, whereby the contents of re D counter 38, as well as the between counter interconnec gister R1 are shifted on column to the left. As discussed more tions, are shown in FIGS. 26-265, 266-268, 272-274, and fully in Section 16.4, this SHIFT LEFTR1 first causes the data 269-271, respectively. As discussed more fully below, the out 25 (the digit "2") that was initially presented to the input circuit put of read amplifier 56 of memory unit 50 is coupled to the of D counter 38 to be entered into the D counter, and then input of A counter 32 and D counter 38. Further, the output causes this data to be inserted into the memory loop at the of C counter 36 is coupled to write amplifier 52 of memory C2R1 position, i.e., during Column 2, Register 1 time. SHIFT unit 50 via gates 101 and 102 as shown in FIGS. 275 and 276 LEFT R1 is accomplished by initiating a transfer from A (FIGS. 308,309). 30 counter 32 to D counter 38 and simultaneously from the D Display unit 40 comprises intensity control circuit 42 which counter to B counter 34 during each R1 register time. At such is coupled to deflection control circuit 44 and visual readout time, there is no direct transfer from A counter 32 to B device 46. Intensity control circuit 42 and deflection control counter 34. During the remaining register times (RS, RO, R2, circuit 44 comprises the components shown in detail in FIGS. R3, and R4) data follows the normal path. As with the SHIFT 194, 195, 207-224, and 277-283 (FIGS. 310, 313), while 35 UP step, SHIFT LEFT R1 takes place during one pass or cycle visual readout device 46 comprises a cathode ray tube, the through arithmetic unit 30. schematic for which is shown in FIG. 283. After the SHIFT LEFTR1 step, the calculator returns to the Memory unit 50 comprises a write amplifier 52, a delay line IDLE condition. Digit "2" now appears in the C2R1 position 54, and a read amplifier 56. Write amplifier 52, which is of the recirculating information. shown in detail in FIG. 201, is coupled to delay line 54 as 40 During the SHIFT UP and SHIfT LEFT procedures and dur shown in FIG. 276. Delay line 54 is coupled to read amplifier ing any rearrangement or modification of the data contained 56 in the manner illustrated in FIGS. 276. Read amplifier 56, in the respective register positions, visual readout device 46 is which is shown in detail in FIG. 198, is coupled to A counter blanked. Blanking is achieved by applying a blanking signal 32 of arithmetic unit 30 via gate 90 as shown in FIGS. 260 and from entry phase counter 26 to display intensity control cir 261 (FIG. 306). Read amplifier 56 is also coupled to D 45 cuit 42. It should be noted that, as discussed more fully in Sec counter 38 of arithmetic unit 30 via gate 89 as shown in FIGS. tions 16.3 and 16.11, the register contents are displayed by 260 and 261 (FIGS. 306). visual readout device 46 during the cleared and the DLEcon Timing unit 60, which provides timing signals to the other ditions only. At other times, entry phase counter 26 serves to five basic units, comprises six major components-an oscilla SO blank readout device 46. tor 62, a clock 64, a bit counter 66, a register counter 67, a The operation of the calculator during DISPLAY mode is as column counter 68, and a display counter 69. Oscillator 62, follows. When data which is to be displayed appears in A shown in detail in FIG. 200, is coupled to clock 64 via gate 99 counter 32, the data is shifted by parallel transfer or broadsid as shown in FIG. 284. Clock 64, in turn, is coupled to the first ing into D counter 38. While in the D counter, this data con of a series of interconnected flip-flops, the first three of which 55 trols display intensity control circuit 42, so that the proper comprise bit counter 66, as shown in FIG. 286. Bit counter 66 segments that are necessary to trace out the digit on the screen is coupled to register counter 67, which comprises the next of the cathode-ray tube display are selected and intensified for four interconnected flip-flops as shown in FIGS. 286, and 288. visual readout. Register counter 67 is coupled to column counter 68, which Display deflection control circuit 44 deflects the electron comprises the succeeding four interconnected flip-flops as 60 beam of the cathode-ray tube display so that the beam traver shown in FIG. 290. Column counter 68 is coupled to display ses the configuration of a figure eight and a decimal point for counter 69 via gates 120 and 122 as seen in FIG. 291 and gate each column position of each register to be displayed. How 123 as shown by FIG. 293. The interconnections between the ever, only those segments that correspond to the digit in the D various components of timing unit 60 and the other basic units counter will be intensified, while the other segments or strokes are schematically portrayed in the logic diagram (FIGS. 65 of the electron beam will be blanked. Display intensity control 297-313) and specifically shown in the circuit diagram, FIGS. circuit 42 acts to energize the cathode-ray tube, whereas dis 225-294. play deflection control circuit 44 serves to deflect the electron beam generated by the cathode-ray tube. For a more detailed GENERALOPERATION discussion of machine operation during the DISPLAY mode, The general operation of the preferred embodiment of FIG. 70 see Section 16. 1. As noted above, during the IDLE condition, the flow of data ple addition of the digits "2" and "7". To begin, the operator in memory unit 50 and arithmetic unit 30 is from delay line 54 actuates the digit "2" key on keyboard 12. This keyboard in to read amplifier 56, serially to A counter 32, then parallel or formation is translated into machine instruction signals by en broadside from the A counter to B counter 34, parallel from coder circuit 14 and presented to the input circuit of D 75 the B counter to C counter 36, serially from the C counter to 372 can be best understood by assuming a problem, for exam 3,634,666 S write amplifier 52 and then back to delay line 54. In this manner, a closed memory loop is formed in which information may be cycled repeatedly. After entry of the digit "2", the ENTER key of the keyboard is depressed. Actuation of this key establishes that the last digit of a number has been entered into the memory unit. In this example, "2" is the first and last digit of the 6 down by one register in the same manner as has been described above in the discussion of the ADD operation so that the minuend and subtrahend are shifted into the R1 and R0 (M/D) registers, respectively. Next, entry phase counter 26 actuates subtract logic circuit 24 so that subtraction can be performed by arithmetic unit 30. Subtraction is performed by complementary addition of number. Entry phase counter 26 then causes shift control like-order R0 and R1 digits, that is, each R1 digit is added to logic 29 to decimal align the number now entered in register the complement of each like-order R0 digit. This is accom 10 plished as follows. In response to an enabling signal from sub R. The operator next inserts the next digit word, which in this tract logic 24, shift control logic 29 causes the R0 digit from example is the digit "7', and the calculator follows the same read amp 56 to sequence D counter 38. Since, as described in format as set forth above. In this case, during the SHIFT UP Section 16.2.6, D counter 38 is a recedable digister, this step, the digit word “2' is shifted up from register R1 to the 15 sequencing of the D counter results in the complement of the next register R2, and then the digit word '7' is entered into R0 digit being developed in D counter 38. The complemented register R1. Ro digit is then parallel transferred or broadsided into A The operator then actuates the ADD function key in order counter 32. The R1 digit is next sequenced into the A counter to effectuate a summation of the digits '2' and “7”. When the on top of the complemented R0 digit. The resulting digit, ADD key is actuated, encoder circuit 4 translates this action 20 representing the remainder or difference between the original, into machine commands. One output signal from encoder cir like-order R1 and R0 digits, is then transferred in the normal cuit 14 triggers entry phase counter 26 to cycle through a way to B counter 34, then to C counter 36, etc. This action is predetermined program, which is built into the machine. followed for all orders C2-C14 of the R0 and R1 register digits The first step of the ADD program is decimal alignment, if and is accomplished in one pass of the filed word through necessary. This alignment is controlled by shift control logic 25 arithmetic unit 30. 29 and decimal point counter 22. Shift control logic 29 shifts At the end of this pass, if originally the subtrahend was information in the R1 register to the left, until decimal point larger than the minuend, the contents of the R1 register will counter 22 determines that the number in register R1 is represent the complement of the desired answer. In such a decimally aligned. For a more detailed discussion of machine case, shift control logic 29, in response to an enabling signal operation during decimal alignment, see the discussion below 30 from subtract logic 24, causes R1 data to be complemented of FIG. 373. and the arithmetic sign to be changed during a second pass of Entry phase counter 26 next causes the information in Re the field word through arithmetic unit 30. The arithmetic sign gisters R1, R2, R3, and R4 to be shifted down by one register. of the R1 data is changed by adding one to the C1R1 digit position (the sign digit position). The R1 data is comple The SHIFT DOWN action is controlled by shift control logic 29, which causes a direct transfer from A counter 32 to C 35 mented by sequencing D counter 38 directly from read ampli counter 36 during R, R2, R3, and R4 register times. As a fier 56 for each R1 digit. As noted above, sequencing the D result, the two digit words or numbers "2' and '7' which are counter causes the complement of the sequencing digit to be to be added are placed in the R1 and R0 (M/D) registers, developed in D counter 38. This complemented digit is then respectively. For a more detailed discussion of machine opera parallel transferred to B counter 34, while the normal A 40 tion during this SHIfT DOWN action, see Section 16.7.3. Entry phase counter 26 then activates add logic circuit 28 so counter to B counter transfer is simultaneously inhibited by shift logic 29. From B counter 34, the complemented R1 digit transferring the R0 digit into A counter 32, inhibiting reset of see Sections 16.7.10 and 16.7.11. that addition can be performed by arithmetic unit 30. is transferred to C counter 36 in the normal way. After the R1 Addition is performed by adding like-order digits of the data data has been complemented, the calculator returns automati contained in registers R0 and R1 after the above-described 45 cally to IDLE condition and DISPLAY mode. For a more SHIFT DOWN action. For each order, this is accomplished by detailed discussion of machine operation during SUBTRACT, the A counter, and then transferring the R1 digit into A To simplify illustration of the MULTIPLY operation, as counter 32 on top of the RO digit. To illustrate, using the sume that digit words representing a multiplier and a mul above example the RO digit '7' is first sequenced into A tiplicand have already been entered in registers R2 and Ri, counter 32 from read amplifier 56. Next, the normal between 50 respectively, and decimal aligned. The operator then actuates transfer resetting of the A counter to zero is inhibited by shift the MULTIPLY function key, which action is translated by control logic 29 in response to an enabling signal from add encoder 14 into machine commands. One output signal from logic 28. Then, the R1 digit "2" is sequenced into A counter encoder circuit 14 triggers entry phase counter 26, which 32. Since A counter 32 still contains the count of seven at the 55 directs shift control logic 29 to shift the decimally aligned con beginning of this latter step, the result of this latter sequencing tents of register R1 down into the R0 register, and clear the R1 is a count of nine (7+2=9) in the A counter. This resulting register. This is achieved by transferring data from A counter digit, the sum of the two digits, is then transferred in the nor 32 to C counter 36 during each R1 register time and is malway to B counter 34, then to C counter 36, etc. The above discussed in detail in Section 16.7.12. sequence A-inhibit reset A-sequence A action is followed 60 Multiplication is performed by repeated addition of the for all orders C2-C14 of the RO and R1 register digits, and is multiplicand in register R0 to the contents of register R1 a accomplished in one pass of the field word through the number of times which is controlled by the multiplier in re arithmetic unit 30. Upon conclusion of the ADD operation, gister R2. This is accomplished by shifting R2 data left, leaving the calculator returns automatically to IDLE condition and the highest order or most significant R2 digit (MSDR2) in D DISPLAY mode. For a more detailed discussion of machine 65 counter 38, and using this digit to control the number of ADD cycles. During each ADD cycle, the contents of register R0 operation during ADD, see Section 16.7.9. To simplify illustration of the SUBTRACT operation, as (the multiplicand) are added to the contents of register R1 sume that digit words representing a minuend and a sub trahend have already been entered in registers R2 and R1, (initially zero). D counter 38 is sequenced after each ADD cycle is completed. When the digit in the D counter has been respectively, and decimal aligned, in the manner described 70 receded or counted down to zero, shift logic 29 causes the above. The operator then actuates the SUBTRACT function contents of register R1 to be shifted one column to the left key, which action is translated by encoder circuit 14 into during one pass of the field word through arithmetic unit 30, machine commands. One output signal from encoder circuit leaving the highest order or most significant R1 digit 14 triggers entry phase counter 26, which causes the decimally (MSDR1) in D counter 38 at the end of the pass. Shift logic 29 aligned contents of registers R1, R2, R3, and R4 to be shifted 75 then causes the contents of register R2 to be shifted left during 7 3,634,666 the next pass of the field word through arithmetic unit 30. At the beginning of this data pass, the digit in D counter 38 (MSDR1) is placed in the least significant digit (LSD) posi tion of register R2 (the C2R2 position), while the most signifi cant R2 digit (MSDR2) is left in the D counter at the end of this pass. This digit is then used to control the number of ADD cycles as described above. 8 gister. With the quotient now located in register R1, and the DIVIDE operation completed, the calculator returns auto matically to IDLE condition and DISPLAY mode. For a more detailed discussion of machine operation during DIVIDE, see In addition to the above-described data handling operations Sections 16.7.4 and 16.9. and suboperations, which set forth calculator operation during the four basic arithmetic operations of ADD, SUBTRACT, LEFT R1 and SHIFT LEFTR2 steps are performed until each MULTIPLY, and DIVIDE, the calculator is also capable of digit of the original multiplier in register R2 has been used to 10 performing other operations and suboperations such as control the repetitive ADD cycles. Since MSDR1 is relocated CLEAR ALL and STORE which are not vital to an un in LSDR2 once for each series of ADD cycles by the com derstanding of the simplified FIG.372 block diagram. bined action of SHIf T LEFT R1 and SHIFT LEFT R2, after Timing unit 60 provides the timing signals that determine the original LSDR2 has been placed in D counter 38 and the D 15 the time relations between the various operations described counter has been receded to zero, the product of the original herein. Clock circuit 64, which is driven by the output of oscil multiplier and multiplicand will be located in register R2. lator 62, produces one pulse for each bit time. These pulses Entry phase counter 26 then causes shift logic 29 to shift are applied inturn to bit counter 66, register counter 67, down the contents of registers R2, R3, and R4 by one register. column counter 68 and display counter 69, the outputs of With the product now located in register R1, and the MUL 20 each of which define a discreet time interval related to the TIPLY operation completed, the calculator returns automati presentation of the data. cally to IDLE condition and DISPLAY mode. For a more Although oscillator 62 runs continuously, the output of detailed discussion of machine operation during MULTIPLY, clock 64 is stopped by the leading portion of the first column see Sections 16.7.4 and 16.8. time, i.e., CORS register time. Clock 64 is started by the ap To simplify illustration of the DIVIDE operation, assume 25 pearance of the leading synchronization pulse each time the that digit words representing a dividend and a divisor have al data is first made available at the output end of delay line 54. ready been entered in registers R2 and R1, respectively, and In this manner, the data is synchronized so that portions Successive series of repetitive ADD cycles and SHIFT decimal aligned. The operator then actuates the DIVIDE thereof may be properly identified relative to their respective function key, which action is translated by encoder circuit 14 register positions as the data is read off delay line 54 and also into machine commands. One output signal from encoder cir 30 while the data is in the various portions of arithmetic unit 30. cuit 14 triggers entry phase counter 26, which directs shift For a more detailed discussion of this start-stop feature of tim control logic 29 to shift the decimally aligned contents of re ing system 60, see Section 16.5. gister R1 down into the R0 register, and clear the R1 register. FIG. 373 illustrated in detail those portions of the calculator This is achieved in the same manner as discussed above in the which comprise the decimal point control system for aligning 35 data entered in entry register R1 to a predetermined decimal description of the MULTIPLY operation. Division is performed by repeated subtraction of the divisor significance. In the ensuing description, the last two digits of in register R0 from the dividend which is progressively shifted the reference numerals identifying the logic gates correspond from register R2 into register R1 and counting the number of exactly to the reference numerals used to identify the same successful subtractions. Subtraction is performed by comple gates in the referenced parent Ragen application. For exam mentary addition as described above in the discussion of the 40 ple, gate 113 in the instant patent corresponds to gate 13 in SUBTRACT operation. During the DIVIDE operation, the the referenced application; gate 140 corresponds to gate 40; contents of register R0 are subtracted from the contents of re etc. In addition, the figure wherein each described element is gister R1 and 'l' is added to register R2 whenever the illustrated in the referenced application is given in parentheses remainder in register R1 is positive. When the remainder is 45 after the first reference thereto. negative, entry phase counter 26 causes add logic circuit 28 to Turning now to FIG. 373, four outputs b, d, f, and h of a restore the former contents of register R1 by adding R0 to R1. decimal position signal generator I (FIG. 190) are coupled to Next, entry phase counter 26 causes shift logic 29 to shift the the DC inputs of four AC AND-gates 100-103 (FIG. 204), contents of register R2 one column to the left during one pass respectively. The AC input to each of gates 100-103 is cou of the field word through arithmetic unit 30, leaving MSDR2 50 pled to the reset output of a decimal point storage flip-flop in D counter 38 at the end of the pass. Shift logic 29 then 105 (FIG. 232), hereinafter designated DPSFF 105, through causes the contents of register R1 to be shifted left during the inverting AND-gate 113 (FIG. 235). The output from each of next pass of the field word through arithmetic unit 30. At the gates 100-103 is coupled to the set input of flip-flops DPCl, beginning of this data pass, the digit in D counter 38 DPC2, DPC4, DPC8, respectively (FIG. 240), which together (MSDR2) is placed in the least significant digit position of re 55 comprise decimal point counter 22. Flip-flops DPC1, DPC2, gister R1 (C2R1 position). After this SHIFT LEFT R1 step, DPC4, and DPC8 are interconnected in a known way to form repetitive subtraction of R0 from R1 is again performed, "l' a scale of 16 counter. Whenever DIV SET signal goes true at is added to register R2 for each successful subtraction until the output of gate 113, each one of those gates 100-103 the remainder in register R1 again is negative, after which the whose DC input from decimal position signal generator I is contents of register R1 are restored and the above shifting 60 conditioned true will set its respective flip-flop DPC1, DPC2, operations are again performed. DPC4, or DPC8. Successive series of repetitive SUBTRACT cycles and FIG. 190 shows the preferred embodiment of decimal posi SHIf T LEFT R2 and SHIFT LEFT R1 steps are performed tion signal generator I. The semicircle shown illustrated at the until the least significant digit of register R2 has been shifted top of this figure represents a decimal position setting into the least significant digit position of register R1, succes 65 thumbwheel mounted on the calculator keyboard. This sive subtract cycles have been performed, a negative thumbwheel is connected to the shaft of a multideck rotary remainder in register R1 has bee obtained, and the contents of shaft, the shaft being represented by broken lines. Although register R1 have been restored. Since "1" has been added to eight decks E, F, G, H, J, K, L, and M are illustrated, only the register R2 for each successful SUBTRACT cycle and since E, F, G, and H decks are utilized in the invention. For the sake this sum has been shifted left once during each SHIFT LEFT 70 of brevity, the ensuing description is directed to these latter R2 step, after the final restoration of the contents of register four decks. R1, the quotient of the original dividend and divisor will be Each of the decks contain five stationary contacts labeled 0, located in register R2. 2, 5, 9, and 13 which correspond to the desired number of Entry phase counter 26 next causes shift logic 29 to SHIFT decimal positions in entry register R1. Selected ones of the DOWN the contents of register R2, R3, and R4 by one re 75 stationary contacts on each of the decks are connected to a 3,634,666 9 source of negative potential according to a predetermined code while the rotary contact of each deck is connected to ground. Output leads b, d, f, and h are connected to the sta 10 gate 104 goes true, resetting DPSFF 105 and advancing decimal point counter 22 by one count. After DPSFF 105 is reset, the set output of DPSFF 105 ap tionary contacts E, F, G, and H. Using the signal convention plied to the input of gate 111 is false. Since CFSFF 108 is still that a positive or ground signal represents a one and a negative reset, and CFFF 106 is set, the CFSFF 108 set and CFFF 106 signal represents a zero, and considering the H deck to reset outputs applied to the input of gate 111 are also false. represent the least significant digit in a four-place binary code, EPCZ signal is likewise false. When HOME signal goes false at it can be seen that the output signals on leads b, d, f, and h the beginning of the data train, the output of gate 111 goes from the E, F, G, and H decks for the illustrated switch setting, true. This true output is inverted false by gate 153 producing a which specifies two decimal positions, are equal to 11 10, the O SHIFT LEFTR1 signal which is applied to various portions of binary representation of decimal 14. Similarly, setting the shift control logic 29 of FIG. 372. Whenever the SHIFT LEFT thumbwheel switch to the 5, 9, or 13 position results in the bi R1 signal is present, the digits in entry register R1 are shifted nary representation for decimal digit 11, 7, or 3, respectively. left one order position for each data pass through arithmetic The binary output of decimal position signal generator I thus 15 unit 30 of FIG. 372. represents the decimal 16’s complement of the desired At the conclusion of each data pass, HOME signal transi number of decimal positions specified by the thumbwheel tions true at the input of gate 111. The output of gate 111 ac switch. cordingly transitions false, inverted true by gate 153 and ap With reference to FIG. 373, as will now be evident when plied to the input of gate 140a. When this input to gate 140a DIV SET signal transitions true, decimal point counter 22 will 20 goes true, the output of this gate also transitions true and ad be set by the coded leads b, d, f, and h of decimal position vances decimal point counter 22 by one count. Thus, decimal signal generator I to the 16's complement of the desired point counter 22 is advanced by one count for each data pass number of decimal positions. This count controls alignment of which shifts left the digits in entry register R1. When HOME the data in entry register R1. signal again goes false at the beginning of the data train, gates The set outputs of flip-flops DPC1, 2, 4, and 8 comprise the 25 111 and 153 again produce a SHIFT LEFT R1 signal and the four inputs to inverting AND-gate 140 (FIG. 243). Since the digits in entry register R1 are again shifted left one order posi output of gate 140 will only be true if all the inputs are false tion, corresponding to a zero state of decimal point counter 22 This sequence of shift left entry register R1-advance this output is labeled DPCZ or decimal point counter zero. decimal point counter 22 continues until decimal point The output of gate 140 is applied to the input of gate 140a 30 counter 22 is advanced from a count of fifteen to zero. When (FIG. 243) along with the output of inverting OR-gate 153 DPCZ signal goes true, entry phase counter 26 is stepped off (FIG. 248) labeled SHIFT LEFTR1. The output of gate 140a zero by circuitry (not shown), gates 104 and 111 are disabled, is applied to the toggle input of DPC1 flip-flop along with the and decimal alignment of entry register R1 is complete. output of AND-gate 104 (FIG. 232). As will be apparent to The operation of the decimal point control system of FIG. those skilled in the art, a positive transition at the toggle input 35 373 proceeds in a different manner if the number entered has of DPC1 will advance decimal point counter 22 by one count. both whole number digits and decimal digits. The entry of The interconnections and functional relationships of the whole number digits proceeds as already described. When the remaining circuitry of the FIG. 373 system will become ap decimal point key is actuated by the operator, indicating that parent from the ensuing description. entry of whole number digits is complete, AC AND-gate 110 The operation of the decimal point control system of FIG. 2 40 (FIG. 232) is enabled by the concurrence of DPKD