Historical Document · 1971
US Patent 3,623,156: Calculator Employing Multiple Registers and Feedback Paths (T. E. Osborne, HP)
Osborne's calculator architecture patent behind the 9100: power gating, subroutine control and the integrated CRT pattern.
Historical Document · 1971
Osborne's calculator architecture patent behind the 9100: power gating, subroutine control and the integrated CRT pattern.
United States Patent (113,623,156 72 Inventor Thomas E. Osborne San Francisco, Calif. (21) Appl. No. 827,795 data between a keyboard input, a random access memory, and a plurality of flip-flop registers to perform arithmetic opera tions and transfers the results of these operations to a cathode 22 Filed May 26, 1969 45) Patented Nov. 23, 1971 73) Assignee Hewlett-Packard Company ray tube output display. The flip-flop registers include a pro gram register comprising a set of primary flip-flops for designating a subroutine to be performed and a set of seconda ry flip-flops for sequentially designating a group of one or Pako Ato, Calif. Original application June 23, 1966, Ser. No. 559,887, now Patent No. 3,566,160, dated Feb. 23, 1971. Divided and this application May 26, 1969, Ser. No. more instructions to be executed in each state of the designated subroutine. The primary and secondary flip-flops are controlled by multiple feedback paths. Power switching is employed in the internal control and subroutine logic so that the subroutines and instructions are supplied with power only when they are to be executed. The flip-flop registers also in clude a memory access register for receiving information read from and to be written into the random access memory. When a random access memory cycle is required, it is automatically interposed between the otherwise regularly recurring logic cy cles by the internal control and subroutine logic. Separate logic circuits are provided for enabling the state of the secon dary flip-flops to be directly transferred to the memory access register and vice versa so that encoded transfer vectors may be stored in the random access memory and subsequently 827,795 (54) CALCULATOR EMPLOYING MULTIPLE REGISTERS AND FEEDBACK PATHS FOR FLEXBLE SUBROUTINE CONTROL 29 Claims, 40Drawing Figs. 52 U.S. Cl........................................................ 340/1725 5 l l Int. Cl............... GO6f 9/16 50 Field of Search............................................ 340,172.5; 23.5/57 56 decoded by the internal control and subroutine logic to permit unrestricted subroutine returns. In the keyboard input two References Cited UNITED STATES PATENTS 3,094,610 6/1963 Humphrey, Jr. et al...... 340/172.5 X 3, 53,225 Of 1964 Merner et al.......... w power supply returns are employed to define one bit of the keyboard encoder. The random access memory is partitioned into one portion addressed by a single bit in an address register and into another, larger portion addressed by the remaining bits in the address register. Each flip-flop of the machine is a J K flip-flop provided with an adjustable threshold for noise im munity and with a high internal gain on the J-K inputs. In the cathode-ray tube output display, a recurring pattern generated by integration in only two directions is selectively blanked to display the results of the operations performed by the calcula tor. A tester may be connected to the machine for allowing all subroutines to be operated in a single step mode. The tester is provided with switches for initializing any internal state of the machine or stopping normal execution under any prescribed conditions and with apparatus for accessing the random ac 340,172.5 3,268,872 8/1966 Kimlinger. 340, 72.5 3,302,183 l (1967 Bennett et al.......... - - - - 340, 72.5 3,341,819 3,355,714 971967 Emerson...................... 1967 Culler............. 3401 172.5 340,172.5 3,366,929 fi968 Mullery et al................. Primary Examiner-Gareth D. Shaw Assistant Examiner-Sydney R. Chirlin Attorney-Roland. Griffin 340/172.5 ABSTRACT: Internal control and subroutine logic transfers cess memory. TESTER (E) waite MEMOey YLCY (3) YwTM (F) 5ENSE AMPLtfiegs. ON YSAN yPM G. READ MEMORY (2) LOC code CONTROL Q2) IK8 F, K24 UBOl 3:guTiNE LINES p SOOOO 5UBROUTINE SEQUENCING 5UBROUTINE DECODERS AND ( DWEs INSTRUCTION DRIVERS AWD FLIP(6) - Ftop J-K LINES ;gNE tit-1 Q (X) MEMORY LOGIC - Q) FLP-FOP outputs REGISTERS (E) () (NBT LINES REGISTERS agarf KEYs T ADDRESS LINES INHIBIT LINES GD TESTER PATENTED NOY 23 197 3, S23, 56 SEET O1 OF 31 FROM DISPLAY OPERAND NO KEY YES W0 (6) ES READ (WIA) I. E. SOM-o- 8FF WES <> O F16. 2 TO FIG. 3 NO us to CD-i <g> YES <> WO YES (Mi) a KBD (AN5) - Mi = OPERAND KEY MEM AUX, SIOR, is OPERAND EY 570 AUY. 510k. OOOOO-PTIA A.E. INITIALIZE MANTISSA DIGIT 0CATOR FEATURE FEATURE +0.000.00 YE5 (c 00000-a-TIA 1. E. WIALIZE (D) 00 -p KBD MANTISSA o DIGIT LOCATOR 2 -0.00. . . 00 s OO &S (e) --KBD & WE. CLEAR (R) SS h CLEAR YES 17t & s S A. Doyly 1NO G) OOOO -o- WA UPDATE SOM TO ENTER MANTISSA DIGITS (KE) - KE / KE5 UNCHANGED NO OPERAND -- KE YES (KE) +! -o- KE () (rIA) + --TIA UPDATE MANTISSA ENTRY POSITION O OPEAND -- KD t = 10 - (TIA) ENTER OPERAND INTO PROPER CHARACTER POSITION RETURN TO DISPLAY PROCESSING OF OPERANDS A/G-1 WWENTO THOMAS clone PATENTED NOY 23 197 3, 623, lb.6 SHEET O3 CF 31 M A 16.2 - - O ARTH 2. TCN o - FROM O15PLAY origin FIG | 7 (KBD) - WRK i.e. MULTIPLICAND OR QUOTIENT -- WRK 5 O --CPAO – MULTIPLY (5EE FIG 4) (KD) x (WD) -> WD O ------ (F) DIVIDE (SEE FIG 5 (WD)/(ko)-W0 (KBD) - TMP te. SAVE KBD (KBD) --TMP te. 6AVE KBD i. (WE)COMPUTE - (KE) --RAW WE i.e. WE le,(WE)-(KE) koil. -- ski PRODUCT QU07/ENT CHARACTERISTIC OF CHARACTERI577C OF NORMALIZE (SEE FIG.6) AROCESSING AR/THMETIC OPERATORS A/63 ... l. (3) ge. E570RE KBD (TMP) -- KED INVENTOR. THOMAS E. OSBOANE RETURN TO DISPLAY PATENTED NOY 23 1971 3, S23, 156 SHEET Ot. Of 31 o (2) (WRK) -o-TMP i.e. MULTIPLICAND-TMP (3) OOO ... O -- WRK i.e, INITIALIZE WRK GE) C) COMPARE SIGN5 TD5 KD5. PUT 51GN OF (TIA) - I --TIA PRODUCT W WDS EXIT TO 0. Fig. 2, 5TATE-D (TDO) -> TIA less s RS TMP III -o- TO9 (&) (WIA)+/ -- WIA LR5 WKK MULTIPL/CATION N.VENTOR F/G-4 THOMAS E. OSBONE PATENTEONOY 23 197 3, S23,56 SHEET OS OF 31 (8) ERROR - ATTEMPTED BY ZERO COMPARE KDS WD5. PUT 5IGN ERR OF QUOI. --TD5 (D) ( 12. Art 8) o FORM IOS COMPLE.M. OF YES Keypo LLS WRK KOO-9 YES (E) I(KD) + (WD) -- WD (H) (TD) - I - TD YES (G) (WIA) - -- WIA <> YES NO (K) YES (E) LLS TMP FORM 16 COMPLEMENT OF (TIA) AND EACH TO CHARACTER O (TIA) - WIA, (TD)-p-WD (M) for, t;gaunter D/VISIOW A/6.5 TO FIG. 3 5TATE (3) NVENTOR THOMAS E. OSBOANE PATENTED NOY 23 197 3, S23,56 SHEET OS OF 31 INVENTOR. M/06/24//24/7O/W AF/G-6 THOMAS E. 05BOAWE 3, S23, 156 PATENTED NOY 23 197 SHEET 07 OF 31 PATENTED NOY 23 1971 3, 623, 156 SEET O8 CF 31 93N/7 ~!@ 1/8 @ |© L3AMA1A@&Wow23w NO2 1907O 1 702) THOMAS E. OSBONE PATENTED NOY 23 197 3, S23, 156 SIEET 10 OF 31 - - - - - - - -- Sg KAAWAUGH MAP OF CHAAACTEA? ENCODING A/6 11 -4s evalue -- S4 KANAUGH MAP OF WOAD EMCOD/WG AIG 10 INVENTOR. THOMAS E. 05BOKNE PATENTED NOY 23 197 3, S23, l 56 SEET 11 Of 31 - YWTM, K42, K43 CONTROL LOGIC F/G, 12 INVENTOR. THOMAS E. OSBOAME PATENTEONOY 2397 3, 623, 156 SHEET 12 OF 31 ICAL, J00 J02, J24, KSJ50 SHIFT iŠd SHIFT KBD IRDR, IICF NVENTOR. SUBROUTINE ACCUMULATE 5 0000 A/G /3 THOMA5 E. O5AOWE PATENTED NOY 23 197 3, S23, l S6 SHEET 13 OF 31 (a ful ISTO (T), IC40 SUBROUTINE MULTIPLY SOOOf FIG 4 () 0010 I570 (Wil), J4), IDC F , I KBF ICAL, J50, IC40, J02 PFF000! R57T MP SFF 100/ 6) tool ICAI, J24, J51,PAFJ02(150 (0.01 LK5 WRK 5FF 1100 ISIO (WIA), J43, IIBF (J40 NVENTOR THOMAS E 05BOME - - - - - - - - - - -r (E) IOO ISTO (TDa), IC40, J4, IJBF PATENTED NOY 23 197 3, 623, 56 SHEET OF 31 SUBROUTINE SUM S OO/O A/6/5 TRANSFER KBD ) WRK J43, IC41 1. ify 3: 5 s: IKE s A.Y t W0 CARRY NVENTOR. THOMAS f. O5BOW f ITIME PATENTED NOY 23 197 3, 623, 56 SHEET 15 OF 31 IRDR (W), ITB5, C4I, J57, K57 EXIT: (f51) = 1 if CARRY INVENTOR SUBROUTINE 5 00116 FIG ADD THOMAS, E. 05AOKWE (5: Ef ECTO PATENTED NOY 23 197 3, S23,56 SHEET 16 OF 31 SUBROUTINE NORMALIZE S0100 A/G/7 ISIOWIA, J43, K24 0<3>Q2). DIVIDE '' ICALJ00, J50J51, K24 LRS WRK (k) 0000 2. 1/MPyoe Act 1510(814.4.18.4 ---------------------. -- () 1000 ISIOWE), K24, ICCF overflow ISTOIKE, ic4 py (e) 1100 Stoike), KBF, ICC, Jol, Koz QU07 IENT 7 O UNDERFLOW DIW OWERFLOW 4 MPY OR ACC PRODUCT O UNDERFlow MPY 6. " (SUM) UNDERFLOW - ACC JNVENTOR THOMAS E. O580&WE NO SIFTS RQD SHIFT5 RQp 10 SHIFTS RQ'D PRODUCT OR QUOTIENT 000 +00 PATENTED NOY 23 197 3, S23, 56 SHEET 17 OF 31 5ELECT Da SELECT REGISTER TO BE 5AIFTED K5 O L S. l-------------- () tool IRDA, IICF ISIO, IKBF, IICF NVENTOR THOMAS A. OSBOKME SUBAOUTINE 5H/FT 5O/Of A/G /3 3, S23, l S6 PATENTED NDY 23 197 SHEET 18 OF 31 FROM S II IO vy IRD, IC40, Ica, lic, ... . . . 1570, J24, K24 ICAL, K02,1640, K24 EXP 6UM SUBROUTINE EXPOWENT UPDATE 50/10 A/G 20 IO CALLING ROUTINE INVENTOR SUBROUTINE COMPLEMENT SO/10 F/G/9 THOMAS E. OSBOWE PATENTED NOY 23 197 3, S23, l S6 SHEET 2 O OF 31 RDe WIA- IRDR (Mi), J42, 1DCF, K41, (ISTO) (CAF) = D9 - 1 (6) ISIO (Ku), IDCF, K4. K40 -- - - - G- -1000 -- - - - --- ESTABLISH PKE IRD (KE), IDCF, IESF (ISIO) t | M. WNTOR SUBROUTINE ENTER DIGIT 5/OOl A/G 22 THOMA5 E. O5BoeNE PATENTED NOY 23 197 3, 623, 56 SHEET 21 OF 31 TRACE AWS KEY/NG DELAY ROUTINE DECODE17 LEFT HALF AOLD DOWN HOLD LEFT SUBROl/7/WE D15PLAY 6 10/1 A/G-23 NVENTOR THOMAS E. OSBOAME PATENTED NOY 23 197 3, 623, 156 SHEET 2. Of 31 Z IROK, IDGF ol. ISIOT, IG40, (4) f4 m - y ( KDR, I DCF Yi ZK) o Ooooo. ISIOW, IC40, IC41 KO3 <& - a----- (J) HII IICF, K41, J40, K32 IRDIA, IICF to <& 9 — ----71 (c) 0100 500 2 IRDR KD), IC40 (E) 0140 god (E) oil IRDR (WEI, IIRA, J32, K50 I570 (K), (40, ICA ! ---- TO TO soo 5gog - IRDe TIICF f ()00 J00, KOl SUBROUTIME MBB S//10 FIG - 26 INVENTOR THOMAS E. OSBONE PATENTED NOY 23 197 3, S23, 56 SHEET 25 CF 31 (CFF) = 10|| (O) Oil IRDR (KE), 1570, (E) OIO! I570 (Kéo), IIBF (CFF) - E - ?oil (f) 001) IKDR (IA), IC40 IC41, J43, J32 (CAF) = 17 (6) 0001 I570 (TIA), J43, IIBF (CFF) = 17 IIBF, IICF SUBROUTINE DIGIT ENTRY P05/TION A/G 27 INVENTOR THOMAS E. O5 BOCNE PATENTED NOY 23 197 3, S23, l 56 SHEET 26 OF 31 5UBAOUTINE EXPOWENT UPDATE DIWIDE INITIAL/ZATION 5 III F/628 IRDR (KD), IC40, IC47, ICCF, CIESF IRDR (WD5), IC41, IESF, IJBF I570 (TD), IC40, K03, I J50) NVENTOR SOI THOMAS E. OSBOAAVE PATENTED NOY 23 197 3, 623, 156 SHEET 27 OF 31 (). WCC UOR "S" INPUT (8) ---. (D V7 (2) YOCA A/ACA ----(S) E"OR "O" CLOCK NPV7 (U) OUTPUT FL/P FLOP Flg. 29 J INPUT (CURRENT) K INPUT (CURRENT) --- : to , t , t , t , t , l l h es - s |-e- E" TRACE NUMERICS GENERATED WITH CASCADED "E" TRACE5 A/63/ INVENTOR. THOMAS E. O5608WE PATENTEONDY 23 197 3, 623, 156 SHEET 28 OF 31 +2.2 W LEFT DEFECTION CIRCU/7 F/G32 G) +2.2 W DOWN DEFLECTION CIRCUIT A/G 33 + 1200 W (E)- RIGHT IDRR (E)/ O) 2.2 W e64T officrow cleur A/G 34 INVENTOR THOMAS 6. 0580KNE PATENTED NOY 23 197 3, 623, 56 SHEET 29 CF 31 LEFI (IGHT 00WN | | | + 200 W - 15 WOLT5 G-(2) Gl - 20-4) 63 24 y H. H B/A5ING CIRCUITS - 3API A/G 35 EP VCC- - - - - -12-4-------------------- Vea. -O ILX toN-- He- t OFF-- IcQ2 (0UE GOLM org/N/N/ >THOMA5 E.?NVENTOR 05BORNE A/G 37 3, 623, l SS PATENTED NOY 23 1971 SHEET ÖN 22 o ( 30 OF 31 #72cC)N N0XNc 00/($) INVENTOR THOMAS E. O5AOAME PATENTED NOY 23 197 3, S23, 156 SHEET 31 OF 31 79J3/I10NI3H7/2ç*O NVENTOR. THOMAS f. O5BOWE 3,623,156 CALCULATOR EMPLOYNG MULTIPLE REGISTERS AND FEEDBACKPATHIS FOR FLEXBLESUBROUTINE CONTROL 2 FIG. 20 is a detailed flow chart of the exponent update subroutine; F.G. 21 is a detailed flow chart of the divide subroutine; This is a divisional application of U.S. Pat. Application Ser. No. 559.887 filed on June 23, 1966, by Thomas E. Osborne FIG.22 is a detailed flow chart of the enter digit subroutine; FIG. 23 is a detailed flow chart of the display subroutine; FG. 24 is a detailed flow chart of the subroutine used for determining arithmetic operators; This invention relates to an electronic desk top calculator for miscellaneous matters; CROSS-REFERENCE TO RELATED APPLICATION and issued on Feb. 23, 1971, as U.S. Pat. No. 3,566,160 enti FG. 2S is a detailed flow chart of the subroutine used for tled SIMPLIFED RACE-PREVENTING F P-FLOP HAW determining the state of the machine; O ING ASELECTABLE NOSE IMMUNTY THRESHOLD. FIG. 26 is a detailed flow chart of the MBB subroutine used and to certain subcombinations therein which are useful in F.G. 27 is a detailed flow chart of the subroutine used for electronic top desk calculators and larger calculators of the determining the position of entered digits; data processing computer type. FIG. 28 is a detailed flow chart of the subroutine used for One form of electronic desktop calculator is illustrated and 5 updating exponents and initiating the first portion of the divi described in detail herein. This calculator is provided with sion process; subroutines for performing the standard arithmetic operations FIG. 29 is a schematic diagram of one of the flip-flop cir of addition, subtraction, multiplication, division, exponential cuits in the calculator; functions, and cumulative operations involving these specific 20 FIG.used 29' operations and is readily adapted for performing additional cuit of FIG.is29;a waveform diagram illustrating the flip-flop cir operations. The calculator includes a keyboard for entering FIG. 30 is a diagram of the trace pattern on the output data, a random access memory for storing data, an output dis cathode-ray tube of the calculator; play for indicating the results of calculations performed by the FIG. 31 is a diagram illustrating how decimal numbers are calculator, apparatus including a plurality of flip-flops for con 25 displayed from the trace pattern of FIG. 30; trolling the operation of the calculator, and a multiterminal FIG. 32 is a schematic diagram of the left deflection circuit connector including a plurality of electrical conductors elec for the cathode-ray tube; trically connected to the outputs of a majority of these flip FIG. 33 is a schematic diagram of the down deflection cir flops. A tester for use with this calculator is also illustrated and for the cathode ray tube; described in detail herein. As will be apparent hereafter, the 30 cuitFIG. 34 is a schematic diagram of the right deflection circuit principles of the invention may be employed in calculators for the cathode-ray tube; other than the specific electronic desk top calculator illus trated herein. FIG. 35 is a schematic diagram of the biasing circuits for the cathode-ray tube; The objects and advantages of the invention will be ap 36 is a schematic diagram of the clock source used in parent from the following description of an electronic top 35 theFIG. calculator; desk calculator and a tester for use therewith read in conjunc FIG. 37 is a waveform diagram illustrating the operation of tion with the attached drawings in which: the clock source of FIG. 36; FIG. 1 is a diagram illustrating the manner in which the cal FIG. 38 is a diagram of the keyboard encoder employed in culator operates in response to operand (digit entry) keys; FIG. 2 is a diagram illustrating the manner in which the cal 40 the calculator, and, FIG. 39 is a schematic diagram of a removable tester used to culator operates in response to control operator keys, test and service the calculator. FIG. 3 is a diagram illustrating the manner in which the cal culator operates in response to arithmetic operator keys; GENERAL OPERATION FIG. 4 is a diagram illustrating the manner in which the cal 45 The machine illustrated in the attached drawings can be di culator operates in response to the multiplication key; FIG. 5 is a diagram illustrating the manner in which the cal vided into three logical sections - an input section, an output culator operates in response to the divide key; section, and a processor. FIG. 6 is a diagram illustrating the manner in which the cal The input section consists of a manually operated keyboard culator normalizes numbers; containing 23 data keys and a diode encoding matrix to 50 FIG. 7 is a diagram illustrating the manner in which the cal generate a unique five-bit code when each key is operated. culator operates in the response to the accumulate keys; The output section consists of a cathode-ray tube (CRT) FIG. 8 is a block diagram of the electronic circuits em and the associated circuitry necessary to display the contents ployed in the calculator; of two registers contained within the processor. The contents FIG. 9 is a schematic diagram of typical circuits employed 55 of the two registers are displayed as two lines of decimal nu in the calculator to execute logic functions by power merals with the two lines arranged in upper and lower posi switching; tions. The register occupying the lower position on the CRT is FIG. 10 is a Karnaugh map illustrating the memory ad the keyboard, or KBD, register. It displays the current numer dressing arrangement employed for addressing each word in ic input data. The contents of KBD are not altered, except for the core memory of the calculator; a sign change under circumstances to be described later, when FIG. l l is a Karnaugh map illustrating the memory ad 60 arithmetic operations are executed. The upper position of the dressing arrangement employed for addressing individual CRT display contains the contents of the answer, or ANS, re characters within each word in the core memory of the calcu gister. ANS always contains the answer to the last arithmetic lator, term processed. Each of the ANS and KBD registers is stored FIG. 12 is a detailed flow chart of the control logic of the 65 in memory and displayed on the CRT as a 10-decimal digit calculator; number (hereafter called the mantissa) having a decimal point FIG. 3 is a detailed flow chart of the accumulate subrou located between the most significant and second most signifi tune; cant digits. The mantissa is followed by two decimal digits, FIG. 14 is a detailed flow chart of the multiply subroutine; called the characteristic, which locate the true decimal point FIG. 15 is a detailed flow chart of the sum subroutine; 70 of the number relative to the normalized position it occupies FIG. 16 is a detailed flow chart of the add subroutine; in the mantissa. For example, the number 0.0125 is displayed FIG. 17 is a detailed flow chart of the normalize subroutine; as 1.250000000 -02. Thus, the smallest positive number FIG. 18 is a detailed flow chart of the shift subroutine; which can be displayed is .000000000X 10. The largest FIG. 19 is a detailed flow chart of the complement subrou tine; 75 positive and negative numbers which can be displayed are --9.999999999.10. 3,623, 156 3 2 6.02.0000000 02 The processor contains logical elements common to digital 3 20000 to 23 computers, i.e., flip-flops, gates, etc., a random access core memory, and means for receiving information from the input section and sending signals to the output display section. With this general background, the operating characteristics, 5 The CHS control operator changes the mantissa sign unless the preceding control operator was an EXP in which case the i.e., response to input data, can be described. Input data is characteristic sign is changed. Additional CHS control opera grouped into two distinct categories, namely operands and tors cause repeated sign changes. When the CHS control operators. The operands consist of the decimal digit entries zero through nine. The operators are divided into two sub operator follows an arithmetic operator or an ERR, ANS, or groups, namely control operators and arithmetic operators. O KBD control operator, the sign of the KBD register is changed as stated above. However, if an operand digit entry or a The control operators are defined as ERR (error), EXP (ex ponent), ANS (answer), CHS (change sign), MEM (memo decimal point follows the CHS control operator, the processor recognizes the CHS control operator as a signal implying that ry), STO (store), KBD (keyboard) and DEC (decimal point). The arithmetic operators are ACC 0(accumulate 0), ACC 15 a new negative mantissa is going to be entered into the KBD register. The processor responds by affixing a negative sign to +(accumulate +), ACC-accumulate -), X(multiply), and the mantissa when the decimal point control operator or the -- (divide). first operand digit is received. In other words, the negative The ERR control operator clears the keyboard to normal sign may be affixed to the mantissa of KBD entry prior to en zero, e.g., a zero mantissa with a zero characteristic. tering the first digit of the mantissa, or at any time following When an operand digit entry follows an arithmetic operator or an ERR, ANS, cr KBD control operator, the processor 20 the entry of the first digit of the mantissa. An operand entry is also used to define auxiliary storage re recognizes the operand as the most significant digit of a new gisters within the processor. When an operand entry follows a data entry, clears the mantissa and characteristic of KBD to zero, and enters the operand into the KBD register as the most STO control operator, the contents of the ANS register are significant digit of the mantissa. The processor will not enter a 25 sent to the auxiliary storage register defined by the operand, digit into the second most significant position of the mantissa e.g., STO followed by 4 results in the contents of AND being until a nonzero digit operand entry is placed in the most sig sent to auxiliary storage register number 4. When a MEM con trol operator is followed by an operand entry, the contents of nificant position of the mantissa. The DEC (decimal point) control operator provides suffi the auxiliary storage register defined by the operand digit are cient information to the processor to determine the proper 30 transferred into the KBD register. The contents of the source digits and sign of the characteristic. Thus, each digit entry register remain unaltered in either process. operator after the first not only enters the digit in the KBD The ANS control operator transfers the contents of the mantissa, but also increments the KBD characteristic until the ANS register into the KBD register. The contents of the ANS decimal point control operator is operated. For instance, the register remain unaltered by this process. This allows answers number 632. 14 is entered in KBD by six key operations as fol 35 of previous arithmetic terms to be used as factors of new lows: terms. The KBD control operator provides a new user with con tinuity in performing arithmetic operations. It is used to simu KEY OPERATIONS CR SPLAY OF KBd late a transfer of the contents of the KBD register into the 40 KBD register. The usefulness of this operator is discussed later -O.000000000 00 in the detailed description of FIG. 2. 6 6.000000000 00 When the arithmetic operator preceding an ACC 0 3 6.30000000 () 2 6.3200.00000 O2 arithmetic operator was an ACC 0, ACC +, or ACC -, the decimal point 6.320000000 02 contents of the ANS register are set to normal zero, and the 6,32000000 02 45 contents of the KBD register are algebraically added to the 4 6,32400000 02 contents of the ANS register. In effect, the contents of the KBD register are transferred into the ANS register. When a decimal point entry follows an arithmetic operator, or When the arithmetic operator preceding an ACC + an ERR, ANS, or KBD control operator, the processor recog nizes the decimal point as the first entry of a forthcoming 50 arithmetic operator was an ACC 0, ACC +, or ACC -, the contents of the KBD register are algebraically added to the operand and clears the KBD register to zero. A decimal point contents of the ANS register. The sum appears in the ANS re control operator is not required when entering integers. When gister and the contents of the KBD register are unchanged. the initial key of an operand is the decimal point, successive When the arithmetic operator preceding an ACC operand keys decrement the characteristic of KBD until a arithmetic operator was an ACC 0, ACC -, or ACC +, the nonzero number has been entered in the most significant posi 55 sign of the KBD register is changed and the new contents of tion of the KBD mantissa. the KBD register are algebraically added to the contents of the The EXP control operator informs the processor that the ANS register. The sign of the KBD register is changed by the characteristic of the KBD register is to be changed. The processor responds by clearing the characteristic of the KBD process. Note that if a second ACC - arithmetic operator is register to zero. When operand digit entries follow the EXP 60 executed, the original contents of ANS and KBD will be reestablished. Thus, it is possible to restore the contents of the control operator, they enter (modulo 100) into the charac ANS register by executing two consecutive ACC - arithmetic teristic of the KBD register. The EXP feature allows the operators. characteristic of an operand to be altered without changing When the arithmetic operator preceding a X arithmetic the mantissa. It also allows the user to enter operands with large negative or positive exponents without inserting leading 65 operator is an ACC 0, ACC -, or ACC +, the processor defines the contents of the KBD register as the multiplicand of or trailing zeros. For example, Avogadro's number (6.02X10 a forthcoming product. As explained below, the contents of ') can be entered into the KBD register by six key operations KBD are defined as the multiplicand by transferring the con as follows: tents of KBD to a third register called the working register 70 (WRK) without changing the contents of KBD. KEY OPERATIONS CR DISPLAY OF KBd When the arithmetic operator preceding a X arithmetic operator is a X, the processor algebraically multiplies the 6.0000000 00 previously defined multiplicand times the contents of the KBD 6,000000000 0 register and identifies the product as the multiplicand of the 6.020000000 02 75 forthcoming product. 6,020000000 00 : 5 3,623,156 When the arithmetic operator preceding a arithmetic operator is an ACC 0, ACC -, or ACC +, the processor defines the contents of the KBD register as a dividend of a forthcoming division. When the arithmetic operator preceding a arithmetic operator is a X, the processor algebraically multiplies the con tents of the KBD register times the previously defined mul tiplicand and defines the product as the dividend of the forthcoming division. When the arithmetic operator preceding a arithmetic operator is a , the processor algebraically divides the previ ously defined dividend by the contents of the KBD register and identifies the quotient as the dividend in the forthcoming 6 The arithmetic notation also differs from the parenthesized notation commonly used in digital computer compilers such as FORTRAN and the electronic calculating machines marketed by Mathetronics, Inc., in that none of its arithmetic operators can be shown to be uniquely equivalent to the open or closed parenthesis, GENERAL SYSTEM The calculator contains a memory consisting of four work ing registers and 10 or less auxiliary storage registers with each register consisting of 13 characters of five bits each. The working registers are defined as WRK (working register), TMP (temporary register), KBD (keyboard register) and ANS division. (answer register). The auxiliary registers are defined as MEM s When the arithmetic operator preceding a X arithmetic 0, MEM1,...MEM 9. Ten of the 3 characters in each register operator is a , the processor algebraically divides the previ are used to store the mantissa. These mantissa characters are ously defined dividend by the contents of the KBD register defined as D, D, D, ...Do with D, being the most significant and identifies the quotient as the multiplicand of the digit (MSD) and Do the least significant digit (LSD). Two of forthcoming product. the remaining three characters, E, and E are used to store 20 When the arithmetic operator preceding an ACC 0 the most significant and least significant digits of the charac arithmetic operator is a X, the processor changes the ANS re teristic. The remaining character, defined as IA, is used for gister to normal zero, then algebraically multiplies the con storing intermediate results of computations and control infor tents of the previously defined multiplicand times the contents mation. of the KBD register and their product is algebraically added to Each character consists of five bits, B, B, B, and B, and the contents of the ANS register. In effect, the product is B. These characters are stored in standard 8-4-2-1-BCD placed in the answer register. code with B and B being the most significant bit (MSB) and When the arithmetic operator preceding an ACC + least significant bit (LSB) respectively. B of D, and E hold arithmetic operator is a X, the contents of the KBD register signs of the mantissa and characteristic respectively. and the previously defined multiplicand are algebraically mul 30 theThe core memory uses the word access storage system tiplied and their product is algebraically added to the contents described by FIGS. 4.1, 4.3, 8.2e, and 8.15a of the book of the ANS register. Square Loop Ferrite Circuitry by C. J. Quartly (Iliffe Books, When the arithmetic operator preceding an ACC Ltd., London). A memory cycle, similar to that in an IBM 704 arithmetic operator is a X, the processor first changes the sign digital computer, is used; thus, reading out of memory of the KBD register, then forms the algebraic product of the becomes a nondestructive process while writing into memory previously defined multiplicand and the contents of the KBD 35 is a destructive process. register, and algebraically adds their product to the contents Five flip-flops (the bit flip-flops or BFF) are used to hold of the ANS register. both the character read out of memory and the one to be writ When the arithmetic operator preceding an ACC 0 ten into memory. The bit flip-flops are also connected to logi arithmetic operator is a , the processor changes the ANS to 40 cal circuitry allowing them to be incremented or decre normal zero and then algebraically divides the previously mented. Incrementing occurs in the four LSB (Ba, B, B, B) defined dividend by the contents of the KBD register and their only and is cyclic 0 through 9 in 8-4-2-1 BCD code. When O quotient is algebraically added to the ANS register. In effect, the contents of BFF are incremented from 9 decimal ( 001 bi the quotient is placed in the ANS register. nary or 11 octal) to 0 decimal, a signal is given to set a carry When the arithmetic operator preceding an ACC + 45 flip-flop to a "l" condition. Decrementing the BFF results in arithmetic operator is, the processor algebraically divides the the four LSB being reduced by one count in straight binary previously defined dividend by the contents of the KBD re fashion. Decrementing zero causes l l l l binary (17 octal) to gister and algebraically adds the quotient to the contents of appear in the four LSB of the BFF. the ANS register. Any character in memory can be selected by inserting its When the arithmetic operator preceding an ACC - SO address into flip-flops used to identify one of the 13 character arithmetic operator is , the processor first changes the sign of locations and any one of the 14 registers. (Quartly, IBID.) the KBD register, then forms the algebraic quotient of the previously defined dividend and the contents of the KBD re To facilitate the detailed system description, the following gister and algebraically adds the quotient to the contents of conventions are used; the ANS register. 55 1. Individual characters in memory are referred to by prefix This mode of operation allows the user of the calculating ing the character identifier with the first letter of a working re machine to form of the answer to any arithmetic expression gister or an M for the "auxiliary storage register. For exam made of terms containing factors of the form (NXNX...XN ple, KDAE and WIA refer to the MSD of the KBD mantis fDxDX...XD,) by following each term with either ACC - or sa, and LSD of the ANS characteristic, and the A character of ACC + depending upon whether the algebraic sign of that 60 WRK respectively. term is negative or positive respectively. Moreover, each mul 2. The sign of the mantissa and characteristic are identified tiplier is preceded by a X arithmetic operator and each divisor by suffixing the D or E identifiers by the letter S. Thus, the is preceded by a arithmetic operator. Those and only those KBD mantissa sign becomes KDS (which is contained in K D, arithmetic operators required to uniquely define the problem B) and the ANS characteristic sign becomes AES (which is are used. This differs from other calculating systems which 65 contained in A. E. B.). require intermediate transfers or extra arithmetic operators to 3. The entire mantissa or characteristic is referred to by accomplish the same type of problem. prefixing the letter D or E, respectively, with the ap It is also important to notice that the arithmetic notation dif propriate register identifier. For example, the mantissa of fers from the Lukasiewicz (Polish) notation, often called 'ANS becomes AD and the characteristic of TMP becomes TE. Parenthesis free' notation, in that the X arithmetic operator O precedes the multiplier instead of follows it, Similarly the 4. When parentheses enclose a register identifier, they sym arithmetic operator precedes the divisor instead of following bolically imply "the contents of." This notation is used to it. This feature assists the user because the X and arithmetic differentiate between the address of a memory area and operators precede the multiplier and divisor respectively when the information stored in the address. For example, the 75 written in standard arithmetic form, symbol (KD) means the contents of the KBD mantissa, 7 3,623,156 8 5. The arrow, -, replaces the words "go into." SOM-01-. This encoding informs the processor that the Some rudementary operations may be described with this STO key has preceded the operand entry. The operand key symbolic language and will help explain the detailed system depressed defines the address of an auxiliary storage register. operation. As a result, (ANS) - M. where i is the operand key actuated. Suppose the contents of KD are to be incremented by one s Note: on any interregister transfers, only the characteristic count. The logical operations would be to set the address flip and mantissa along with their signs are transferred. The IA characters do not transfer. flops to KD, execute a read cycle, increment the BFF, and ex ecute a store cycle. These operations are symbolically stated SOM=l 1-. This encoding informs the processor that the as (KD) --1 - KD, which reads "the contents of the address MEM key has preceded the operand key. The operand key O KD, plus one, go into KD." Similarly, if the contents of WE defines the address of an auxiliary storage location. As a are to be transferred to TE, the apparatus includes control result, (M)- KBD. sequencing to select the address of WE, execute a read cycle, SOM =-01 1-. This encoding directs the processor to put select the address of TE, and execute a write cycle. This is (KE) - KE and to enter the operand into KE. written symbolically as (WE) - TE which reads "the con SOM-01-0. This encoding informs the processor that the s tents of the address WEgo into TE." position of the decimal point has not been fixed. All of the detailed logical characteristics of the calculating SOM-01-1. This encoding informs the processor that the machine will be described by using symbolic language, similar position of the decimal point is fixed. to the preceding sample expressions. Proper time sequencing SOM-010-. This encoding directs the processor to enter of the logical operations is given by placing the symbolic ex the operand into the proper KBD mantissa character location. pressions in flow charts (IBM Form A22-6503-2, pp. 31, 33). The address of the proper location is stored in TIA and is up The flow chart is a particularly convenient means for describ dated each time a new operand is entered. ing the system logic for two reasons: (1) translating informa The flow chart covering the proper response to operand tion from a flow chart into logical design set-reset equations is keys is shown in FIG. i. Throughout various FIGS. in the flow a process well-known to logical designers, and (2) the logical charts, certain states are referred to by letter references in the equations and/or circuit diagrams are voluminous, making it FIGS. In this description, the letter references are prefaced by difficult to understand the system operation without the aid of the number of the FIG. in which the reference appears. In the flow charts. state 1A, the SOM is obtained from WIA. If the SOM is a PKE By using the random access capabilities of the memory or NKE, signifying a new mantissa entry, zero is stored into system, the contents of ANS and KBD are displayed on a 0 TIA, states 1B and 1C, thereby initializing so that the operand cathode-ray tube employing deflection circuitry and logic will be stored in KD as directed in L. After initializing TIA, described below. The resultant two line display has the con the KBD register is cleared to positive zero, 1D, if PKE or to tents of ANS displayed above the contents of KBD. From left negative zero, E, if NKE. to right, the characters displayed are mantissa sign, D, Following the PKE or NKE zeroing, the SOM is updated to decimal point, D, D, D, D, D, D, D, D, Do, blank, 35 00100 if the operand key actuated was not a zero, 1G. The characteristic sign, E, and E. Positive signs are implied by no SOM is left at PKE or NKE if the operand key was a zero key. sign at all, while negative signs are displayed in their conven The logic directing control to 1H determines that the tional form. The characteristic locates the decimal point rela characteristic should be incremented by one count. This logic tive to its displayed position. As an example, the number -ll 2 allows the processor to assign the proper exponent to integers is displayed as -1.120000000 02. The number zero is dis 40 and decimal fractions. played by having all characters set to zero. Signs of the charac The operand is stored into the proper mantissa character by teristic or mantissa can be either positive or negative when dis the logic provided in 1 K and 1L. playing zero. The SOM directs the processor to enter the operand into All information enters the processor via 23 manually the KBD characteristic in states M and N. operated keys. Logically, these keys are organized into three When the SOM directs control to 1 P or 10, the auxiliary groups: (i) operands -0, 1,2,3,4,5,6,7,8, and 9; (2) control storage features are put into effect. State R sets the SOM to operators-ERR, EXP, ANS, DEC, CHS, MEM, STO, and PKE. KBD: and (3) arithmetic operations -X, , ACC 0, ACC -, ACC +. Each of the keys is encoded into a unique five-bit PROCESSING CONTROL OPERATORS code by a diode encoding matrix. SO The MSB, B, of the encoded signal differentiates between FIG. 2 shows the processor response to control operator operators and operands. The four LSB of each operand code keys. Each of the eight unique control operator codes directs encode the operands in straight 8-4-2-1 BCD code. control to one of the eight entrances shown. An information line enters the processor from the keyboard in state 2A, (ANS)- KBD. This allows the answer of a indicating that a key is down. This signal commands the 55 previous term to be used as a factor in a new term. State 2B machine to exit from the display routine and to