Historical Document · 1971
US Patent 3,566,160: Simplified Race-Preventing Flip-Flop (T. E. Osborne, HP)
The J-K flip-flop with selectable noise immunity used throughout the HP 9100.
Historical Document · 1971
The J-K flip-flop with selectable noise immunity used throughout the HP 9100.
United States Patent (11) 3,566,160 72 Inventor Thomas E. Osborne San Francisco, Calif, (21) Appi. No. 559,887 22 Filed June 23, 1966 45) Patented Feb. 23, 1971 73) Assignee Hewlett-Packard Company 3,045,128 7/1962 Skerritt........................ 3,046,413 7/1962 Clapper..... 3,100,848 8/1963 Skerritt........................ Primary Examiner-Stanley D. Miller, Jr. Attorney-Roland I. Griffin 307/292 307/292 3071292 Palo Alto, Calif. 54 SIMPLIFEDRACE-PREVENTING FILIP-FLOP HAVING ASELECTABLE NOSE IMMUNITY THRESHOL) 16 Claims, 39 Drawing Figs. (52) U.S.C........................................................ 307/291, 3071289,3071292,328/196, 328/206 51) Int. Cli........................................................ H03k 3/12 50 Field of Search............................................ 3071291, 292, 289; 328/196, 197,206 56) References Cited UNITED STATES PATENTS 3,102,208 8/1963 Reach, Jr...................... 3,294,980 12/1966 Whittle......................... 3,334,249 8/1967 White........................... 3,351,778 11/1967 Seelbach et al............... 307/292X 328/196X 307/292X 3071291 3,369,130 2/1968 Stern............................ 307/291 ABSTRACT: First and second transistors are arranged as a flip-flop in which the base of each transistor is connected by a separate resistor to the collector of the other transistor, the collector of each transistor is connected by a separate resistor to a source of supply voltage, and the emitter of each transistor is connected to a source of reference voltage. A first input drive circuit is connected to the base of the first transistor. This input drive circuit includes a capacitor, and a resistor serially connected between the base of the first transistor and the source of supply voltage. It also includes an input transistor having its collector connected by the capaci tor to the base of the first transistor, its base connected by a diode to the collector of the first transistor, and its emitter connected to a source of adjustable voltage having a value in termediate to the values of the supply and reference voltages. A second input drive circuit of the same type as the first is similarly connected to the base of the second transistor. See FIGS. 29 and 29' and under the heading FLIP-FLOPDRIVER AND GATING. Such flip-flops are employed in the internal control and subroutine logic of a calculator. "E"Ok "O" "F" De "1" OUTPUT OUTPUT FLIP FLOP PATENTED FEB 23197 3,566, 16 O SHEET O1 OF 31 FROM DISPLAY OPERAND NO KEY? YES N0 TO FI6. 2 TO FIG. 3 Egy 1/E5 (2) READ (WIA) I. E. SOM-s- BFF YES <> CONT&OL OPEKATIO NO O (P) (Mi) -- KBD (Q) (AN5) - Mil 00000-PTIA I.E. INITIALIZE MANTISSA 00000-a-TIA LE. INITIALIZE - OPERAND KEY i = OPERAND KEY DIGIT LOCAT0K "DIGIT L0CATOK MEM AUX, SIOK. 570 AUX. 5IOK. FEATURE MANTIS5A Q 2 (E) FEATURE +0.000.00 +00 Q& -p KBD S. diEik (R) N CLEAR YES 00000 -o- WIA r SS S. V.) 5ET SOM 70 "PKE" SR 15 K. ZEKO" 5 boy NO G) OOlOO -- WIA UPDATE 5OM TO ENTER MANTISSA DIGITS (KEo) - KE! KE5 UNCHANGED NO IMPLIES <> o/EE OPERAND - KE (KEo) +l -- KE (TIA) + I-PTIA UPDATE MANTISSA ENTRY POSITION O OPERAND -> KDi i = 10 - (TIA) ENTER OPERAND INTO PROPER CHARACTER POSITION RETURN TO DISPLAY PROCESSING OF OPEKANDS A/G-1 INVENTOK THOMAS E. O5BOKWE BY 2%-1 2-4 PATENTED FEB23 (97. 3,566,160 SHEET O3 OF 31 ARTHREric TI A/6. 2.-- 0 CE FROM D15PLAY 2-oright FIG. I. 2 (KBD) -- WRK i.e. MULTIPLICAND OR 0U07 IENT -- WRK / (E) 7 (E) MULTIPLY (SEE is 4) DIVIDE (SEE FIG.5 (WE), (KE) - RAW WE AS36 CHARACTERISTIC OF (KD) x (WD) -- WD te. COMPUTE CHARACTERISTIC OF PRODUCT (KBD) - TMP i.e. SAVE KBD QUOTIENT ACCUMULATE (SEE FIG 7) (WD)+(KD) -> WD NORMALIZE (5EE FIG 6 PROCESSING AR/THMETIC OPERATOK5 (R) A/63 (WKK) -- AN5 (5) (TMP)- KBD i.e. RE5TORE KBD (D MA0 -- WIA RETURN TO DISPLAY INVENTOR. THOMAS E. OSBOKWE BY 2% 4-2 - 12-4 ATTOKNEWS PATENTED FEB 231971 3,566, l8O SHEET O' OF 31 (4) (WRK) -> TMP i.e. MULTIPLICAND--TMP (8) 000... O -- WRK i.e, INITIALIZE WRK COMPARE SIGN5 TD5 & KD5. PUT 516N OF PRODUCT IN WD6 EXIT T2.-- FIG. 2, 5TATE (C) MULTIPL/CAT/OW F/G-4 INVENTOR. THOMA5 E. 05BOKNE BY 12-4-2-/- 12 A77OAMEYs 3,566, 160 PATENTED FEB 231971 SHEET OS OF 31 O --TD -9 III --TD O -> TIA (8) ERROR - ATTEMPTED i: BY ZERO COMPARE KDS & WD5. PUT 5IGN OF QUOI. --TD5 ERR keybowN)YES 7 TO 5TATE (8) FIG. 2 Q) LLS WRK FOKM 106 COMPLEM. OF KDO-9 YE5 (E) |(KD)I lovo-wo CARRY YES ? (G) (WIA) -1 - WIA ES <> YES (E) LL5 TMP NO GK) FORM 16 COMPLEMENT 0F (TIA) AND EACH TD CHARACTER O (TIA) -- WIA, (TD)->WD (V) FORM THE 106 COMPLEMENT A/p/29/2// A/6.5 5TATE (6) 2. 2-4-2- - 12.2 A77 OCME V6 PATENTED FEB2397 3,566, l8O SHEET OS OF 31 O EN TER (4) --OO -o- KE NO <> YES IS (WIA)=0000 YE5 N0 6 (WIA)-0000 p 7 NO (C) -- Of -- KE (D) LRS, WKK - 5 NP {(WD5-0000). YES 7 (E) (KE) + (WE) (E) 5E7 KDS 70 "MINU5 -- WE 5 YES NO 7 O) (E) (6) (KE) + 1 - KEo -- EXIT INVENTOR. AVOAA14A/2277/62/V Af/G. 6 THOMAS E. 05BOAWE "7%-4--- 122 PATENTED FEB23 97 3,566, 18O SHEET O7 OF 31 ATTOKNE Y6 PATENTENFEB2397 3,566, l8O SHEET O9 OF 31 (@) /3/W/)02879 INVENTOR. THOMAS E. 05BOA W PATENTED FEB 23197 3,566, 160 SHEET 10 OF 31 1N tas as us IAS IAS IA5 IA5 IAS IA5 IA5 IAS IA5 IAS IA6 Sal- Sal KAANAUGH MAP OF CHARACTER ENCODING A/G // Sal KAKNAUGH MAP OF WORD ENCODING F/G /O INVENTOR THOMA5 E. 05BOKNE BY 12-4-2-12-4 ATIOAAVE Y6 PATENTED FEB23 (97. 3.566.160 SHEET 11 OF 31 YWTM, K42, K43 CONTROL LOGIC F/G, 12 INVENTOR. THOMAS E. O5BOAC/WE BY 7%. /-/2-e PATENTED FEB2397 3,566,160 SHEET 12 OF 31 FNVENTOR. SUBROUTINE ACCUMULATE 6 OOOO A/6/3 BY THOMAS E. O5AOA/VE 3-2- - 12-4 2-4-2 PATENTED FEB 23197 3,566, l8O SHEET 13 OF 31 SUBROUTINE MULTIPLY SOOOl FIG 14 I570 (Wil), J41, IDCF IKBF AOD PFF 000 SFF 010 IRDR (WIA), 43, ICA) ICAL, J50, IC40, J02 Top PEF000T RSTMP tit; N0 CARRY 0 -------Er "" (p. oooo ISIO (WA), J43, LIBF J4) PFF 0001 LR6 WRK 5FF 1100 ISTO (TDa), IC40, J4, IJBF inventor. THOMAS E. 0580&NE BY 12-4-2- /-/2ea a ATTOAAWE 16 PATENTERFEB 23197 3,566.16O SHEET 14 OF 31 SUBROUTINE SUM 6 OO/O A/6/5 Q)0000 ICAL, J02, J24 COMPLEMENT ADD TRANSFER KBD 10 WKK : (E) 0100 - J43, IC4- - 3) AIKE As y SANS Nory 3. ALIKE s : N0 CAKKYd NVENTOR. THOMAS E. 05BOKWE BY 2-42-22-4 ATTO, WEYS PATENTED FEB23 (97. 3,566. l BO SHEET 15 OF 31 IRDR (Wil), ITB5, lC41, J51, K57 0001 IIBF, I570 (Wii) EXIT : (f51) = | IF CARRY SUBROUTINf 6 00 FIG 16 ADD ( tr. ) INVENTOR. THOMAS E. 05BOWA SE: BY (EE" 2-4-2TKANSFER VECTOK ATTOKWE/6 3,566, l8O PATENTED FEB 23197 SHEET 1.S OF 31 6UBROUTINE NORMALIZE S0-100 F/G/7 (0) 00II ISIOWA), J43, K24 <>JDK3> DIWIDE ; (k) 0000 MPy OR Act (WE) (KE) QUOTIENT 7 O of UNDERFLOW & DIW ICALJ00, J50J51, K24 LRS WRK EMPY ORACC. CONDITION OVERFLOW. DIW Q) JOI) ISIO/WIAJ43.IKBEJ4 ISTOIKEI), IKB OWERFLOW 4 MPY OR ACC PRODUCT O UNDERFLOW MPY NVENTOR THOMAS E. 05BORNE by 72%-e- 12 PATENTEDFEB23.97 3,566, 18O SHEET 17 OF 31 SELECT De <22> -o M O 5ELECT REGISTER TO BE 5AIFTED I570, IKBF, ICF (CFF) = 1000 O 1110 NVENTOR. THOMAS E. 05BORNE SUBAOUT/WE 5H/FT sa/O / A/G. 18 BY 2-4-2 - 24 ATIO/WE Y3 PATENTED FEB 23197 3,566, le O SHEET 18 OF 31 SUBROUTINE EXPOWENT UPDATE 50/10 A/G 2O TO CALLING KOUTINE NVENTOR SUBROUTINE COMPLEMENT Thomas E. Osborne F/G/9 ATTO&WE YS PATENTED FEB 23197 3,566, l8O SHEET 1.9 OF 31 ISIOWIAJ43, IICF, IC4IJB, KBF -0--- SUBROUTINE D///DE INVENTOR. 5 O/// A/G 2) THOMAS E. O5BOAWE BY 24%-2 r/22. A ATTOAME/6 PATENTED FEB 23197 3,566, l BO SHEET 2 O OF 31 0000 J4, IDBF, IUBF ITKB IST0 (Ki), IESF, K40, K4, J02 (5) KDR WIAN (CFF) = D9 +1 IKDK (Mi), J42, IDCF, K41, (I5707 - G 1000, -- - --- - ESTABLISH PKE -(...) y Q) IOI IKDR (KEI), J32 (K) 1100 IRD (KE), IDE,OIESFIlol(ISIO I570 (KEI), IIC, IESF, J5) INVENTOR. SUBROUTINE ENTEK. D/G/T 5 1001 A/G - 22 THOMA5 E. O5BOANE "24- / 12-4 ATTORNEY6 PATENTED FEB2397 3,566, l8O SHEET 21 OF 31 TRACE ANS KEYING DELAY ROUTINE DECODEly LEFT HALF Ne RESTORE RIGHT <32) TRACE - , HOLD DOWN HOLD LEFT SUBROUTINE DISPLAY 6 10/1 A/G-23 INVENTOR THOMAS E. 05BONE "2/4 - 2 ATTOWEY6 3,566.16 O PATENTED FEB2397 SHEET 22 OF 31 INVENTOR. THOMA5 E. 05BOAA/E BY we ATTOGAeys PATENTED FEB 2397 3,566.16O SHEET 24 OF 31 IRDR (wellite4.J32 Kso Yi INVENTOR. THOMA5 E. O5BORNE SUBROUTIME MBB BY 5/110 12%-2- ^ 12-e- FIG 26 ATTOAWE/6 PATENTED FEB 23197 3,566, l8O SHEET 25 OF 31 IC40, IC4I, ICCF IESF SUBROUTINE DIGIT ENTRY P05ITION INVENTOR. A/G 27 THOMAS E. O5 BOCWE "24- 12-ea Aft/0/AVE Y6 PATENTED FEB 2397 3,566.lsO SHEET 2S OF 31 IS I5TO (TD), IICF, IIIBF, IJBF 5UBROUTINE EXPOWENT UPDATE DIVIDE INITIAL/ZATION 5 IIII F16. 23 CD 0010 IRDR (KDs), IC40, IC41, ICCF (IESF () 0 || 0 IRDR (WDs), IC4I, IESF, IJBF INVENTOR. THOMA5 E, OSBORNE BY a- 2 AT TO RAVEYs PATENTENFEB23 (97. 3,566, l8O SHEET 27 OF 31 U" OR "S" (8) CD 44. 4 Cag Cao Cas vayav 7 ///ae/2 (S) O"E" OR 'O' , (U) OUTPUT FLIP FLOP Flg. 29 ( see- : (Q) to , t , t , t , t , J INPUT (CURRENT) K INPUT (CURRENT) l sees = NUMERIC5 GENERATED WITH CASCADED "E" TRACE3 A/6.3 - - - "E" TRACE FG. 3O INVENTOR. BY THOMAS E. O5606AE '4-224-7-12-24 ATTOKAVE/6 PATENTED FEB 23197 3,566, l8O SHEET 28 OF 31 +2.2 V LEFT DEF/ECTION CIRCU/7 F/G32 G) +2.2 V p0WW DEFLECTION CIRCUIT F/6. 33 RIGHT o IDRR () 22 v INVENTOR elGHT DEF2.ÉcTION CIRCUIT THOMAS E. 05BORNE A/G 34 Y 24%--- 2e ATTOEMEYS PATENTED FEB 23197 3,566, l8O SHEET 29 OF 3 LEFI (IGHT DOWN DJ4 DJ3 DJ2 DJ d) +24 y H H BIA5ING CIRCUITS - 3RPI A/G 35 BY ATTORNEYS PATENTED FEB 23197 3,566, l8O SHEET 30 OF 31 o--OZÒN oÖN|Z @00/ INVENTOR. THOMAS E. O5BOA/WE BY 12%-2- / 72-4 ATTOR NEYs 3,566, l8 O PATENTED FEB 23197 SHEET 31 OF 31 @- - BY AT70AME/6 3,566,160 SEMPLEFEDRACE-PREVENTING FLP-FLOPHAVENGA SELECTABLE NOSE IMMUNTY THRESEHOLD 2 FIG. 29 is a waveform diagram illustrating the operation of the flip-flop circuit of FIG.29; FIG. 30 is a diagram of the trace pattern on the output This invention relates to an electronic desk top calculator and to certain subcombinations therein which are useful in cathode-ray tube of the calculator; electronic desk top calculators and larger calculators of the FIG. 3 is a diagram illustrating how decimal numbers are data processing computer type. displayed from the trace pattern of FIG.30; One form of electronic desktop calculator is illustrated and FIG. 32 is a schematic diagram of the left deflection circuit described in detail herein. This calculator is designed for per for the cathode-ray tube; forming the standard arithmetic operations: addition, subtrac FIG.33 is a schematic diagram of the down deflection cir tion, multiplication, division, exponential functions, and cu O cuit for the cathode-ray tube; mulative operations involving these specific operations. The 34 is a schematic diagram of the right deflection circuit calculator is readily adapted for performing additional opera forFIG. the cathode-ray tube; tions, and as will be apparent hereafter, the principles of the FIG. 35 is a schematic diagram of the biasing circuits for the invention may be employed in calculators other than the 15 cathode-ray tube; specific electronic desktop calculator illustrated herein. FIG. 36 is a schematic diagram of the clock source used in The objects and advantages of the invention will be ap calculator; parent from the following description of an electronic desk theFIG. is a waveform diagram illustrating the operation of top calculator read in conjunction with the attached drawings the clock37source of FIG. 36; in which: FIG. 38 is a schematic diagram of the keyboard encoder FIG. is a diagram illustrating the manner in which the cal 20 employed in the calculator; and culator operates in response to operand (digit entry) keys; 39 is a schematic diagram of a removable tester used to F.G. 2 is a diagram illustrating the manner in which the cal testFIG. and service the calculator. culator operates in response to control operator keys; FIG. 3 is a diagram illustrating the manner in which the cal 25 GENERALOPERATION culator operates in response to arithmetic operator keys; The machine illustrated in the attached drawings can be di FIG. 4 is a diagram illustrating the manner in which the cal vided into three logical sections-an input section, an output culator operates in response to the multiplication key; FIG. 5 is a diagram illustrating the manner in which the cal section, and a processor. The input section consists of a manually operated keyboard culator operates in response to the divide key; FIG. 6 is a diagram illustrating the manner in which the cal 30 containing 23 data keys and a diode encoding matrix to generate a unique five bit code when each key is operated. culator normalizes numbers; The output section consists of a cathode-ray tube (CRT) FIG. 7 is a diagram illustrating the manner in which the cal and the associated circuitry necessary to display the contents culator operates in response to the accumulate keys, FIG. 8 is a block diagram of the electronic circuits em 35 of two registers contained within the processor. The contents of the two registers are displayed as two lines of decimal nu ployed in the calculator; FIG. 9 is a schematic diagram of typical circuits employed merals with the two lines arranged in upper and lower posi- . in the calculator to execute logic functions by power tions. The register occupying the lower position on the CRT is switching; the keyboard, or KBD, register. It displays the current numer FIG. i0 is a Karnaugh map illustrating the memory ad 40 ic input data. The contents of KBD are not altered, except for dressing arrangement employed for addressing each word in a sign change under circumstances to be described later, when the core memory of the calculator, arithmetic operations are executed. The upper position of the FiG. 11 is a Karnaugh map illustrating the memory ad display contains the contents of the answer, or ANS re dressing arrangement employed for addressing individual CRT gister. ANS always contains the answer to the last arithmetic characters within each word in the core memory of the calcu 45 term processed. Each of the ANS and KBD registers is stored lator; in memory and displayed on the CRT as a 10 decimal digit F.G. 12 is a detailed flow chart of the control logic of the number (hereafter called the mantissa) having a decimal point calculator; located between the most significant and second most signifi FIG. 13 is a detailed flow chart of the accumulate subrou cant digits. The mantissa is followed by two decimal digits, tine, SO called the characteristic, which locate the true decimal point FIG. 4 is a detailed flow chart of the multiply subroutine; of the number relative to the normalized position it occupies F.G. 5 is a detailed flow chart of the sum subroutine; in the mantissa. For example, the number 0.0125 is displayed F.G. 6 is a detailed flow chart of the add subroutine; as 1.250000000 -02. Thus, the smallest positive number F.G. 17 is a detailed flow chart of the normalize subroutine; 55 which can be displayed is 1.000000000 x 10-'. The largest F.G. 8 is a detailed flow chart of the shift subroutine; and negative numbers which can be displayed are st F.G. 19 is a detailed flow chart of the complement subrou positive 9.999999999 x 1099. time; The processor contains logical elements common to digital FIG. 26) is a detailed flow chart of the exponent update computers, i.e., flip-flops, gates, etc., a random access core subroutine; 60 memory, and means for receiving information from the input F.G. 2 is a detailed flow chart of the divide subroutine; section and sending signals to the output display section. FIG.22 is a detailed flow chart of the enter digit subroutine; With this general background, the operating characteristics, FiG. 23 is a detailed flow chart of the display subroutine; i.e., response to input data, can be described. Input data is FiG. 24 is a detailed flow chart of the subroutine used for grouped into two distinct categories, namely operands and determining arithmetic operators; F.G. 25 is a detailed flow chart of the subroutine used for 65 operators. The operands consist of the decimal digit entries zero through nine. The operators are divided into two sub determining the state of the machine; groups, namely control operators and arithmetic operators. F.G. 26 is a detailed flow chart of the MBB subroutine used The control operators are defined as ERR (error), EXP (ex for miscellaneous matters, ponent), ANS (answer), CHS (change sign), MEM (memo F.G. 27 is a detailed flow chart of the subroutine used for 70 ry), STO (store), KBD (keyboard) and DEC (decimal point). determining the position of entered digits; The arithmetic operators are ACC 0 (accumulate 0), ACC + FiG. 28 is a detailed flow chart of the subroutine used for (accumulate +), ACC - (accumulate -), X (multiply), and updating exponents and initiating the first portion of the divi sion process; FIG. 29 is a schematic diagram of the one of the flip-flop 75 circuits used in the calculator; (divide). The ERR control operator clears the keyboard to normal zero, e.g., a zero mantissa with a zero characteristic. 3,566,160 3 When an operand digit entry follows an arithmetic operator 4. e.g., STO followed by four results in the contents of ANS or an ERR, ANS or KBD control operator, the processor being sent to auxiliary storage register number 4. When a recognizes the operand as the most significant digit of a new MEM control operator is followed by an operand entry, the data entry, clears the mantissa and characteristic of KBD to contents of the auxiliary storage register defined by the zero, and enters the operand into the KBD register as the most operand digit are transferred into the KBD register. The con significant digit of the mantissa. The processor will not enter a tents of the source register remain unaltered in either process. digit into the second most significant position of the mantissa The ANS control operator transfers the contents of the until a nonzero digit operand entry is placed in the most sig ANS register into the KBD register. The contents of the ANS nificant position of the mantissa. register remain unaltered by this process. This allows answers The DEC (decimal point) control operator provides suffi 10 of previous arithmetic terms to be used as factors of new ters. cient information to the processor to determine the proper digits and sign of the characteristic. Thus, each digit entry The KBD control operator provides a new user with con tinuity in performing arithmetic operations. It is used to simu operator after the first not only enters the digit in the KBD mantissa, but also increments the KBD characteristic until the late a transfer of the contents of the KBD register into the decimal point control operator is operated. For instance, the 15 KBD register. The usefulness of this operator is discussed later in the detailed description of FIG.2. number 632.14 is entered in KBD by six key operations as fol lows: When the arithmetic operator preceding an ACC 0 KEY OFPERATIONS CRT DISPLAY OF KBD arithmetic operator was an ACC 0, ACC +, or ACC -, the 0.00000000000 20 contents of the ANS register are set to normal zero, and the 6.00000000000 contents of the KBD register are algebraically added to the 6.30000000001 contents of the ANS register. In effect, the contents of the 6,32000000002 KBD register are transferred into the ANS register. When the arithmetic operator preceding an ACC + decimal point 6.32000000002 6.321000000 O2 25 arithmetic operator was an ACCO, ACC +, or ACC -, the 4. 632140000002 contents of the KBD register are algebraically added to the When a decimal point entry follows an arithmetic operator, or contents of the ANS register. The sum appears in the ANS re an ERR, ANS or KBD control operator, the processor recog gister and the contents of the KBD register are unchanged. nizes the decimal point as the first entry of a forthcoming When the arithmetic operator preceding an ACC operand and clears the KBD register to zero. A decimal point 30 arithmetic operator was an ACC 0, ACC -, or ACC +, the control operator is not required when entering integers. When sign of the KBD register is changed and the new contents of the initial key of an operand is the decimal point, successive the KBD register are algebraically added to the contents of the operand keys decrement the characteristic of KBD until a ANS register. The sign of the KBD register is changed by the nonzero number has been entered in the most significant posi process. Note that if a second ACC - arithmetic operator is tion of the KBD mantissa. 35 executed, the original contents of ANS and KBD will be The EXP control operator informs the processor that the reestablished. Thus, it is possible to restore the contents of the characteristic of the KBD register is to be changed. The ANS register by executing two consecutive ACC - arithmetic processor responds by clearing the characteristic of the KBD operators. register to zero. When operand digit entries follow the EXP When the arithmetic operator preceding a X arithmetic control operator, they enter (modulo 100) into the charac 40 operator is an ACC 0, ACC -, or ACC +, the processor teristic of the KBD register. The EXP feature allows the defines the contents of the KBD register as the multiplicand of characteristic of an operand to be altered without changing a forthcoming product. As explained below, the contents of the mantissa. It also allows the user to enter operands with KBD are defined as the multiplicand by transferring the con large negative or positive exponents without inserting leading tents of KBD to a third register called the working register or trailing zeros. For example, Avogadro's number (6.02 X 45 (WRK) without changing the contents of KBD. 10) can be entered into the KBD register by six key opera When the arithmetic operator preceding a X arithmetic tions as follows: operator is a X, the processor algebraically multiplies the KEY OPERATIONS CRT DISPLAY OF KBD previously defined multiplicand times the contents of the KBD 6 6.00000000000 register and identifies the product as the multiplicand of the 50 O 6.00000000001 forthcoming product. 2 6.02000000002 When the arithmetic operator preceding a arithmetic EXP 6.02000000000 operator is an ACC O, ACC -, or ACC +, the processor 2 6.02000OOOOO2 defines the contents of the KBD register as a dividend of a 3 6.020000000 23 55 forthcoming division. The CHS control operator changes the mantissa sign unless When the arithmetic operator preceding a arithmetic the preceding control operator was an EXP in which case the operator is a X, the processor algebraically multiplies the con characteristic sign is changed. Additional CHS control opera tents of the KBD register times the previously defined mul tors cause repeated sign changes. When the CHS control tiplicand and defines the product as the dividend of the operator follows an arithmetic operator or an ERR, ANS or 60 forthcoming division. KBE) control operator, the sign of the KBD register is changed When the arithmetic operator preceding a arithmetic as stated above. However, if an operand digit entry or a operator is a , the processor algebraically divides the previ decimal point follows the CHS control operator, the processor ously defined dividend by the contents of the KBD register recognizes the CHS control operator as a signal implying that and identifies the quotient as the dividend in the forthcoming a new negative mantissa is going to be entered into the KBD 65 division. register. The processor responds by affixing a negative sign to When the arithmetic operator preceding a X arithmetic operator is a , the processor algebraically divides the previ the mantissa when the decimal point control operator or the first operand digit is received. In other words, the negative ously defined dividend by the contents of the KBD register sign may be affixed to the mantissa of a KBD entry prior to en and identifies the quotient as the multiplicand of the tering the first digit of the mantissa, or at any time following 70 forthcoming product. the entry of the first digit of the mantissa. When the arithmetic operator preceding an ACC () An operand entry is also used to define auxiliary storage re arithmetic operator is a X, the processor changes the ANS re gisters within the processor. When an operand entry follows a gister to normal zero, then algebraically multiplies the con STO control operator, the contents of the ANS register are tents of the previously defined multiplicand times the contents sent to the auxiliary storage register defined by the operand, 75 of the KBD register and their product is algebraically added to 3,566,160 5 6 store the most significant and least significant digits of the characteristic. The remaining character, defined as IA, is used for storing intermediate results of computations and control the contents of the ANS register. In effect, the product is placed in the answer register. When the arithmetic operator preceding an ACC + arithmetic operator is a X, the contents of the KBD register information. Each character consists of five bits, B, Ba, B, and B, and and the previously defined multiplicand are algebraically mul tiplied and their product is algebraically added to the contents Bo. These characters are stored in standard 8-4-2-1 BCD code with B. and Bo being the most significant bit (MSB) and of the ANS register. When the arithmetic operator preceding an ACC - least significant bit (LSB) respectively. B of D and E hold arithmetic operator is a X, the processor first changes the sign the signs of the mantissa and characteristic respectively. of the KBD register, then forms the algebraic product of the 10 The core memory uses the word access storage system by FIGS. 4.1, 4.3, 8.2e, and 8.15a of the book previously defined multiplicand and the contents of the KBD described Square Loop Ferrite Circuitry by C. J. Quartly (Iliffe Books, register, and algebraically adds their product to the contents Ltd., London). A memory cycle, similar to that in an IBM 704 of the ANS register. When the arithmetic operator preceding an ACC 0 15 digital computer, is used; thus, reading out of memory arithmetic operator is a -i-, the processor changes the ANS to becomes a nondestructive process while writing into memory destructive process. normal zero and then algebraically divides the previously is aFive flip-flops (the bit flip-flops or BFF) are used to hold defined dividend by the contents of the KBD register and their both the character read out of memory and the one to be writ quotient is algebraically added to the ANS register. In effect, ten into memory. The bit flip-flops are also connected to logi the quotient is placed in the ANS register. 20 cal circuitry allowing them to be incremented or decre When the arithmetic operator preceding an ACC + Incrementing occurs in the four LSB (B3, B2, B1, Bo) arithmetic operator is -i-, the processor algebraically divides mented. and is cyclic 0 through 9 in 9-4-2-1 BCD code. When the previously defined dividend by the contents of the KBD only the contents of BFF are incremented from 9 decimal (1001 bi register and algebraically adds the quotient to the contents 25 nary or 11 octal) to 0 decimal, a signal is given to set a carry of the ANS register. to a 1 condition. Decrementing the BFF results in the When the arithmetic operator preceding an ACC - flip-flop four LSB being reduced by one count in straight binary arithmetic operator is , the processor first changes the sign of fashion. Decrementing zero causes 1111 binary (17 octal) to the KBD register, then forms the algebraic quotient of the in the four LSB of the BFF. previously defined dividend and the contents of the KBD re 30 appear Any character in memory can be selected by inserting its gister and algebraically adds the quotient to the contents of address into flip-flops used to identify one of the 13 character the ANS register. and any one of the 14 registers. (Quartly, IBID.) This mode of operation allows the user of the calculating locations To facilitate detailed system description, the following machine to form the answer to any arithmetic expression conventions arethe used: made of terms containing factors of the form 35 1. Individual characters in memory are referred to by prefix NXNX P o XN ing the character identifier with the first letter of a work ing register or an M, for the i' auxiliary storage register. DXDX . . . XD; For example, KDs, AEo, and WIA refer to the MSD of the by following each term with either ACC - or ACC + depend KBD mantissa, the LSD of the ANS characteristic, and ing upon whether the algebraic sign of that term is negative or 40 the IA character of WRK respectively. positive respectively. Moreover, each multiplier is preceded 2. The sign of the mantissa and characteristic are identified by a X arithmetic operator and each divisor is preceded by a -iby suffixing the D or E identifiers by the letter S. Thus, arithmetic operator. Those and only those arithmetic opera the KBD mantissa sign becomes KDS (which is contained tors required to uniquely defined the problem are used. This in K Ds B) and the ANS characteristic sign becomes AES differs from other calculating systems which require inter 45 (which is contained in A E B). mediate transfers or extra arithmetic operators to accomplish 3. The entire mantissa or characteristic is referred to by the same type of problem. prefixing the letter D or E, respectively, with the ap It is also important to notice that the arithmetic notation dif propriate register identifier. For example, the mantissa of fers from the Lukasiewicz (Polish) notation, often called 'ANS becomes AD and the characteristic of TMP Parenthisis free' notation, in that the X arithmetic operator 50 becomes TE. precedes the multiplier instead of follows it. Similarly the 4. When parentheses enclose a register identifier, they sym arithmetic operator precedes the divisor instead of following bolically imply "the contents of.” This notation is used to it. This feature assists the user because the X and arithmetic differentiate between the address of a memory area and operators precede the multiplier and divisor respectively when the information stored in the address. For example, the 55 written in standard arithmetic form. symbol (KD) means the contents of the KBD mantissa. The arithmetic notation also differs from the parenthesized 5. The arrow,->, replaces the words "go into.” notation commonly used in digital computer compilers such as Some rudementary operations may be described with this FORTRAN and the electronic calculating machines marketed symbolic language and will help explain the detailed system by Mathetronics, Inc., in that none of its arithmetic operators 60 operation. can be shown to be uniquely equivalent to the open or closed Suppose the contents of KDs are to be incremented by one parenthesis. count. The logical operations would be to set the address flip flops to KDs, execute a read cycle, increment the BFF, and ex GENERAL SYSTEM ecute a store cycle. These operations are symbolically stated The calculator contains a memory consisting of four work 65 as (KD) + i ->KD which reads "the contents of the address ing registers and ten or less auxiliary storage registers with KDs, plus one, go into KDs." Similarly, if the contents of WEo each register consisting of 13 characters of five bits each. The are to be transferred to TEo, the apparatus includes control working registers are defined as WRK (working register), sequencing to select the address of WEo, execute a read cycle, TMP (temporary register), KBD (keyboard register), and select the address of TEo, and execute a write cycle. This is ANS (answer register). The auxiliary registers are defined as 70 written symbolically as (WE) -> TEo which reads "the con tents of the address WEogo into TEo.' MEM 0, MEM1, ... MEM 9. Ten of the 13 characters in each All of the detailed logical characteristics of the calculating register are used to store the mantissa. These mantissa charac machine will be described by using symbolic language, similar ters are defined as D9, D8, D, ... Do with Ds being the most sig nificant digit (MSD) and Do the least significant digit (LSD). to the two preceding sample expressions. Proper time Two of the remaining three characters, E, and Eo, are used to 75 sequencing of the logical operations is given by placing the 7 3,566,160 symbolic expressions in flow charts (IBM Form A22-6503-2, Pgs. 31,33). The flow chart is a particularly convenient means for describing the system logic for two reasons: (1) translating information from a flow chart into logical design set-reset equations is a process well known to logical designers, and (2) 8 SOM = -010-. This encoding directs the processor to enter the operand into the proper KBD mantissa character location. The address of the proper location is stored in TIA and is up dated each time a new operand is entered. The flowchart covering the proper response to operand the logical equations and/or circuit diagrams are voluminous, keys is shown in FIG. 1. Throughout various FIGS. in the flow making it difficult to understand the system operation without charts, certain states are referred to by letter references in the the aid of flow charts. FIGS. In this description, the letter references are prefaced by By using the random access capabilities of the memory 1 O the number of the FIG. in which the reference appears. In system, the contents of ANS and KBD are displayed on a state 1A, the SOM is obtained from WIA. If the SOM is a PKE cathode-ray tube employing deflection circuitry and logic or NKE, signifying a new mantissa entry, zero is stored into described below. The resultant two line display has the con TIA, states 1B and 1C, thereby initializing so that the operand tents of ANS displayed above the contents of KBD. From left will be stored in KD as directed in L. After initializing TIA, to right, the characters displayed are mantissa sign, D9, 15 the KBD register is cleared to positive zero, 1D, if PKE or to decimal point, D, D, D6, D5, D4, D3, D2, D1, Do, blank, negative zero, 1E, if NKE. characteristic sign, E1, and Eo. Positive signs are implied by no Following the PKE or NKE zeroing, the SOM is updated to sign at all, while negative signs are displayed in their conven 00100 if the operand key actuated was not a zero, 1G. The tional form. The characteristic locates the decimal point rela SOM is left at PKE or NKE if the operand key was a zero key. tive to its displayed position. As an example, the number 112 20 The logic directing control to 1H determines that the is displayed as -1.12000000002. The number zero is dis characteristic should be incremented by one count. This logic played by having all characters set to zero. Signs of the charac allows the processor to assign the proper exponent to integers teristic or mantissa can be either positive or negative when dis and decimal fractions. playing Zero. The operand is stored into the proper mantissa character by All information enters the processor via 23 manually 25 the logic provided in 1K and 1L. operated keys. Logically, these keys are organized into three The SOM directs the processor to enter the operand into groups: (1) operands-0,1,2,3,4,5,6,7,8, and 9; (2) control the KBD characteristic in states 1M and 1N. operators-ERR, EXP, ANS DEC CHS, MEM, STO, and When the SOM directs control to 1P or 10, the auxiliary KBD; and (3) arithmetic operations-X, , ACC 0, ACC -, 30 storage features are put into effect. State IR sets the SOM to PKE. ACC +. Each of the keys is encoded into a unique five bit code by a diode encoding matrix. PROCESSING CONTROL OPERATORS The MSB, B, of the encoded signal differentiates between operators and operands. The four LSB of each operand code FIG. 2 shows the processor, response to control operator encode the operands in straight 8-4-2-1 BCD code. keys. Each of the eight unique control operator codes directs 35 An information line enters the processor from the keyboard control to one of the eight entrances shown. indicating that a key is down. This signal commands the In state 2A, (ANS) -> KBD. This allows the answer of a machine to exit from the display routine and to begin previous term to be used as a factor in a new term. State 2B processing new data. A detailed analysis of the operand entry establishes a PKE condition in SOM. The KBD control opera routine follows: 40 tor is not required for proper machine operation. Its purpose is to give continuity to operations using the (KBD) as factors in a PROCESSING OPERANDS computation. For example, a term can be cubed by either of When an operand key is depressed, the processor reads the following methods: (1) enter factor, followed by the X, WIA to obtain the State of the Machine (SOM). This informa KBD, X, KBD, and ACC 0 operation keys; (2) enter factor, tion will tell the processor whether the operand is a character 45 followed by X, X, and ACC0. The inexperienced operator ap of the KBD mantissa, a character of the KBD characteristic, or preciates the continuity of the first method where the struc an auxiliary storage register address. The pertinent states of ture has operands and operators alternating. The experienced the SOM as they appear in WIA are given below. Dashes in operator will prefer the second method because it involves dicate don't care conditions. fewer key operations. SOM 00000. This encoding identifies a "Positive 50 In states 2D and 2E, the sign of KES and KDS are changed, Keyboard Entry' or PKE. It directs the processor to zero the depending upon the SOM. If the SOM is PKE in 2C, it will be KBD register and to enter the operand into KDs as a positive changed to an NKE. This operation in effect prepares the number. machine to enter a negative mantissa if the next key depres SOM 10000. This encoding identifies a "Negative sion is an operand (state 2E, FIG. 1) or a decimal point (state Keyboard Entry' or NKE. It directs the processor to zero the 55 2J, FIG. 2). KBD register and to enter the operand into KD as a negative States 2F and 2G update the SOM to recognize the next number. operand as an auxiliary storage address. (Refer to FIG. 1, SOM = 01.... This encoding informs the processor that the states 1P and 10). STO key has preceded the operand entry. The operand key 60 In states 2L and 2J, the processor zeros KE to minus zero depressed defines the address of an auxiliary storage register. and zeros KD to plus zero for PKE or minus zero for NKE. In As a result, (ANS)--> M where i is the operand key actuated. state 2H, it then updates the SOM to a “decimal fixed” (1 -> Note: on any interregister transfers, only the characteristic Bo) and "enter digit' (1->B) state. and mantissa along with their signs are transferred. The IA When an EXP control operator occurs, state 2M, the SOM characters do not transfer. 65 is updated to enter further operands into KE (FIG. 1, states SOM = 11.... This encoding informs the processor that the 1M and 1N) and zeros KE to positive zero in state 2N. MEM key has preceded the operand key. The operand key In state 2P, the ERR control operator directs the processor defines the address of an auxiliary storage location. As a to set the SOM to PKE. The KBD register is then cleared to positive zero in 20. result, (M)->KBD. SOM = -011-. This encoding directs the processor to put 70 (KE)->KE, and to enter the operand into KEo. PROCESSING ARITHMETICOPERATORS SO