Historical Document · 1970
US Patent 3,526,760: Square Root (R. A. Ragen, Friden EC-132)
The EC-132's square-root method by subtraction of successive odd numbers, filed 1 April 1966 and granted 1 September 1970.
Historical Document · 1970
The EC-132's square-root method by subtraction of successive odd numbers, filed 1 April 1966 and granted 1 September 1970.
Sept. 1, 1970 R. A. RAGEN SQUARE ROOT CALCULATOR EMPLOYING A MODIFIEl) 3,526,760 SUM OF THE ODD INTEGERS METHOD Filed April 1, 1966 19 Sheets-Sheet l 3 ROBER A. RAGEN Ef INVENTOR. by ?et de4.7% AT TORNEY Sept. 1, 1970 R. A. RAGEN SQUARE ROOT CALCULATOR EMPLOYING A MODIFIE) 3,526,760 SUM OF THE ODD INTEGERS METHOD Filed April 1, 1966 l9 Sheets-Sheet 2 14) MEMORY 10N 12) ARTH METC UNIT Ef SHIFT UP SHIFT DOWN Era * TIME -< 28) --DATA FLOW s -(- 2 DELAY LINE RRR,R,R,R,R,R,R,R,R,R, C2 C3 Ef a -C- Sept. 1, 1970 SQUARE ROOT CALCULATOR R. A. RAGEN 3,526,760 EMPLOYING A MODIFIED SUM OF THE ODD INTEGERS METHOD Filed April 1, 1966 9 Sheets-Sheet S 28 DISPLAW DISPLAY-5 END OF C 15 TME Ef Es DATA PLOW rt-A -- . . . . . ONE WORD TM H --ONEM TM coc1 c2C3C4 C5 C6C7c8|C9|CoC (C12C 13C 14C15 N / NN / Y ONE N N START PULS - /REGISTER TIMEN - - N. R. R. R. R. R. R. N N 1 F- ON BIT TM N BOB B2B3B4B5Be|87 B3B Bo Bill B12B12B14|BIs a Sept. 1, 1970 R. A. RAGEN 3,526,760 SQUARE ROOT CALCULATOR EMPLOYING A MODIFIED Filed April 1, 1966 ~ ~|~<\! NWOG|11HS SUM OF THE ODD INTEGERS METHOD 9 Sheets-Sheet 4 Sept. 1, 1970 R. A. RAGEN SQUARE ROOT CALCULATOR EMPLOYING A MODIFIE) Filed April l, 1966 3,526,760 SUM OF THE ODD INTEGERS METHOD 9 Sheets-Sheet –T§XIOEF || 2 0 d 0 TOTTOTTIGTÕTTTOTIÐ, TTTOTIEGT TODTOITOI TOTOTIŽ TLITOGTOT TLOLTI TITZTTLO ? || 0 DO 9 || D? || 2 I0 DO I | 0 ??| 2 || 0 TIL 10 BHTEVTFE7T 3 || s l Sept. 1, 1970 R. A. RAGEN SQUARE ROOT CALCULATOR EMPLOYING A MODIFIED Filed April 1, 1966 SUM OF THE ODD INTEGERS METHOD DPS O DPS >- 19 Sheets-Sheet & 52 E) 3,526,760 8 DPC . 08 DECMAL PONT COUNTER OO --a Sept. 1, 1970 R. A. RAGEN SQUARE ROOT CALCULATOR EMPLOYING A MODIFIED Filed April 1, l966 3,526,760 SUM OF THE ODD INTEGERS ME HOD 9 Sheets-Sheet ', Sept. 1, 1970 R. A. RAGEN SQUARE ROOT CALCULATOR EMPLOYING A MODIFIED 3,526,760 SUM OF THE ODD INTEGERS METHOD Filed April 1, 1966 R 9 Sheets-Sheet 3 PC 15 DECMAL ALGN PC1 SAT DOWN R3 R4 SAT UP RO STEP TO PSA PC2 SHIFT R, R2, R3, R4 UP PC4 CLEAR RO R.S. DPS NO DPC = O 2 YS PC 14 St DPS S T RO LL R + (20+ 1) PC5, PC4 SAT R2 LET S T R LT DPC = 0 PC5 PCI2, PC 13 NCRMN DPC S. DPS P DPC = O R + RO PC6, SHIFT R2 LEFT ST R LIT YS ... No CARRY OFLOW. S. 2 PC7 PC 10 INCREMENT DPC PDPC-0 Ri-Ro PC8 PC9 R-cool YES (cAnyorows) PC ADD TO RO is Sept. 1, 1970 R. A. RAGEN SQUARE ROOT CALCULATOR EMPLOYING A MODIFIEI) 3,526,760 SUM OF THE ODD INTEGERS METHOD Filed April 1, 1966 l9 Sheets-Sheet Sept. 1, 1970 R. A. RAGEN 3,526,760 SQUARE ROOT CALCULATOR EMPLOYING A MODIFIEl) SUM OF THE ODD INTEGERS METHOD Filed April 1, 1966 9 Sheets-Sheet 0 ENTER SHIFT LEFT (FROM 256 FIG.19) y ENTRY COUNTER O32 - -- - - - - - - - - - -214 ----------- O EF I -12V | " : " COUNTE ..., -- - - --mir H--- man - - - - -u- - - - run mur -m-, m- - - - - Sept. 1, 1970 R. A. RAGEN SQUARE ROOT CALCULATOR EMPLOYING A MODIFIED SUM OF THE ODD INTEGERS METHOD Filed April 1, 1966 3,526,760 l9 Sheets-Sheet ll. Sept. 1, 1970 R. A. RAGEN SQUARE ROOT CAL CULATOR EMPLOYING A MODIFIED SUM OF THE ODD INTEGERS METHOD Filed April 1, 1966 S-10 ZZZ 3,526,760 l9 Sheets-Sheet la Sept. 1, 1970 R. A. RAGEN SQUARE ROOT CALCULATOR EMPLOYING A MODIFIED Filed April 1, 1966 3,526,760 SUM OF THE ODD INTEGERS METHOD 9 Sheets-Sheet l5 09 '?i]· DI 1 O 0 + 0 G ? KHIOMOTHWO 80d 040d + Sept. 1, 1970 R. A. RAGEN SQUARE ROOT CALCULATOR EMPLOYING A MODIFIED 3,526,760 SUM OF THE ODD INTEGERS METHOD Filed April 1, 1966 l9 Sheets-Sheet la H Sept. 1, 1970 SQUARE ROOT CALCUATOR R. A. RAGEN 3,526,760 EMPLOYING A MODIFIE) Filed April 1, 1966 SUM OF THE ODD INTEGERS METHOD Sept. 1, 1970 R. A. RAGEN SQUARE ROOT CALCULATOR EMPLOYING A MODIFIED Filed April 1, 1966 /12 3,526,760 SUM OF THE ODD INTEGERS METHOD 19 Sheets-Sheet les Sept. 1, 1970 R. A. RAGEN SQUARE ROOT CALCULATOR EMPLOYING A MODIFIEl) SUM OF THE ODD INTEGERS METHOD Filed April l, 1966 -la Cs S. S. SS US Cd. s Y S S. S. O SS S as S so O S CNA a. NY Qd w e & ca S. S as CS) C li) DC Cd QNs R D Q-d t l9 Sheets-Sheet l', tl- S. 3,526,760 CSN OO Sept. 1, 1970 Filed April 1, 1966 L U Z s - > C O O R. A. RAGEN SQUARE ROOT CALCULATOR EMPLOYING A MODIFIED SUM OF THE ODD INTEGERS METHOD 3,526,760 9 Sheets-Sheet l8 Sept. 1, 1970 R. A. RAGEN 3,526,760 SQUARE ROOT CALCULATOR EMPLOYING A MODIFIED SUM OF THE ODD INTEGERS METHOD Filed April 1, 1966 l9 Sheets-Sheet 9 s: r (S : United States Patent Office 3,526,760 MODIFIED SUM OF THE ODD INTEGERS SQUARE ROOT CALCULATOR EMPLOYING A 3,526,760 Patented Sept. 1, 1970 2 tially the same ease as other arithmetic functions per formed by the calculator. When a series of numbers are entered into the calcula tor by manipulation of the keyboard, it is considered de METHOD sirable that a cumulative sum of the entries be tempo Robert A. Ragen, Hayward, Calif., assignor, by mesne rarily recorded so that a running check of the computa assignments, to The Singer Company, a corporation of tion in a problem may be maintained. This is of consider New Jersey able assistance, not only to casual users of the calculator Filed Apr. 1, 1966, Ser. No. 539,569 with limited experience, but also to skilled operators of Int, C. G06f 7/48 U.S. C. 235-158 18 Claims 0 calculating machines. The novel method employed in the present invention for deriving a square root is a modified "sum of the odd integers' method. The "sum of the odd integers' method ABSTRACT OF THE DISCLOSURE is known as a method of extracting a square root, but it A calculator is disclosed for deriving the square root 15 is not easily adapted to digital techniques, and until the of an operand according to a modified sum of the odd present invention, a practical manner of utilizing this integers method. The square root is obtained by arranging method had not been known. the operand in consecutive pairs of contiguous digits and Odd integers are the whole numbers 1, 3, 5, 7, 9, 11, performing a plurality of series of successive substrac etc. If such a succession of odd integers (an odd order tions on several partial operands. Each partial operand 20 arithmetic progression) are added, each summation will comprises a pair of digits arranged to the right of the last result in a perfect square. A perfect square is, of course, a non-negative remainder from the previous series of Sub number whose square root is a whole number. This is tractions. Circuitry is provided for decimally aligning the illustrated by the following table: entered operand and the derived square root in accord ance with the number of digits desired to the right of the 25 (1) 1-0=1-12 (2) 1--3=4=22 decimal point. (3) 1--3--5=9=32 -- (4) 1--3-4-5-7=16=42 This invention relates to improvements in electronic 30 (5) 1--3--5-7--9=25=52 By adding the next higher odd order integer to each calculators and more particularly, but not by way of preceding summation, all existing perfect squares are pro limitation, to an electronic calculator which simply and duced, with none being omitted. It should also be noted quickly derives the square root of a number, the square that the number of odd order integers in each summation root being correctly decimally aligned. The invention also provides for the cumulative counting of the entry of 35 is the square root of the sum. In example five of the pre ceding table, there are five parts to the summation, and each complete number into the calculator. Electronic computers with the capability of extracting five is the square root of twenty-five. This observation is true for any combination of successive odd integers. the square root of an operand are known in the art, and The square root of a number may be extracted by re have provided a significant improvement in the operation of numbers over mechanical calculating machines. There 40 versing this procedure. In this instance, the successive odd integers starting at one are subtracted to arrive at the are digital computers, presently known in the art, which Square root. The following example illustrates this: provide highly accurate and extremely fast calculations. By utilizing sophisticated circuitry, these present digital computers can be adapted to derive the square root of a number. However, due to the extraordinary speed re 45 quirements of these machines, this added capability re sults in a disproportionate increase in cost. 16 -l. 15 -3 12 -5 7 -7 5 12 7 0 In the presently emerging market for deck-top digital computers and electronic calculating machines, simplic (1) (2) (3) (4) ity of design and reasonableness of cost are important 50 considerations. The cost of adapting a desk-top electronic calculator to derive a square root using present known methods would be economically prohibitive. Also, while The number of successive subtractions is the square the speed requirements of a deck-top electronic calcula root. tor are lower than that of a large digital computer, none 55 This is a satisfactory method for use with perfect theless, speed is a consideration. It is desirable in the der squares. A related method of deriving the square root is ivation of a correct decimally aligned square root by a accomplished by applying a simple formula rather than desk-top electronic calculator that the time required for counting the subtractions to arrive at the square root. this derivation not to differ substantially from that re This formula is represented by the equation R=(N-1)/2 quired for the performance of other functions of the ma 60 where N is the last integer to be successfully subtracted chine such as multiplication and division. (no overdraft), which is sometimes called the "partial It is also desirable for an operator of the electronic root” and R represents the square root. calculator to be able to easily perform a square root oper In an example of extracting the square root of 64, it ation with only an absolute minimum manipulation of is obvious that the last number that could be successfully the keyboard. An advantage of electronic calculators 65 subtracted would be fifteen. By adding one to fifteen, over rotary mechanical calculating machines is that many which would be sixteen, and then dividing by two, the arithmetic functions may be performed in a simpler man eight would be the square root of sixty-four. ner, thereby permitting use of the machine by a relatively This method, which has been presently shown, is valid untrained operator. In furtherance of the objective of for small numbers but is unduly cumbersome for large permitting complete operation of the calculator by an 70 numbers. Since the number of subtract cycles is equal operator possessing only limited training, the square root to the square root of the number, an excessive length of function of the calculator must be initiated with substan time is necessary to complete a problem using large num 3,526,760 4. each of the above subtract cycles into two steps. The table 3 bers. Thus, this method, although valid, does not repre sent a practical solution to the problem of extracting the below illustrates how this is done: Square root. A modification of this method of extracting the square root provides for the number, starting at the decimal point, to be divided into pairs of digits called "couplets.” Beginning at the most significant couplet, the answer may be derived, one digit being produced for each couplet. However, the couplets must be operated upon in a way that is somewhat different than was done in the previous examples. If, for example, the number 441 is to have its square root extracted, it appears as 04 41 when divided into couplets. The root of each couplet will become one digit of the final square root, which will have two digits to the left of the decimal point. However, the root of 04, and the root of 41 cannot be combined in any way to pro duce the root of the original number. The first step is to operate upon the most significant couplet by subtract ing successive odd integers as shown below: 04 03 -1 -3 03 00 Normal method 5 Stact Modified Imethod int. --------------------------------O 8-- - - - - - - - - - - - - - - 4----------------5----------------- Stact Odd integer 1st pair.- : (1) 8-1-1; 0+1-1. 8 2nd pair- (3) +1-2; 2+1-3. 5 3rd pair.-- 6 (6) SH-3; 3+2-5. 7 4th pair- () +1-4; 4+3-7. 95th pair- 8 () +1-5; 5+4-9. It is to be noted that for each normal cycle, there are two subtractions in the novel system. The first half of the novel subtract cycle uses the previous integer developed in the prior step, while the second subtract cycle comprises 20 a first subtraction by zero, followed by a second subtrac tion by one (0-1); the second subtract cycle comprises a first subtraction by one followed by a second subtraction by two, and so on. Since there are twice as many subtract cycles as before, The method now provides for a one to be added to the three so that 3-- 1 =4, and this number is used to 25 it is not necessary to divide by two at the final step. The last successful subtract is the square root by this novel method. A complete example to four significant digits in the root is given below to illustrate the way the method begin operation on the second couplet. First, however, since the partial root for the most significant couplet is works: l8l in couplets (O). 8) O 8. Subtract-OO Pair (l) N2. Subtract -19 - (1 moved left Pair (1) S. one place) Ola Add l OO as Remainder Successfull Ol ill - (Addl.) Subtract l-l. Last 60 Subtract Overdraft) Pair (3) S3 12 - (Add. 1) Restore) 37 i; 125 Pair (5 Y532 -as (Addl.) Remainder Tast Successful/ l3 Subtract Overdraft) Restore) The last successful subtraction yielded the number thirteen, and the Square root of 181 is 13 plus a decimal amount. This decimal amount can be found by con tinuing the subtractions using another couplet (00) and in the tens column of the final result, it must be altered by multiplying by ten. The second step is to use this result 4x 10-40, add one, and begin operations on the second couplet. 41 -41 55 00 Now applying the formula, we have 60 (41-1)/2=42/2=21. Thus, the square root of 441 is 21. In this example, there was no remainder so that the problem is completed at this point. While the method described of utilizing couplets in the derivation of the square root could possibly be imple mented by digital techniques, the final step of dividing by two could add an amount of time to the total operation as to make it inacceptable for use in an electronic desk 70 top calculator. The previous examples used successive odd integers in the subtraction process, as 1, 3, 5, 7, 9, etc. The final step in the process was the division by two. However, the novel method of extracting a square root as utilized in this invention produces the same end result by separating whatever remainder is left. In this case 12. Remainder N Coupiet Added btaic Subtract 3O moved left left one place 3. lace) Subtract 3. Pair (533 3) - (Add l ) fairs, 35 32 - (Add 1. 676 Subtract - 32 Pair (5) S5: I - (Add l) l Subtract Pair (7) Y5-(Aaal) ll. - Realinder Last Successful Subtract Pair - 133 278 31. O 132 Stift) Restore) p 5 3,526,760 6 A means is also provided for restoring to the second register the value of the first subtrahend if the remainder approximation of the square root of 181, then is 13.4. in the first subtraction is negative, and for restoring to If more decimal places are desired, then another couplet the second register the values of the first subtrahend and (00) is used with the remainder each time for each 5 the second subtrahend if the remainer in the second sub decimal place. traction is negative. A means is also included for shift In the foregoing illustration of extracting a Square ing the third register one digit to the left after the value root, the odd integers were found by successfully using in the second register has been restored to the value it the last numbers successfully subtracted as the first step had prior to the subtraction pair having a negative re in each subtract cycle, then adding one for the Second 10 mainder. A means responsive to the number of digits re moved from the first register is provided for inhibiting step of the cycle. The odd integer can also be found further digit removal once a predetermined number of by adding one to the last number successfully subtracted said digits has been removed. in the first step of the new subtract cycle, and for the In order to provide correct decimal alignment for the second step using the last number without adding one. extracted square root there is included a counter which In other words, mathematically it does not matter in assumes a first count configuration responsive to an indi which step of the subtract cycle that the one is added; cator of whether the number of digits appearing on one the sum of the two steps will still result in the next odd integer. side of the decimal point in the operand is odd or even and is stepped twice for each couplet removed from the This is the method used in the illustrated embodiment of the present invention. In the first step of each sub 20 first register utnil a configuration representing zero is reached, then the counter assumes a second count con tract cycle, one is effectively added to the last number figuration representing the number of digits right of the successfully subtracted without, however, affecting the decimal point in the operand and which determines the retention of the last number. As the second step in each pair, the retained last number is subtracted. If both pairs number of digits which will appear to the right of the of subtracts are successful, then one is directly added to 25 decimal point in the extracted square root and is again counted to zero, the further removal of digits from the the last successfully subtracted number, which then is operand being inhibited when the counter assumes a zero used in the next subtracted cycle. It is important to note count for the second time. that each subtract in a pair of subtracts must be success Accordingly, an object of this invention is to provide ful before the number representing the last successful 30 an improved electronic calculator and novel method for subtract is actually changed. quickly and simply extracting the square root of a In accordance with one exemplary implementation of number. the novel method of this invention, circuity is provided for extracting the square root of an operand in a serial Another object of this invention is to provide an elec digital calculator which includes a recirculating memory tronic calculator for extracting the square root of an loop having information stored therein the form of a data 35 operand in a manner which does not require division of train having separate space-time compartments. The re a developed number to obtain the square root. circulating memory loop follows any one of a predeter And yet another object of the present invention is to mined number of paths, the particular path being chosen provide an electronic calculator for extracting the square root of the number in a manner which significantly re according to the manner in which it is desired to manipu late the information contained in the data train. A tim 40 duces the number of required steps and, accordingly, ing signal source is synchronized with the memory loop completes the operation in a minimum of time. Still another object of the present invention is to pro to maintain the information within the loop properly vide an electronic calculator which utilizes a novel method arranged even though the information may be trans related to the "sum of odd integers' method for deriving lated a number of times for handling or storage in a memory medium. square roots. A further object of the invention is to provide an im A counter is interconnected with the logic of the memory loop and the timing signal source whereby the proved method of extracting a square root in which the information is handled in a predetermined manner ac steps of commutation are sequentially performed in a cording to the sequential stepping of the counter and ac calculator. cording to circuitry activated by the command to perform Another object of this invention is to provide an elec the desired function. The initial setting of the counter is tronic calculator for extracting the square root of an determined by the function which is to be performed by operand in response to a single command. the calculator. Still another object of the present invention is to pro When a complete number has been entered into the vide an electronic calculator which uses a minimum of data train circulating in the memory loop, circuitry pro 55 electronic circuitry to extract the square root of an op vides for a visual indicating means to be stepped a unit erand at high speed. value so that the cumulative sum of the number of en And yet another object of the present invention is to tries into the data train is available to the operator of a provide an electronic calculator which correctly aligns machine. numbers with respect to a decimal point when they are More specifically, in the illustrated embodiment of the 60 entered into the calculator. invention, an electronic calculator, in response to a com And yet a still further object of the invention is to mand to extract the square root of an operand, includes provide an electronic calculator which correctly aligns means for initating a couplet cycle by removing the two an answer with respect to a decimal point. most significant digits of an operand contained in the first It is another object of the present invention to provide register and placing these digits in the two least sig an electronic calculator which temporarily records the nificant digit positions of a second register. A means is total number of entries into the calculator. then provided for subtracting the contents of an initially It is another object of the present invention to provide cleared third register from the second register in a first an electronic calculator which counts the entry of each The last successful subtraction yielded the number 134, which properly decimal aligned would be 13.4. A closer and second subtraction wherein the first subtrahend number into the calculator during the operation of a varies by the value of one from the second subtrahend 70 problem. and the second subtraction occurs only if the remainder It is yet another object of the present invention to pro from the first subtraction is non-negative. A means is in vide an electronic calculator which is fast in operation, cluded for incrementing the value in the third register, simple and reliable in operation, and inexpensive to which represents the developing square root, by one when construct. the remainder from the second subtraction is not negative. 75 Other objects and advantages of the invention will be 3,526,760 8 lative sum of the entry of complete numbers is indicated during the operation of a problem. Referring now to FIGS. 4 and 5, the organization of information within the recirculating memory loop and the manner in which it is displayed by the display means 18 is illustrated. The memory 4 in the illustrated embodi 7 evident from the following detailed description, when read in conjunction with the accompanying drawings which illustrate the invention. In the drawings: FIG. 1 is a pictorial representation of an electronic calculator embodying the invention. FIG. 2 is a plan view of the keyboard of the calculator. FIG. 3 is a simplified block diagram of one embodiment of the present invention. FIG. 4 illustrates a full field display of information retained in the memory of the invention. FIG. 5 illustrates the manner in which information con tained in a data train is organized in one type of memory which may be utilized with the present invention. FIG. 6 is a block diagram of a timing means used in ment of the invention comprises a magnetostrictive acoustic delay line 26 through which information travels O in the form of acoustic pulses at the speed of sound. The delay afforded by the delay line 26 is approximately 5 milliseconds. The information circulating through the memory loop is placed on the delay line 26 in the form of acoustic pulses in a pulse count notation. In a pulse count nota 5 tion, the number of acoustic pulses in a predetermined Space-time compartment represents a digit. For example, this invention. four acoustic pulses appearing in a single space-time com FIG. 7 further illustrates the organization of informa partment represents the digit four and seven acoustic tion within the data train and its relation to a display on pulses appearing in another space-time compartment a cathode ray tube. FIG. 8 is a more detailed block diagram of the embodi 20 would represent the digit seven. A data train passing through the delay line 26 represents a plurality of serially ment of the invention illustrated in FIG. 1. arranged space-time compartments in which acoustic FIG. 9 is a logic diagram of a counter means used in pulses representing data may appear. The number of the mode control of the system shown in FIG. 1. Space-time compartments which comprise a data train is FIG. 9A illustrates the different configurations assumed 25 shown in FIG. 4, which also illustrates a field display of by the counter means. information as it would appear on the face of a cathode FIGS. 10 and 11 are logic diagrams of a means used in ray tube (not shown) which is used as a visual display decimal alignment. in the display means 18. FIG. 12 is a flow chart illustrating the sequential steps The information circulating within the memory loop of the electronic calculator during performance of the 30 is considered to be arranged in six horizontal registers square root function. and fifteen vertical columns. As seen in FIG. 4, only four FIG. 13 is a flip-flop used in the practice of this registers, R1 through R4, and thirteen columns, C2 invention. through C14, are displayed. The register R0 is used in FIG. 14 is the symbol used for an OR-gate. ternally within the machine for arithmetic purposes and FIG. 15 is the symbol used for an AND-gate. FIG. 16 are the symbols used for an OR-gate con 35 the register RS is used for the retrievable storage of a number. nected to an inverter. A column C0 is not used for data but a corresponding FIG. 17 is the symbol used for an AND-gate. space-time compartment at the leading edge of the data FIG. 18 is a diagram of the logic used in temporarily recording the cumulative sum of the entry of numbers 40 train is reserved for a start or synchronizing pulse as will be shown hereinafter. The column C1 does not con into the calculator. tain significant digits, but is used to display a negative FIG. 18A is a circuit diagram of the diagram of FIG. sign of a number contained in columns C2 through C4 8. of each register. The thirteen significant digits of a num FIGS. 19 to 27 are diagrams illustrating the logic for ber in each register are displayed in columns C2 through the square root function of the calculator illustrated in C4. FIG. 1. Referring now to FIG. 7, the arrangement of the in FIG. 28 shows how FIGS. 20 to 27 are to be arranged. formation of the display in FIG. 4 into a data train that FIG. 29 is a diagram showing idealized wave forms. is circulated through the memory loop is clearly illus FIG. 30 is a diagram showing idealized wave forms. trated. The data train which is equal to one word time FIG. 30A is a wave form appearing in FIG. 30 on an has the columns C1 through C15 serially arranged therein. expanded time scale. The data train is preceded by a start or synchronization Referring to the drawings in detail, and particularly pulse which appears in a space-time compartment C0. FIG. 3, reference character 10 designates one embodiment Within a space-time compartment representing a column, of an electronic calculator constructed in accordance with Such as the illustrated column time C9, are six space this invention. A pictorial representation of the calculator time compartments which represent the six registers of 10 appears in FIG. 1. The calculator 10 includes an the data train. Within each one of the register times, arithmetic unit 12 which is connected with a dynamic Such as the illustrated register time R2, are sixteen bit memory 14 to form a recirculating memory loop. A tim time positions B0 through B15. The illustrated embodi ing means 16 is interconnected with the arithmetic unit ment of the invention uses only nine of these bit times to 12 to synchronize the flow of information through the recirculating memory loop and to also synchronize the 60 represent digits zero through nine. As previously dis closed, a digit is represented by an equivalent number of selective display of information contained in the loop by pulses in a pulse count notation. a display means 18 which is also interconnected with the The start pulse appearing in column time C0 is the arithmetic unit 12. A keyboard 20 is connected to the first pulse of the data train and is a synchronization pulse arithmetic unit 12 for entering information into the re for initiating operation of the timing means 16. The tim circulating memory loop. A pictorial representation of the keyboard 20 is shown in FIG. 2. The keyboard 20 is also connected to a function control 22 in order to initiate commands to the function control 22 for directing the se quential operation of the arithmetic unit 12 in the carry ing out of these commands. The timing means 16 is also connected to the function control 22 in order to synchro nize the recirculating memory loop with the manipula tion of information by the arithmetic unit 12 in response to commands from the function control 22. The keyboard 20 is connected to an entry counter 24 whereby the cumu ing means 16 is shown in more detail in the logic diagram of FIG. 6. In the illustrated embodiment of the invention, logical "one' or true is 0 volt and logical “Zero' or false is -6 volts. An oscillator 28, operating in the present embodiment at a frequency of 666 kilocycles, is con nected to one input of an AND gate 30. A flip-flop 32, entitled the Home flip-flop, has its reset or Home output connected to another input of the AND gate 30. The re Set input of the Home flip-flop 32 is connected to receive the data train circulating through the memory loop. The 3,526,760 9 only puse of significance on the data train to the Home O counter which receives information serially or in parallel and which shifts information in parallel. The counter 56, termed the B counter, receives information in parallel from the A counter 54 or the D counter 60 and also transmits the information in parallel. The counter 58, also termed the C counter in the present embodiment of the invention is a down-counter and receives informa tion in parallel from the A counter 54 or the B counter 56. The counter 58 transmits the information contained O therein serially. flip-flop 32, however, is the leading or start pulse con tained in C0 column time. The receipt of the start pulse on the Home input resets the Home flip-flop 32 so that the Home output is true and enables the gate 30 to pass the output of the oscillator 28 to the toggling input 36 of clock flip-flop 38. The output of the clock flip-flop. 38 provides the clock time for the calculator 10. In the illus trated calculator, this clock time has a frequency of 333 kilocycles. The output of the clock flip-flop 38 is connected to the The counter 60, also termed the D counter in the input 40 of a bit time counter 42. The bit time counter present embodiment of the invention is a down-counter. 42 may comprise four flip-flops (not shown) connected The D counter can receive information serially or in in series so that each flip-flop essentially divides the out parallel and transmits information in parallel to the A put of the previous flip-flop by two. This counter has a 5 counter 54 or the B counter 56. capacity of sixteen individual configurations, each con The memory loop during normal recirculation com figuration representing a bit time in the data train. The prises the delay line 26, the A counter 54, the B counter counter 42 has an output once each sixteen counts or six 56 and the C counter 58. More specifically, the delay line teen bits and represents one register time. The output of 26 is connected to a suitable read amplifier 62 which con the bit time counter 42 is connected to the input 44 of R 20 verts acoustic pulses carried by the delay line 26 into time counter 46. The R time counter or register counter electric impulses. The read amplifier 62 is connected 46 may comprise three flip-flops (not shown) which, if through a suitable AND gate 64 to the A counter 54. ordinarily serially connected, would have a capacity of The AND gate 64 is enabled by a pulse on input 66, eight counts. The flip-flops of the R time counter, how termed the advance A pulse, which enables the gate 64 ever, are interconnected in a manner well known in the 25 and permits the pulses to step the A counter 54 to a art to provide an output pulse after six individual counts. digit value. The counter 54 is also provided with inputs The R time counter 46 is advanced one count each time to reset it to a zero configuration and to set it to a an input is received from the bit time counter 42. After predetermined configuration for arithmetic operations. six counts, the counter is recycled to its initial condition The A counter 54 is connected through an AND gate 68 and begins counting again. Every six counts of the R time 30 to the B counter 56. The AND gate 68 is enabled by a counter 46 provides an output pulse, which represents one Shift A to B pulse to permit the parallel transfer of column time, on lead 48 connected to the column time information from the A counter 54 to the B counter 56. counter 50. The parallel transfer of information between the counters The column or C time counter 50 may comprise four is covered in much greater detail in U.S. patent applica Serially connected flip-flops (not shown) with each input 35 tion, Ser. No. 319,704, filed in behalf of Robert A. Ragen pulse received from the R time counter 46 stepping the and assigned to the same assignee as the instant applica counter one count until it has assumed each of sixteen individual configurations. After the C time counter 50 tion. The B counter 56 is connected to the C counter 58 through an AND gate 70 whereby information is parallel shifted from the B counter 56 to the C counter has reached its sixteenth configuration, the pulse on its output 52 is transmitted to a display counter 54 and to 40 58. The AND gate 70 is enabled by a Shift B to C pulse. The C counter 58 is connected to an AND gate 72. The the Set input of the Home flip-flop 32. It is apparent that AND gate 72 is connected to a suitable write amplifier the pulse appearing on lead 52 indicates that a data train 74 for translating electrical pulses into acoustic pulses comprising a start pulse and fifteen columns has passed through the arithmetic unit and back onto the delay line which are transmitted through the delay line 26. The AND gate 72 also has an input 76 which receives clock 26 and, accordingly, the timing chain may be shut down. pulses. If the C counter is not equal to zero AND gate This is accomplished by the pulse appearing on the set input of Home flip-flop 32. It is further apparent that the 72 will have an output every clock pulse. This output is the Advance C signal. The Advance C pulses are also an toggling of the Home flip-flop 32 will disenable the AND input of the C counter to step the C counter down to a gate 30 and preclude the timing chain from being ad vanced by the output of oscillator 28. Thus, it is seen 50 Zero configuration. When the C counter 58 reaches a zero configuration, the voltage level on the input to the AND that the start pulse at the leading portion of a data train gate 72 becomes false, thereby disenabling the AND gate starts operation of a timing means which provides timing 72 and results in the number of acoustic pulses being signals for dividing the pulses contained in the data train placed on the delay line 26 being equal to the digit which into individual space-time compartments in accordance was contained in the C counter 58. with various configurations of the counters within the timing chain and that operation of the timing means is Variations may be made in the memory loop in order terminated when the column counter 50 indicates that to manipulate the data by a predetermined transfer of it has reached its terminal configuration. All functions data between the space-time compartments. An example in the calculator 10 are referenced to these various coun of this is provided by a memory loop which bypasses the ters and depend upon them for synchronization thereof. 60 B counter 56. In this instance, information is parallel Wave forms which illustrate the pertinent timing signals shifted from the A counter 54 through an AND gate 78 used in the calculator 10 are shown in FIGS. 29 and 30. to the C counter 58. The AND gate 78 is enabled by a During the time period when the data train is contained Shift A to C pulse. entirely within the delay line 26 and the timing chain is Another variation in the memory loop may be pro not being incremented, the display on the face of the 65 vided by the inclusion of the D counter 60. The read cathode ray tube is not affected because of the persistence amplifier 62 is also connected to the D counter 60 through effect of the phosphorescent coating on the face. an AND gate 80. The AND gate 80 is enabled by an A more detailed diagram which more clearly illustrates Advance D pulse so that pulses received from the read the recirculating memory loop of arithmetic unit 12 and amplifier 62 are permitted to count down the D counter the memory unit 14 is shown in FIG. 8. This figure also 70 to a configuration which represents the complement of clearly illustrates the way in which the loop may be the digit. The information then contained in the D counter changed to manipulate data circulating within the loop. 60 may be parallel shifted to the A counter 54. The The arithmetic unit 12 comprises four counters 54, 56, D counter 60 is connected to the A counter 54 through 58 and 60. The counter 54 is also termed the A counter. an AND gate 82 which is enabled by a Shift D to A In the present embodiment of the invention it is an up 75 pulse. The D counter 60 is also connected to the B counter 3,526,760 2 shifted back in time in the data train and replacing the number in the R2 register. If the digit in each column of the A1 register is delayed one digit time, then the entire contents of the R register is placed in the R2 Another variation in the memory loop may be pro register position on the data train and on the display. vided by the inclusion of the D counter 60 in a different The variation of the memory loop is termed a shift up manner. Information is counted into the A counter 54, since this is the way it would appear in a display. It is then parallel shifted through AND gate 86 to the D to be understood that a shift up operation shifts each counter 60. The normal A counter 54 parallel shift to register up into the immediately adjacent register position. B counter 56 through AND gate 68 is disenabled in this This results in the R4 register being entirely displaced O instance. The D counter 60 then parallel shifts to the B and the number Zero then appearing in the R0 register. Collinter 56 through AND gate 84. The B counter 56 parallel shifts to the C counter