Historical Document · 1970
US Patent 3,518,629: Recirculating Memory Timing (S. P. Frankel, Computron / SCM Cogito)
Frankel's recirculating-memory timing, from the design line that became the SCM Cogito 240.
Historical Document · 1970
Frankel's recirculating-memory timing, from the design line that became the SCM Cogito 240.
June 30, 1970 S. P. FRANKE 3,518,629 RECIRCULATING MEMORY TIMING Filed Feb. 5, 1964 36 Sheets-Sheet f30 372 re A12AM 12 Yea. X M72A7. 160 2 Ž2% 2.2% June 30, 1970 3,518,629 S. P. FRANKEL RECIRCULATING MEMORY TIMING 36 Sheets-Sheet 3 Filed Feb. 6, 1964 (rºz y ¿Pezor ||||| A + ] 4% aAzrae/ 24. AZAL a3 17%-74/r S. P. FRANKEL June 30, 1970 3,518,629 RECIRCULATING MEMORY TEM.ING 33 Sleets-Shet S Fig 3 Feb 6, 1964 Af ECC 4. M MY 4. Z M/ 4. p/ MY 4 W / M A A/ Z M/ A? p/ MY 2 1. A p/ M/ 22 27 2% zaa aa a2 s H. H.HE H. a 0 s X, Y 2. az X, Y a a2 - X Y a A3 - x Y a : a4 = x Y a a4 = y Y a 2a a y Y a M/b/af///2a A7 is x y a 4%/4/7%/ 2 24.172-74%r 2.x June 30, 1970 S. P. FRANKE RECIRCULATING MEMORY TIMING 3,518,629 56 Sheets-Sheet Fied Feb. 2, 1964 227 42% aarzée/ 12%//7ear June 30, 1970 S. P. FRANKE 3,518,629 RECIRCULATING MEMORY TIMING 56 Sheets-Sheet S Filed Feb. 6, 1964 + 2 6%, ׺ y June 30, 1970 S. P. FRANKE RECIRCULATING MEMORY TIMING 3,518,629 June 30, 1970 S. P. FRANKEL RECIRCULATING MEMORY TIMING 3,518,629 June 30, 1970 S. P. FRANKE 3,518,629 RECIRCULATING MEMORY TIMING Filed Feb. 6, 1964 56 Sheets-Sheet lS 47/aa-zea/A4e 4 % ear ga -2. (20-?e /ra/// er AVA/a. My Yea 4%.7% 4/azae/ June 30, 1970 S. P. FRANKEL 3,518,629 RECIRCULATING MEMORY T TMTNG Filed Feb. (E, 1964 33 Shcot S-Shtet 8 / a June 30, 1970 3,518,629 S. P. FRANKE RECIRCULATING MEMORY TIMING Fir Frb. , N Y& () N S. 47.7/e/4 a/746, /3 4-2, 6-7%. /2-x ...Y w June 30, 1970 Filed Feb. C, 1964 S. P. FRANKEL RECIRCULATING MEMORY TIMING 3,518,629 36 Sheets-Sheet li --- | (%) | | /// Ø #49 (5 (2/*3) (7,2) (2)' (27 AvA2A/72a. 5%.7% a zée, 3. 1-22-, 2-> A. 4-2772 June 30, 1970 S. P. FRANKE 3,518,629 RECIRCULATING MEMORY TIMING Filed Feb 6, 1964 53 Sheets-Sheet '24. 27 --- al --My rafts: --- As. af aya (%a 42- 46. . -- A - Ao 14%aata - aa 24- a co-77 ( ae) a A - 23 by 76 afé fa (3/2Zé263%) aaoo 24/7-year wye ae/3 - 14 (2 e a faaaaz2// 'a( 14244346 47A/A6/22)as 23426/2: 24.66.42ee 2/25.42 a.2) Aaaya/ r1/s/ / ae) 7 a.44/// 3 M = 2a4 Wa Aaaaaa 73 A4 A (24) June 30, 1970 S. P. FRANKE 3,518,629 RECIRCULATING MEMORY TIMING Filed Feb 6, 1964 36 Sheets-Sheet : O rry - (a rae) as 4 Waaa. 467 A/ae/3-a2a aaaaaza (1) J W - a releaa/24-17 Auza Co?azé/aaaaaaas - a 6/22 r a 27 - a / /Z27 / 23) & Aaazraa 4 (634-64Aea/327 afe v--(42) Aaayaaaayaa-zaarazaara (672-azéaasaaaaaa sy-4-42aaz2-aa. Aaaayaa-Zaaaaaaaa-2/42. A? 4% a 46/aaazz MVA2A/2a 472/7/2/a/aayae/ 2. 3-6%/2-x 17%/areer June 30, 1970 Filed Feb 6, 1964 S. P. FRANKEL RECIRCULATING MEMORY TIMING 3,518,629 56 Sheets-Sheet 27% a 7-ayaa/ 1/721/72 June 30, 1970 FiCd Feb, f, 1964 3,518,629 S. P. FRANKEL RECIRCULATING MEMORY TIMING 36 Sheets-Shect ? Z June 30, 1970 S. P. FRANKE RECIRCULATING MEMORY TIMING 3,518,629 June 30, 1970 Filed Feb. 6, 1964 S. P. FRANKEL ECIRCULATING MEMORY TIMING 3,518,629 36 Sheets-Sheet S A/12//724. weaezée/ June 30, 1970 Filed Feb. C, 1964 3,518,629 S. P. FRANKEL RECIRCULATING MEMORY TIMIN(i 5S Sheets-Sheet MMA2//72a. 2 -4,á 6-4 v/2.2% - a. June 30, 1970 S. P. FRANKE 3,518,629 RECIRCULATING MEMORY TIMING Filed Feb. 6, 1964 '%r 407 36 Sheets-Sheet (2/72 a?aaver) -4. 26/27/23)tyavaz7%azé 67 FM-772 a 6. Awaay72a 3% aayae/ f 241-67%-76er récy, June 30, 1970 S. P. FRANKEL 3,518,629 RECIRCULATING MEMORY TIMING Filed Feb. 6, 1964 3S Sheets-Sheet O June 30, 1970 Filed Feb. 6, 964 S. P. FRANKE RECIRCULATING MEMORY TIMING 3,518,629 36 Sheets-Sheet S r 8. awaa/72a 4% a 7-zée/ 24, 4-6 June 30, 1970 S. P. FRANKEL 3,518,629 RECIRCULATING MEMORY TIMING Filed Feb. 6, 1964 36 Sheets-Sheet SS A3. 2 76% Cézae/ A 100 (2Y 122 (1A (17Y Af-awa 22 2 f (2Y 4. a2 SA ea af a (2\ (2Y 6. A2 a. a Asa ?ay 47 A2744a es A22 - V - Moo 122 a.2 (2Y (YY f Vraoz A.Sarasa 6aye afa (22-yaz A2a2) a V a.asea leazaa/29/ae/204/azaavaaz 2 A2 - 422 2% Aes 2 - 24.624A69 a.4 6-43 - 2, 20.2564 23 Az62-72(767-7672).2/zaaaa-za 76Z24 Zé728 42/46 M/A/2M/724 4% a-22%e/ 2 2. fé-6/%--> 17%/year June 30, 1970 S. P. FRANKE RECIRCULATING MEMORY TIMING 3,518,629 June 30, 1970 S. P. FRANKEL 3,518,629 RECIRCULATING MEMORY TIMING Filed Feb. 6, 1964 56 Sheets-Sheet S 8 2-0 (2) DDO O. DOOOOOOO (2) oD DO DEC D (e) o O OO O. D D @ DODO O. e OOD O DE zoo do | 234.5 bilBO 2 A 5-6-27 (2724 (fere-z/2/ 7%. 22 /772-A/ea) A2/re ea?ava a? (% we 20% w/ 2. 4.2%42/72Af f/2.2% United States Patent Office 3,518,629 Patented June 30, 1970 2 3,518,629 RECIRCULATING MEMORY TIMING Stanley P. Frankel, Los Angeles, Calif., assignor to Com putron Corporation, Oakland, Calif., a corporation of California Filed Feb. 6, 1964, Ser. No. 342,881 nt. Cl. G11c 2 1/00, 21/02 U.S. C. 340-172.5 12 Claims ABSTRACT OF THE DISCLOSURE A delay line memory is disclosed in which temperature compensation is made unnecessary by provision of an inter-controlled counter-multivibrator combination for operating the delay line. The multivibrator is meta of the digits which are inserted into the registers appear on the cathode ray display. Digits are inserted into any of the three registers of the desk calculator by using a single ten-digit keyboard. The particular register to which the digits and other information are entered is chosen by the use of one of a plurality of register selection keys. These keys allow the entry of information to any one of the registers and also allow, in one instance, the entry of information to O two registers at the same time. In addition to the above, there is an automatic control which provides entry to a particular one of the plurality of registers at all times. The keyboard of the desk calculator also includes keys which provide positive or negative signs. The sign infor 5 mation can be entered into a register at any time during the digits and can be changed at will. The stable-that is, conditionally monostable, its astability the entry of of the desk calculator also includes a decimal being dependent upon detection of the first pulse to keyboard point key. The decimal point in each register normally emerge from the delay line. to the left of the most significant digit position. The first pulse, though a marker pulse, is indistinguish 20 appears If non-zero digits are initially entered into a register, able from the data pulses except that at the time of its the decimal point moves to the right until the decimal arrival the counter is at a given count and the multi key is operated. At this time the decimal point is vibrator is in its stable state. To guard against blocked point If zeros are initially entered into a register, the operation caused by multivibrator entry into the stable fixed. point moves to the left until a non-zero digit State before any data pulses are recorded in the memory, 25 isdecimal entered. an RC circuit is used to reestablish the astable or “free The desk calculator can perform various arithmetic running' condition, spontaneously, if this does not occur computations which are controlled by individual keys on within respective time limits. the keyboard. The term "arithmetic' is used in this appli cation to include all the various computations which can BACKGROUND AND SUMMARY OF THE subtract, multiply, divide, accumulative multiply, and INVENTION accumulative divide. The desk calculator will perform all of the above computations using positive and/or This application relates to an electronic desk calcu negative numbers together with associated decimal lator. More specifically, the application relates to an points. electronic binary-coded decimal digital desk calculator. Each of the working registers described above has The desk calculators now or previously on the market associated with it a surrogate register to operate as a are of a mechanical construction and are designed to memory. The which is entered into the desk perform a variety of functions, including those of addi calculator and information is operated upon in the desk calcu tion, subtraction, multiplication and division. These 40 lator is part ofwhich of the working registers, but mechanical desk calculators usually operate on a digital it is also possiblethetocontent store, recall and exchange informa basis. Mechanical desk calculators have major disad between each working register and its complemen vantages in that they are comparatively slow in their tion tary surrogate register. These functions are controlled operation and relatively inflexible in their application. by store, recall and exchange keys on the keyboard of For example, some of the prior art desk calculators have desk calculator. It is also possible to transfer infor huge multi-keyed keyboards for inserting the numbers 45 the mation from one working register to another working which are used as part of the arithmetic computations. register by the use of transfer keys which are located Further, most of the prior art mechanical desk calcu on the keyboard of the desk calculator. lators only have a single entry register which limits the flexibility of the arithmetic operations which may be per 50 The information which is inserted into the desk calcu lator continuously circulates in the form of a train of formed with the calculator. One object of the desk cal pulses. Each pulse position may be occupied by a pulse or, culator of the present invention is, therefore, to pro alternatively, may be unoccupied, and represents a single vide an electronic desk calculator which will have signifi cantly faster operation and greater flexibility than desk bit of information. Four such bits make up a character. 5 5 Each four bits may represent either a decimal or a non calculators of the prior art. decimal character. The pulses pass through a delay line Another object of the desk calculator of the present which operates as the memory. The length of the delay invention is to use a cathode ray tube for simultaneously line is longer than required by the total number of pulses displaying a plurality of decimal digits in a plurality of used in each cycle. The pulses are paced by a clock gen register positions. The desk calculator has three registers, In order to compensate for any timing errors in Two of the registers hold twelve significant digits and 60 erator. the desk calculator, each cycle of circulation is initiated the third register holds twenty-four significant digits. by a marker pulse having the same characteristics as a bit The two short registers are each displayed in a single line representing the binary value “1'. At the end of each on the face of the cathode ray tube and the long register cycle, the clock generator enters a metastable state until is split into halves with each half displayed in a single appearance of the marker pulse. line on the face of the cathode ray tube. There are, 65 theAnother obect of the desk calculator of the present therefore, four rows of digits displayed representing invention is to interleave the bits of information so as to three registers. To the left of each of the three registers slowly present the successive bits of information as they are four zeros which permanently appear on the face of leave the delay line. It is also desirable to interleave the the cathode ray tube. The four permanent zeros are decimal of the different registers to facilitate the 70 used so that the maximum number of significant digits arithmeticdigits computations performed by the desk calcu can be entered into each register for numbers which are lator. One of the short registers is interleaved with the smaller than 0.1 but equal to or larger than 0.00001. All 30 be performed by the desk calculator. These include add, 3,518,629 3 4. first half of the long register, and the other of the short FIG. 3 is a flow chart of the Transfer and Enter Digit registers is interleaved with the second half of the long routines; register. The bits of information are arranged in groups FIG. 14 is a block diagram of the K, P, and T7-T12 of least significant bits, next most significant bits, and so flip-flops which form part of the timing counter logic; on, to the most significant bits. FIG. 15 is a block diagram of the character time logic The desk calculator uses a floating decimal point Sys 5 for producing the C signals; tem. When all the necessary information has been inserted FIG. 16 is a schematic diagram of the bit time logic into the registers, an arithmetic operation key is pressed. for producing the t and quadrant signals; During the arithmetic operation, the position of the deci FIG. 17 is a block diagram of the clock generator and mal point of the result is automatically computed. If, after T0-T6 flip-flops which form another part of the timing the arithmetic operation, the decimal point is off scale, counter logic to produce the n1-n5 and N127 signals it is carried around to the other end of the register. If the associated with timing the information circulating in the Memory; decimal point is off scale to the left, which indicates a small number, a streak appears on the lefthand side of the FIG. 18 is a schematic diagram of circuitry to produce display. If the decimal point is off scale to the right, signals representative of significant periods of time within which indicates a large number, a streak appears on the each machine cycle: righthand side of the display. The streaks can only operate FIG. 19 is a schematic diagram of Memory logic in within a certain range and if the number is either extreme cluding the delay line and flip-flops M, S, and D; ly large or extremely small, both streaks appear. FIG. 20 is a magnetostrictive delay line which may be The desk calculator uses six flip-flops to distinguish 20 used with the Memory logic of FIG. 19; various conditions of operation. These six flip-flops are FIG. 21 is an expanded view of the coupling unit used interrelated to give sixty-four possible states which are with the delay line of FIG. 20; called phases. The desk calculator uses a plurality of FIG. 22 is an amplifier which may be used as the am routines wherein each routine is a linear progression of plifier 250 shown in FIG. 19: states which are occupied in succession by the change of 2 5 FIG. 23 is an amplifier which may be used as the am one of the basic flip-flops for each step in the progression. plifier 252 shown in FEG, 19; The routines also include branches or loops. The basic FIGS. 24 and 25(a) to (e) are block diagrams of cir routines are add-substract and accumulative multiply and cuitry which produce miscellaneous controlling signals in cluding the h-h7 signals; accumulative division which include multiply and division. Within the basic routines are other activities which are 30 FIGS. 26(a) to (n) are block diagrams of circuitry common to the basic routines. These activities include which produce signals representative of the various in delaying or advancing the information in a register so as equalities used in the logic of the desk calculator; to align the digits of two registers. Other activities which FIGS. 27 to 32 are block diagrams of the phase chang are basic to all the routines are sub-additions and sub ing flip-flops U, V, W, X, Y and Z and the associated controlling circuitry; tractions as part of all the arithmetic computation. Another activity which is used in the divide routine is FIG. 33 is a block diagram of the E1-E4 and D1-D4 the augmentation of a register. For example, as the divi flip-flops and the associated control circuitry; sion progresses, the register which displays the quotient is FIGS. 34 and 35(a) to (l) are block diagrams of the augmented each time a successful subtraction is made. circuitry used to produce the d" signal; Also, during some of the basic routines it is sometimes FIG. 36 is a block diagram of the E5 and E6 flip-flops necessary to complement a number. with their associated control circuitry; After any of the arithmetic operations, it may be neces FIG. 37 is a block diagram of the circuitry used to produce the e' signal; sary to restore to a normal form the number which ap pears as the answer. This may means delaying or advanc FIG. 38 is a block diagram of the F flip-flop and its ing the number to the proper position, recomplementing associated control circuitry; if the number appears in the complemented form and other FIG. 39 is a block diagram of the I flip-flop and its normalizing activities. A clearer understanding of the desk associated control circuitry; calculator will be had with reference to the following FG. 40 is a block diagram of the circuitry used to figures wherein: produce the Inc. signal; 50 FIG. 41 is a block diagram of the circuitry used to BRIEF DESCRIPTION OF THE DRAWING produce the memory input signal M'; FIG. 42 is a block diagram of the G flip-flop and its FIG. 1 is a view of the outward configuration of the associated control circuitry: desk calculator showing the keyboard, display and display FIG. 43 is a block diagram of the C flip-flop and its controls; 5 5 associated control circuitry; FIG. 2 is an expanded view of the keyboard of the desk FIG. 44 is a block diagram of the H flip-flop and its calculator; associated control circuitry; FIG. 3 is a schematic drawing showing the production FIG. 45 is a block diagram of the J flip-flop and its of signals from the decimal digit and decimal point keys of associated control circuitry; FIG. 2; 60 FIG. 46 is a block diagram of the k and q flip-flops FIG. 4 is a schematic drawing showing the production and their associated control circuitry; of signals from the non-decimal keys of FIG. 2; FIG. 47 is a diagram partly in block and partly in FIG. 5 is a block diagram of the circuitry to produce Schematic form of the vertical deflection circuit for the signals designated by the letter a: FIG. 6 is a block diagram of the circuitry to produce 65 cathode ray display unit of the desk calculator; FIG. 48 is a diagram partly in block and partly in signals designated by the letter b; Schematic form of the horizontal deflection circuit for the FIG. 7 is a block diagram showing the interrelation cathode ray display unit of the desk calculator; ship of the a and b signal plus other signals to produce FIG. 49 is a block diagram of the beam suppression the basic phases (qb) of the desk calculator; FIG. 8 is a block diagram of the desk calculator illus 70 System for the cathode ray display unit of the desk cal trating the interrelationship of all the phases; culator; FIG. 9 is a flow chart of the Add-Subtract routine; FIGS. 50(a) to (f) is a series of typical displays show FIG. 10 is a flow chart of the Multiply routine; ing various decimal point indications; FIG. 11 is a flow chart of the Divide routine; FIG. 51 is a schematic diagram of a clock generator FIG, 12 is a flow chart of the Restore-P routine; ) which may be used for the clock generator of FIG. 17; 3,518,629 6 is named by the values of the six flip-flop settings and the specific name is described by two octal digits. The first digit indicates the state of the flip-flops U, V and W. The outputs of these three flip-flops are combined to produce signals a0, a1, a2 . . . a7. FIG. 5 shows the 5 interconnection of the flip-flops to produce the a signals and contains the logic equations describing the intercon nection of the flip-flops. The second digit describes the state of the flip-flops X, Y and Z which produce signals DETAILED DESCRIPTION OF THE INVENTION O b0, b1, b2 . . . bt. FIG. 6 illustrates the production of the b signals. Any individual phase is described by the The outward configuration of the desk calculator is general term bii wherein ij=0, 1 . . . 7; for example, shown in FIG. 1. The desk calculator includes a vertical $64=a6, b4= U V XYZ. All of the a and h signals face 10 and a horizontal face 12. A cathode ray display are made available for direct use, as well as the most fre unit 14 is mounted to display information at the vertical quently used phase signals. FIG. 7 illustrates the produc face 10. The cathode ray unit 14 displays the contents of tion of the common phase signals which are used in the three registers K, Q and P. Registers K and Q are each desk calculator. In addition to the phases which are displayed in a single line whereas the register P display derived solely from the a and b signals, a plurality of is split up into two lines. Controls are mounted on the signals (dap, picq, (bcp, and (bdp) which are used fre vertical face 10 to regulate the operation of the cathode ray unit 14. The controls include a combined on-off 20 quently in the desk calculator are derived using the a and b signals, the phase indicating flip-flops and an Switch and variable brightens control 16, a horizontal con auxiliary flip-flop J. trol 18 and a vertical control 20. The rest state in the desk calculator occurs in b00. The horizontal face 12 includes the keyboard controls Departure from the rest state occurs only on the opera for the desk calculator. The keyboard is more clearly tion of control keys on the keyboard. Each key initiates shown in FIG. 2. The keyboard for the desk calculator an activity which leads, on completion, to a return to uses a ten-key digit keyboard 100 which is used to enter the rest state. The major activities are carried out in numbers into the different registers. A decimal key 102 "routines." Each routine makes use of a series or group places a decimal point in the appropriate position in a register as a number is being set into a register. Also in 30 of phases. The main routines are the Add-subtract routine (indicated by As.), Multiply (M), Divide (D), Transfer cluded on the keyboard are register selection keys 104, (T), and Enter Digit (Ed.). Also, the first three routines 106, 108 and 110 for selecting the entry into registers (As, M, D) lead into a corrective routine called Restore P, Q, KQ (that is, into both K and Q) and K, respective P (Rip). ly. A switch 112 provides an automatic selection of the Each routine is not always a linear progression of states K register after each arithmetic operation. occupied in succession, but the routine may involve A clear key 114 is included on the keyboard for clear branches or loops. The progression through one of these ing all the registers. Keys 116 and 118 are used to in series of states, whether linear, branched, or cyclic, is dicate the negative or positive character of numbers as accomplished by a succession of phase changes. Each they are entered into appropriate registers. Four keys 120, phase change reverses the state of only one of the six 5 FIG. 52 is a schematic diagram of a basic flip-flop hav ing set (s) and reset (r) inputs; FIG. 53 is a schematic diagram of a flip-flop incorporat ing the basic flip-flop of FIG. 52 and additionally includ ing a complement (c) input; and FIG. 54 is a schematic diagram of a flip-flop incor porating the basic flip-flop of FIG. 52 and additionally including star (*) inputs. 122, 124 and 126 are used to transfer numbers from one 40 phase-indicating flip-flops, U, V, W, X, Y and Z. Each state is also given a name which identifies the routine in which the state is used and the approximate position of the state is given by a number which is even or odd as the phase is an even or odd number of steps from the rest p00. (In other words, this number is odd if there junction with an auxiliary or "surrogate' memory con 45 isstate, an odd number of one-states among U, V, W, X Y, Z.) tained within the desk calculator. Key 128 recalls informa names are used in FIGS. 8 to 13. tion which has been previously stored in the surrogate These full array of 64 possible phases is shown in FIG. memory. Key 130 stores information in the surrogate 8. The It will be noted that some of the phases shown in FIG. memory, and key 132 exchanges information between a 50 8 are not used as part of the activities of the desk calcu Selected register and the surrogate memory. lator. The phases used in each of the five routines are The right side of the keyboard contains the various shown in FIGS. 9 to 13. Some activities are carried out keys which control the arithmetic operations in the desk in several phases, not necessarily in the same routine. calculator. Key 134 is the add button, key 136 is the sub These phases are given collective names which identify tract button, key 138 is the multiply button and key 140 the activities. As shown in FIG. 7, the major ones have is the divide button. Two additional keys 142 and 144 collective names of: Delay P(bdp), Add to P(qbap), provide a multiplication or division in the desk calculator Complement Q(qbcq) and Complement P(qbcp). The with a concurrent accumulation of the answer from the above activities plus Advance P, Advance Q and Aug multiplication or division with a number stored in the ment Q will be described prior to the description of the desk calculator. five routines. Also, fundamental portions of the com The production of signals by the activation of any of 60 plete desk calculator will be described first to lay the the keys is accomplished by the circuits of FIGS. 3 and groundwork for a description of all the activities. These 4. The circuit of FIG. 3 is used in conjunction with the are the timing the timing logic, the delay line digit keyboard 100 and the decimal point key 102 to input, the D andsystem, E regsters and the number structure. produce signals representative of the value of the num Timing system,--The timing system as shown in FIGS. bers set into the desk calculator and signals representa 14, 15, 16 and 17 includes flip-flops T0, T1 . . . T12 and tive of the activation of the decimal point key. The use flip-flops P and K. The changes in state of the timing of these signals is described at appropriate places through flip-flops including the P and K flip-flops are paced by out the description of the desk calculator. The circuit of FIG. 4 shows the production of signals O a multi-vibrator which produces primary clock pulses designated C. These flip-flops define various parts of a from all the operation-control keys contained on the key period of time called a machine cycle. The duration of board. The use of the signals is described at later times a machine cycle is approximately 30 milliseconds. Fach in the description of the desk calculator. machine cycle is divided into two half-cycles by flip-flop The desk calculator uses the settings of six flip-flops, K, which is “Off" in the first half-cycle (marked K), and U, V, W, X, Y and Z (FIG. 5 and FIG. 6) to give a pos sibility of sixty-four phases of activity. Each phase (qb) 75 "On' in the second half-cycle (marked K). The change register to another. Key 120 transfers a number entered vide transfer functions as illustrated on the face of the keys shown in FEG, 2. Three keys 128, 130 and 132 provide functions in con into the P register to the K register. The other keys pro 3,518,629 7 in the state of flip-flop K is illustrated in FIG. 14. Each half-cycle is divided into 30 character periods. In each character period, one character of the number held in one of the three registers K, Q and P is available for manipulation. Usually a character which becomes avail able in one character period undergoes some modifica tions and is set into a group of four flip-flops collec tively called D. These four flip-flops form a supple mentary D register, the operation of which will be de scribed later. The character held in the D register is then available for further manipulation in the following character period. Typically, the manipulation of the - 8 associated with the less significant half of the P register which appear in the K half of the machine cycle. The machine cycle consists of 60 character periods. Each character period occupies one memory cycle, including its dead period. t The first character period of the first half-cycle of the machine cycle is marked KIC0 where C0 represents one of the states of the four flip-flops, T9, T10, T11 and T12 as shown in FIG. 15. The second character period of () the first half-cycle is marked KPCO. The third and fourth character ends at this time and the character is returned to an inactive status in the memory until the next machine cycle. Occasionally a character is held for one or more additional character periods in the D register. Another group of four flip-flops called the E register is used for storing a character so it may be used for a number of character periods. A character consists of four bits which are manip ulated serially; first the least significant bit, then the Sec ond and third bits, and last the most significant bit. A are marked KIC 1 and KPC1, etc. Similarly, the succes Sive character periods of the second half of the machine cycle are marked KPC0, KPC0, etc. Flip-flop P changes state after each character period and there is a change in the state of one or more of the flip-flops T9 to T12 at the time P changes from "On' to “Off." The control of the flip-flops T9 to T12 by the flip-flop P is shown in FIG. 14. Two successive character periods, the first marked I, the second marked P, are called a character period pair and have a common "C-number" indicating 1 he states of flip-flops T9 to T12. The fifteen C-numbers, C0, C1 . . . C14, are distin guished by the tinning flip-flops T9, T10, T11 and T12 character may be a decimal digit, in which case the nu merical value of the character is no greater than 9. A chai and are marked as follows: be explained. Since the period of recirculation is one bers and groups of C-numbers which are needed to limit the times of occurrence of particular activities in the acter may also be a sign character or part of a decimal Tg) Tl? T11 12 position indication. The numerical value of a sign charac ter is always greater than 9. Therefore, its possible values () () ( () O } are 10, 1, 2, 13, 14 and 15. A decimal position indication () () has any value from () to 63, since 6 bits from two adja 30 (' () ) (} { {} cent characters provide the decimal position indication. c () () Each character period is divided into four bit periods. ( () I () 1 (} Each bit period, with one exception to be described later, { () } 1. is divided into 120 clock periods. The production of sig l } () O () mals representative of the bit periods is shown in FIG. l O 1. 16. The memory of the desk calculator consists of a de C O 1. lay line through which some 480 bits of information are C () 1 recirculated. The period of recirculation is one character period and, therefore, a bit held in memory is available once in each character period. Usually a bit is not modi 40 The first twelve C-numbers are collectively denoted C0 11. The last three C-numbers are marked C12-14, and fied or made use of except during the one bit period in the last two are marked C13-14. Other groups of C-num each machine cycle when the bit is in an active status, bers are denoted C1-11 and C1-12. The specific C-num i.e., stored in one of a group of buffer flip-flops, as will character period, this period of time is also referred to as a memory cycle. desk calculator are derived in the circuit of FIG. 15. Each bit period is divided into four quadrants. The Each C-number is held through two character periods last three of the four quadrants are of equal length but which are distinguished by the flip-flop P, as described the first quadrant is sometimes longer since it may in previously. P is Off for the first character period of the clude a dead period of time, defined subsequently. In each pair, On for the second. Each Character period is divided bit period a single bit of the working memory is held in 50 into four bit periods (t1, t2, t3, and ta) which are dis a flip-flop called M and is made available for manipula tinguished by flip-flops T7 and T8 as shown in FIG. 16. tion. The working memory consists of 240 bits which are The flip-flops T7 and T8 cycle in the Gray code pattern. the contents of registers K, Q and P. In addition to the Each of the four bit periods is divided into four quad rants working memory the delay line holds in circulation an other 240 bits called the surrogate memory. The 240 5 5 bits of the surrogate memory form three surrogate reg 1 1 , , 1 ( l, i2, 8 and 14) isters corresponding to K, Q and P. In each bit period one bit of the surrogate memory is held in a flip-flop The quadrants are distinguished by the states of the flip called S. In some of the Transfer operations the bits held T5 and T6 in the binary code as shown in FIG. 16. in flip-flop S are changed by copying into flip-flop S the 60 flops With the exception of the first quadrant of the first bit bits held in M. Otherwise, the contents of the surrogate period of a character period memoiry recirculate unchanged. The recirculation pattern for surrogate bits, which will be described in detail later, includes the occupancy of flip-flop S for one bit period of each machine cycle. Tinning chain logic.- The memory of the desk calcu each quadrant is divided into 30 clock periods by flip-flops lator holds the contents of the three registers and their cor T0, T1, T2, T3 and T4. These flip-flops form a normal responding surrogates as described before. Registers K binary counter except that the two conditions T1T2T3T4 and Q each hold fifteen characters. These fifteen char (with T0=0 and T0=1) are not used at most times. acters consist of twelve decimal digits, the sign charac These two conditions called N0 and N1 are, however, ter, and the decimal position indication held in two char used at the beginning of the first quadrant of each charac acters. Similarly, register P holds 30 characters of which ter period and mark a dead period. During the dead period 24 are decimal digits, one is the sign and two are the the normal recirculation of information in the delay line decimal position. The remaining three characters of the is suspended. The dead time forms a part of the first quad register are meaningless sign and decimal indications rant only in the t1 bit period. That is, the dead time lies ( 11) 3,518,629 9 between the ta bit period in one machine cycle and the live part of the first quadrant of t1 in the next character period. The first and second quadrants of a bit period are designated by the subscript -, the third and fourth quad rants by . Thus tA- means 10 a marker pulse at an appropriate time in the next dead period. However, in the initial condition following the first application of power to the machine, the timing flip flops might fall into the state N1 before any one-bits had been recorded. If the metastable state of the clock multi vibrator were fully stable, there would be no escape from The clock multivibrator provides a primary clock pulse, called C. The primary clock pulse drives the cycling of and O flip-flops T0, T1 . . . T6, as described by the equations 2 - 1. R -associated with FIG. 17. t2. (3+4)2 The resetting of flip-flop T6 marks the end of a bit period and provides a signal to drive the flip-flops T7, T8 The dead period is a part of t or more specifically of as shown by the equations associated with FIG. 14. The resetting of T8 marks the end of a memory cycle and 11 serves to change the state of flip-flop P as described in FIG. 14. The resetting of P provides a clock signal, C. Entry to the condition NO is permitted by the signal which drives the flip-flops T9, T10, T11, T12 and K. These called "Enable *T1" illustrated in FIG. 17. In the absence changes are described by the equations shown in FIG. 14. of the signal Enable *T1, the condition N0 fails to occur, 20 The resetting of K marks the end of a full machine cycle. as does also the condition N1. This condition N1, the The K and P flip-flops together with the C-numbers second of the two clock periods of the dead period, is of provide a plurality of signals which indicate periods of an indefinitely long duration by reason of the suppression time which are of frequent occurrence in the circum of the signal "Enable C' which permits the free running stances for setting and resetting flip-flops and other ex of multivibrator C. Each of the remaining clock periods 25 pressions in the logic of the desk calculator. These signals is of approximately one microsecond duration. The two are developed in FIG. 18. extraordinary clock periods are named N0 and N1, as Delay line input.-Information in the desk calculator is mentioned above, and the thirty ordinary clock periods circulated through a delay line 200 shown in FIG. 19 following the first two are named N2 to N31. The next which has a nominal time delay greater than 480 micro three quadrants 30 seconds. An additional period of time is provided to allow 1 ... 1 for tolerances in both the delay line length and the fre ( 2t1, .3t1 and 141) quency of the clock multivibrator and for a few addi tional microseconds which are spent in the blocked state, each have thirty clock periods named N34 to N63, N66 N1. It is desirable that aside from the dead period, the alternation of states of the multivibrator shall be almost to N95 and N98 to N127. (The names N32, N33, N64, N65, N96 and N97 are not used since the conditions which completely free of influence by signals received from the these names describe do not occur.) The bit period t1, delay line. A small influence on the period of the multi therefore, has 122 clock periods, the second being ex vibrator by the circulating bits is tolerable though traordinarily long. Each of the following three bit periods undesirable. (t2, t3 and ta) has only 120 clock periods named N2 to The delay line 200 may be an electro-mechanical type N127 (again omitting the names N32, N33. . . . N97). as shown in detail in FIGS. 20 and 21. The delay line The names of the clock periods are indicated by the states 200 includes a long length of wire 202 which mechani of the flip-flops T0 to T6, where T0 is the least significant cally provides the delay needed in the operation of the bit and has a position value of unity. T1 has a position desk calculator. The wire 202 is excited in the torsional , , i. (1 + 2)-4 value of 2, and so on to T6 which has a value of 64. that condition. mode by the input signal to the delay line which passes Certain combinations of the states of flip-flops T0 to T6 through an input coupling mechanism 204. The output are used to form signals marked n1, m2, m3, n.4, n5 and signal from the delay line is received by an output cou N127 as shown in FIG. 17, and these signals are used pling mechanism 206. Both the input and output coupling to derive the few individual clock periods which need to mechanisms have the same structure and are shown in be distinguished. more detail in FIG. 21. As was indicated previously, the duration of the normal A pair of coils 208 and 210 are disposed adjacent to clock periods are equal to each other and have a nominal each other. The coils 208 and 210 include hollow cylin value of one microsecond. The repetition rate of the free drical coil forms 212 and 214. Windings 216 and 218 are running multivibrator which supplies the clock pulses around the coil forms 212 and 214 in opposite need only be approximately one megacycle, since devia 5 5 wound directions. The first ends of each winding are electrically tions from that value are compensated for during the N1 connected and the second ends are used as input or out period. In N1, the behavior of the free-running clock mul put terminals. A magnet 220 is provided in proximity to tivibrator is modified so that it can remain in one of its the two coils to operate as a magnetically biasing element. two states for a long period of time. Normally, the stable A plurality of tapes 222 pass through the coil forms condition of the clock multivibrator persists until a marker 60 212 and 214 and form a half turn around t