Historical Document · 1969
US Patent 3,454,785: Shift Register Employing Insulated Gate Field Effect Transistors (Norman, GME)
General Micro-electronics' dynamic MOS shift register, the memory of the Victor 3900.
Historical Document · 1969
General Micro-electronics' dynamic MOS shift register, the memory of the Victor 3900.
July 8, 1969 R. H. NORMAN ET AL. 3,454,785 SHIFT REGISTER EMPLOYING INSULATED GATE FIELD EFFECT TRANSISTORS Filed July 27, 1964 Sheet / -----ANN/NWIN 77N of 2 77 N. ANN N nSSAne S4N4S4N 22 Az Z7-27 2 W 2O B INVENTOR. AOAARTAYWOARMMAW AOMEA ESTEPHEWsov w A77OAWEY July 8, 1969 R; H, NORMAN ET AL 3,454,785 SHIFT REGISTER EMPLOYING INSULATED GATE FIELD EFFECT TRANSISTORS INVENTOR. AOAAA7 A. WOAAAW BY A/OMAA AS7AAA/EAVSOMW ATIOAM/AW United States Patent Office 3,454,785 Patented July 8, 1969 2 3.454,785 SHIFT REGISTEREMEosing INSULATED GATE FIELD EFFECT TRANSSTORS Robert H. Norman, Los Altos, and Homer E. Stephenson, Sunnyvale, Calif., assignors, by mesne assignments, to Philico-Ford Corporation, a corporation of Delaware Filed July 27, 1964, Ser. No. 385,444 with a suffix b, and the source electrodes with a suffix c. By Way of example, the source electrode of transistor 22 is designated 22c. As shown in FIG. 3, the shift register includes 10 groups I-X of three transistors each although in practice at least forty groups are generally employed. The odd groups I, III, V, VII and IX are disposed in parallel relation along chip 50 as are the even groups II, IV, U.S. C. 307. 22. 8 Claims VI, VIII and X. In practice, the foregoing ten groups merely occupy one-fourth of the surface of a typical The present invention relates in general to a shift O chip and a similar construction and arrangement is pro register or clocked delay line and more particularly to a vided for the remaining three fourths of the chip. shift register employing field effect transistors. Connected to terminal 60 (FIG. 3) is a negative supply Heretofore shift registers employing field effect tran voltage Vss terminal connected to the drain electrodes of sistors were complicated in construction and required transistors 20, 23, 26, 29, 32, 35, 38, 41, 44, and 47, complex driving signals. For example, one such shift 5 by way of bus 61. register requires field effect transistors of both conductivity The input signals for the shift register are supplied to types in each stage and four phase bipolar clock pulse terminal 66 which is connected to gate 22a of transistor 22. driving sources. Accordingly several objects of the present invention 20 The delayed output signals are supplied by the shift Int, C. Gib 9/06 are: (1) to provide a new and improved shift register register at output terminal 99 which is connected to the Source electrode 47c of transistor 47. using field effect transistors, (2) to provide such a shift register whose construction and operation are relatively Supplied to the gate electrodes of transistors 20, 21, simple and therefore more reliable, and (3) to provide 26, 27, 32, 33, 38, 39, 44, and 45 by way of a bus 81 such a shift register which requires relatively simple driv is a negative clock pulse train shown at p1 in FIG. 4. ing signals. Additional obpects of the invention are: (4) Supplied to the gate electrodes of transistors 23, 24, to provide a shift register which can easily be constructed 29, 30, 35, 36, 41, 42, 47, and 48 by way of a bus 86 in integrated circuit form, (5) to provide a shift register is an out-of-phase clock pulse train shown as b2 in FG. 4. which requires relatively low power, (6) to provide a shift register which has a wider frequency range of oper 30 From the foregoing, it is to be noted that clock pulses ation, and (7) to provide a shift register which can be made to have as many stages as desired. Other objects and advantages of the present invention will be apparent to one skilled in the art from the follow p1 are impressed on the gates of the top two tran sistors of each odd group while clock pulses p2 are impressed on the gates of the top two transistors of the alternate or even groups. ing description taken in conjunction with the accompany 35 For connecting the groups I-X of transistors in cas ing drawings, in which: cade, the source electrode of the top transistor of each FIG. 1 is a diagrammatic plan view of an integrated group is connected to the gate electrode of the bottom transistor of each Succeeding group. circuit embodiment of the shift register of the present invention. A ground bus 100 and a metal terminal pad 101, FIG. 2 is an enlarged fragmentary vertical sectional 40 which is also made from an aluminum film strip. The view taken along line 2-2 of FIG. 1. aluminum film strip 100 is connected to the source elec FIG. 3 is a schematic diagram of the shift register of trode of the bottom transistor of each group. By employing metal oxide semiconductor field effect the present invention. FIG. 4 is a graphic representation of the clock pulse transistors, a relatively high resistance-capacitance time synchronizing signals and the data input signal Supplied constant is attained between successive transistors for to the shift register. interstage storage in excess of the phase time difference of the p2 and b1 pulses. As shown in FIGS. 1 and 2, the shift register of the invention comprises a plurality of interconnected in It is to be noted that the top transistor of each group has a higher conducting impedance from source to drain sulated gate or metal oxide semiconductor field effect transistors 20–49. Although these transistors are shown 50 than that of the other two transistors of the same group. as embodied in a single semiconductor body 50, which As is well known, the conducting impedance of the tran may be of N-type silicon, discrete devices with separate sistors 20-49 is controlled by the device geometry and external interconnections may alternatively be utilized. dimensions. The top transistor of each group acts as a As shown in FIG. 3, transistors 20-49 are arranged load device, the middle transistor as an isolation device, in groups of three, with typical groups being 20-22, 55 and the bottom transistor as a data input and storage 23-25, 26-28, 29-31. . . . 47-49. The source-drain cir cuits of each group of three transistors are connected elec trically in series by means of the usual metallic (e.g., device. The load and isolation transistors of each odd numbered group are rendered conductive or enabled when the Synchronizing clock pulse signal b1 is negative. Like Each transistor has a gate electrode, a soure region, 60 Wise, the load and isolation transistors of each even numbered group are rendered conductive or enabled and a drain region. The drain and source regions are when the Synchronizing clock pulse signal b2 is negative. formed of P-type regions 51-56, which are diffused in Transistor 22 of group I is enabled or rendered con body 50. By means of the aluminum surface conductors, aluminum) film surface conductors. ductive while the data input signal fed to the gate elec ohmic contacts are formed on the source and drain 22a thereof is negative. regions through holes in the silicon dioxide surface layer 65 trode During the first cycle of operation, a negative input 57. A disclosure of the foregoing may be found in the 'signal to be delayed is fed to gate 22a to enable tran patent to Dawon Kahng, No. 3,102,230, issued Aug. 27, 1963, for Electric Field Controlled Semiconductor Device. sistor 22 while the clock pulse b1 is negative. Since at this time a negative voltage is supplied to the gate elec In FIGS. 1 and 3, the gate electrodes of transistors trodes of all three transistors, a current will flow from 20-49 are designated by the reference numeral of the 70 the VSS source through all these series connected source associated transistor with a suffix a, the drain electrodes drain circuits. Transistors 20-22 will stop conducting 3,454,785 3 current when the clock synchronizing pulse signal p1 returns to Zero potential. While transistors 20–22 of group I are conducting, any charge present at the gate electrode 25a of transistor 25 of group II will be discharged through the transistors 21 5 and 22 to ground. Thus, any charge on gate electrode 25a of transistor 25 of group II will be reduced to substantially zero when a negative input is supplied to gate electrode 22a and a clock pulse signal appears on the $1 bus. This is analogous to the customary inverting function pro vided by most amplifying stages. When the synchronizing clock pulse signal pit returns to zero, the semiconductor devices 20-21 are turned off, leaving the input capacity discharged and isolated by the high input impedance at the junction of 20c, 21b, and 25a. This discharged condition will be maintained for a period greater than one-half the interval between successive pulses in the clock synchronizing pulse signal p1. When the synchronizing clock pulse signal p2 goes O 4. having a gate electrode, a source electrode, and a drain electrode, a first transistor of each group hav ing a higher conducting impedance from source to drain than the other transistors of each group, means for supplying an input signal to the gate elec trode of a second of said transistors of said first group, means on said body for connecting the Source electrode of said first transistor of said first group to the gate electrode of a second of said transistors of said Sec ond group so as to connect said second group of means for supplying a first train of synchronizing pulses to the gate electrodes of the transistors of Said first group other than said second transistor thereof, means for supplying a second train of synchronizing pulses signal to the gate electrodes of the transistors of said second group other than Said second transistor transistors in cascade with said first group, thereof, said second train of synchronizing pulses being out of time phase with said first train of synchronizing pulses, and means connected to said second group of transistors tive, transistors 23 and 24 but not transistor 25 will con for supplying an output signal representative of a de duct. As a consequence thereof, a negative potential layed version of said input signal. representative of the data input signal delayed one cycle 25 2. A shift register comprising a plurality of groups of is transferred via lead 91 to the gate electrode 28a, thereby transistors, each group comprising a plurality of field effect causing a negative charge to be stored on the gate elec transistors which are connected in series from Sources to trode 28a. This potential charge is equal to Vss less the voltage drop across transistor 23. drain, The negative charge applied to the gate electrode 28a 30 means for connecting said groups of transistors in cascade, is sufficient to render transistor 28 of group III conductive. means for supplying a first train of synchronizing pulses When the clock pulse signal b2 returns to zero, transistors 23-25 will be non-conducting leaving the input capacity to alternate groups of said transistors, said pulses being supplied to the gate electrodes of plurality of to the gate 28a charged and isolated by the high input transistors of each group, impedance at the junction of 23c, 24b and 28a. This means for simultaneously supplying a second train of charge will be maintained for a period greater than one synchronizing pulses to the gate electrodes of a plural half the interval between successive pulses in the clock ity of transistors of a group of transistors interposed Synchronizing pulse signal d52. between said alternate groups, At the time the next pulse of the clock pulse signal p1 is supplied the gate electrodes of transistors 26 and 27 40 said second train of synchronizing pulses being out of time phase with said first train of synchronizing of group III will go negative along with gate electrode pulses, 28a. This will cause any potential on the gate electrode negative the near zero potential at the gate electrode 25a 20 of transistor 25 of group II will insure that transistor 25 remains nonconductive. Thus when the d52 bus goes nega 31a to be discharged through transistors 27 and 28 to near ground. The above-described sequence will thereafter be repeated for the succeeding groups of transistors. It is apparent, therefore, that the signal transferred to the even group II, IV, VI, VIII and X in the shift register will be representative of the input signal with an opposite polarity and delayed one-half bit time from the preceding odd group, and that the signal presented to the odd groups III, V, VII, and IX will be representative of the input signal with the same polarity and delayed one bit time from the preceding odd group. The output of group X will be representative of the input signal at the same polarity with a five bit delay. 55 Thus, the shift register is capable of performing the function of a synchronized delay line. Any desired delay or register length can be attained by adding in cascade addi tional groups of transistors. During a succeeding cycle, another negative input signal 60 can be fed to the gate electrode transistor 22 of group I and will thereupon be propagated in clock synchronism through the shift register until fed to the output terminal. The advancement of the input signals through the shift Tegister is slaved to the timing of clock synchronizing pulses p1 and p2. It is to be understood that modifications and variations of the invention disclosed herein may be resorted to without departing from the spirit of the invention and the scope of the appended claims. We claim: 1. A shift register comprising: a semiconductor body, a first group and a second group of field effect transistors formed in said body, each transistor of each group means for supplying an input signal to the gate elec trode of one transistor in a first group of said transis tors, and means connected to a last group of said transistors for Supplying an output signal. 3. A shift register comprising: a first and a second group of field effect transistors, each group including first, second, and third trans sistors, each of said transistors having a gate electrode, a source electrode, and a drain electrode, Supply voltage means for supplying a bias potential to the drain electrodes of said first transistor of each of said groups, means for Supplying a first train of synchronizing pulses to the gate electrodes of said first and second tran sistors in said first group, means for supplying a second train of synchronizing pulses to the gate electrodes of said first and second transistors in said second group, said second train of synchronizing pulses being out of time phase with said first train of synchronizing pulses, means connecting the source electrode of the first tran sistor in said first group to the gate electrode of the third transistor in said second group for connecting said two groups in cascade, means for Supplying an input signal to the gate elec trode of the third transistor in said first group, whereby the simultaneous application of said input signal to said third transistor of said first group and Said first synchronizing pulse signal to said gate electrodes of said first and second transistors of said 5 3,454,785 first group will render the transistors of said first group conductive so as to discharge any potential charge stored on the gate electrode of said third transistor of said second group, and means connected to the source electrode of said first transistor in said second group for supplying an out put signal representative of a delayed version of said input signal. 4. A shift register comprising: a first and a second group field effect transistors, each 10 group having first, second, and third transistors, each of said transistors having a gate electrode, a source electrode, and a drain electrode, said first transistor of each group having a higher con ducting impedance between its source and drain elec trodes than said second and third transistors of each grOtp, Supply voltage means for supplying a bias potential to the drain electrodes of the first transistor in each of said groups, means for Supplying a first train of synchronizing pulses to the gate electrodes of said first and second tran sistors in said first group, 20 means for supplying a second train of synchronizing pulses to the gate electrodes of said first and second transistors in said second group, time phase with said first train of synchronizing pulses, means connecting the source electrode of the first tran 30 sistor in Said first group to the gate electrode of the third transistor in said second group for con necting said second group in cascade with said first grOllp, means for Supplying an input signal to the gate elec 35 trode of the third transistor in said first group, Whereby the simultaneous application of said input sig nal to said third transistor in said first group and said first Synchronizing pulse signal to said gate electrodes of Said first and second transistors of said first group 40 Said Second train of synchronizing pulses being out of will render the transistors in said first group conduc tive so as to discharge through said first and second transistors in said first group any charge stored on the gate electrode of said third transistor in said 45 Second group, and means connected to the source electrode of said first transistor in said second group for supplying an out put signal representative of a delayed version of said input signal. 50 5. A shift register comprising: a first data input field effect transistor having gate, Source, and drain electrodes, means for Supplying an input signal to the gate elec trode of Said first transistor for controlling the con duction thereof, 55 a second data input field effect transistor having gate, Source, and drain electrodes, an isolation field effect transistor having gate, source, and drain electrodes, the source-drain circuit of said isolation transistor being 60 connected between the drain electrode of said first data input transistor and the gate electrode of said Second data input transistor, means for Supplying a first train of synchronizing pulses 6 path for discharging any charge on the gate electrode of said second transistor, when said first transistor is conducting, and a load field effect transistor having gate, source, and drain electrodes, the source-drain circuit of said load transistor being connected in series with the source drain circuit of said first transistor, the gate electrode of said load transistor being con nected to the gate electrode of said isolation transistor. 6. The shift register of claim 5 further including: a second load transistor having gate, source, and drain electrodes, the Source-drain circuit of said second load transistor being connected in series with the source-drain cir cuit of said second transistor, and means for Supplying a second train of synchronizing pulses to the gate electrode of said second load tran sistor for controlling the conduction thereof, said second train of synchronizing pulses being out of time phase with said first train of synchronizing pulses. 7. A transistor circuit comprising: a first data input field effect transistor of one conduc tivity type having a source, gate, and drain electrodes, means for Supplying an input signal to the gate electrode of Said data input transistor, a first isolation transistor and a first load transistor, each being of said one conductivity type and having gate, Source, and drain electrodes, the Source-drain circuit of said load and isolation tran sistor being connected in series with the source-drain circuit of data input transistor, means for Supplying a direct current bias potential be tWeen the source electrode of said load transistor and the drain electrode of said data input transistor, means for Supplying a first train of clock pulses to the gate electrodes of said isolation and load transistors to control the conduction thereof, and means connected to the junction of said load and isola tion transistors for supplying an output signal. 8. The circuit of claim 7 further including a second data input transistor, a second isolation transistor, and a Second load transistor, each being similar to said first data input, isolation, and load transistors, the Source-drain circuits of said second transistors be ing connected in series across said means for supply ing a direct current bias potential, means for connecting the source electrode of said first load transistor to the gate electrode of said second data input transistor, and means for supplying a second train of clock pulses to the gate electrodes of said second isolation and load transistors to control the conduction thereof, said Second train of clock pulses being out of time phase with said first train of clock pulses. References Cited 2,971,101 UNITED STATES PATENTS 2/1961 Hurst et al. --------- 328-42 3,233,123 2/1966 Heiman ------------ 3.07-88.5 3,252,009 5/1966 Weimer ------- 307-88.5 3,215,859 11/1965 Sorchych ---------- 307-88.5 to the gate electrode of said isolation transistor for 65 ARTHURGAUSS, Primary Examiner. JOHN ZAZWORSKY, Assistant Examiner. controlling the conduction thereof between on state and an off state, U.S. C. X.R. whereby said off state of said isolation transistor iso lates said second transistor from said first transistor 307-238,251, 303, 304 and said on state of said isolation transistor forms a 70 32. UNITED STATES PATENT OFFICE CERTIFICATE OF CORRECTION Patent No. 3'-5's 785 Dated July 8, 1969 Inventor(s) Robert H. Norman and Homer Eo Stephenson It is certified that error appears in the above-identified patent and that said Letters Patent are hereby corrected as shown below: - Column 5, line lO, after "group" insert -- of --. Column 6, line 24, after "having" delete "a". Column 6, line 31, change "sistor" to -- sistors --. SIGNED AND SEALED APR140 (SEAL) Attest: Edward M. Fletcher, Jr. Attesting Officer - WILLIAM E. SCBUYLER, Jr. commissioner of Fate