Historical Document · 1969
US Patent 3,453,601: Two Speed Arithmetic Calculator (Bogert and Miner, Victor 3900)
The Victor 3900's MOS calculator, running at 330 kHz to compute and 60 kHz to display, with stroke-drawn figure-8 digits.
Historical Document · 1969
The Victor 3900's MOS calculator, running at 330 kHz to compute and 60 kHz to display, with stroke-drawn figure-8 digits.
July 1, 1969 H. Z. BOGERT ET AL 3,453,601 TWO SPEED ARITHMETIC CALCULATOR Filed Oct. 18, 1966 2 17 away 17a 7A222 2012 aZ 12 AAA/ (af21zew) aa Maa. 22 aOAvaz 1a/Ya/Myaya aadafoa Maat 2' 22% 2.2% Aaaay 7 27. S. / 7G. M (14 czaro wr/ 7mo-?azza Czoc a2 arr U Ulf LJ U L Ulf "U up/ ----- afya AMWA ama A. Maay 22 / 7G. 2. awarazzarze a 2- aza. A Azai Zafav f- ceavaMa Mwas a me a - 12 (1/4//olf): c-/ao 12 INVENTORS wease.222 r BY 529ead 61Au 72afavaty United States Patent Office 1. 3,453,601 3,453,601 Patented July 1, 1969 2 strobed circuits which are operative during both the dis play and calculating modes will be the same in both modes, This is highly wasteful of power since a desk top calcula Howard Z. Bogert, Cupertino, and Jay G. Miner, Sunny tor will operate in the display mode hundreds to thousands vale, Calif., assignors to Philco-Ford Corporation, Philadelphia, Pa., a corporation of Delaware 5 of times longer than it operates in the calculating mode. In addition to power wastage, the unnecessary heat produced Filed Oct. 18, 1966, Ser. No. 587,448 Int, C. G. b. I3/00 during the display mode shortens the life and decreases the U.S. C., 340--1725 10 Clains reliability of electronic components, especially in view of the fact that the display mode of a desk top calculator TWO SPEED ARTHMETIC CALCULATOR ABSTRACT OF THE DISCLOSURE Recirculating arithmetic calculator employing an arith metic processor and a dynamic display means which is activated after completion of the arithmetic processor's operations. During its arithmetic mode, the calculator is clocked with high frequency pulses to obtain high calculat ing Speel, and during its Subsequent display mode, the cal culator is clocked with low frequency, low duty cycle O often occurs for hours at a time. When such electronic components are formed entirely within monolithic inte grated circuits, the heat generated in these circuits is par ticularly harmful, as will be recognized by those skilled in the art. Accordingly, several objects of the present invention are: (1) to provide an arithmetic calculator whose calcu lating speed is not limited by the maximum speed by which a dynamic display unit can be operated, (2) to provide an arithmetic calculator whose display unit can be operated pulses to minimize power consumption. The calculator may employ active element circuits, such as a shift register 20 at a relatively slow speed for ease of display and lower reduction but whose arithmetic processing unit can be and load transistors periodically rendered conductive by operated at its maximum speed for minimizing computa clock pulses. In this arrangement power consumption will tion time, (3) to provide an arithmetic calculator which be proportional to the duty cycle of the clock pulses. utilizes, comparatively little power and generates compara 25 tively little heat during the display mode, and (4) to pro vide an arithmetic calculator of increased reliability and This invention relates to computing machines and more longevity. Other objects and advantages of the present in particularly to a serial type recirculating arithmetic cal culator having dual operating speeds. In the following dis vention will be apparent from a consideration of the en suing description thereof. cussion, the invention will be described with reference to its application in an electronic calculator of the type which 30 SUMMARY utilizes a recirculating memory to provide temporary stor According to the present invention an arithmetic calcula age during calculation and to provide a recurrent drive for tor which includes a serial type recirculating memory and a dynamic output display unit. However the invention is dynamic display means driven by said memory utilizes a fully applicable to stored program type computers which two speed clock pulse generator for clocking the compo use a recirculating memory to drive a dynamic output dis nents of the calculator at a relatively fast speed during play inasmuch as such a computer includes circuitry sim computation operations and a relatively slow speed during ilar to the present calculator, differing therefrom prin the display mode. cipally in that it also includes a stored program capacity DRAWINGS and a multiple address memory. 40 In the aforementioned type of arithmetic calculator, a FIG. 1 shows a block diagram of a calculator accord clock pulse generator is provided to drive the various cir ing to the invention. cuits of the calculator in synchronism. Heretofore the FIG. 2 shows a schematic diagram of a shift register clock pulses supplied by Such a generator were of a fixed which may be used in the calculator of FIG. 1. frequency which was set at the maximum reliable oper 45 F.G. ating speed of the slowest component of the calculator. In a typical recirculating calculator the slowest component is The calculator of FIG. 1 comprises a serial arithmetic Li Sually the dynamic display device (e.g., a cathode ray processor 10 for performing arithmetic operations on se tube numerical displayer). Since a dynamic display device rial binary digital data, a shift register 12 for providing a is able to operate at only a fraction of the speed of a serial dynamic memory for processor 10, and a display control arithmetic processor, it will be apparent that utilization of unit 14 which is arranged to receive information from a fixed frequency clock pulse generator severely limits cal culating speed. In a desk-type electronic calculator, for processor 10 and supply said information in a suitable form for display purposes to display unit comprising a example, typical arithmetic calculations will usually take cathode ray tube 16, Connected to the vertical and hor as long as several seconds if the calculator is clocked by 5 5 izontal deflection plates (X and Y inputs) of tube 16 is a a single frequency clock pulse generator. This is highly typical numeral 8 pattern and deflection generator 18 undesirable, as will be recognized by those experienced in which is arranged to cause an electron beam, when gen usage of desk-type calculators. erated at the cathode of tube 16, to trace out a series of Another disadvantage found in calculators which use a rows of numeral 8's such as shown at 20 on the faceplate fixed frequency clock pulse generator is unnecessarily high 60 of the tube. Each 8 is formed of a matrix of straight power consumption during the display mode. In a calcula strokes of the electron beam. Under control of the display tor of a type wherein the display device is driven by active unit 14, the Z axis input of the cathode ray tube is modu element circuits, such as a shift register, which utilize ac lated in order to blank completely or illuminate selected tive elements which are strobed (i.e., gated into an opera strokes of the numeral 8's so as to write blanks or num tive state) by the clock pulses, the percentage of time that bers on the faceplate of tube 16 as shown. The operation the active element circuits are "on' and consuming power of the calculator is programmed by a sequence control or will be proportional to the duty cycle of the clock pulse phase counting unit 22 which, via connection 24, causes waveform. In a calculator of the type which utilizes a sin the arithmetic processor 10 to perform an assigned opera gle frequency clock pulse generator, the duty cycle of the tion on input data supplied to the calculator from a suit clock pulse waveform during the display mode is, of able input unit (not illustrated), and via lead 26, to ac course, the same as that during the calculating mode; tivate the display control 14 so that the information cir culating from processor 10 to register 12 and back to proc hence the power consumed in the shift register and other 3,453,601 4 3 quency clock pulses should be the same; thereby the duty essor 10 will be displayed on the faceplate of cathode cycle of the low frequency clock pulses will be reduced in ray tube 20 during the display mode. The calculator is proportion to the frequency reduction thereof. driven by a clock pulse generator 28 which is arranged to In one embodiment of a typical desktop solid state elec Supply on its output terminal 30 synchronizing and oper tronic calculator using strobed circuits, the clock pulses ating clock pulses for all of the components of the calcu were supplied during the calculation mode at a frequency lator (except tube 16). Each component has a clock pulse of 330 kHz. with 50% duty cycle while during the display input terminal, such as terminal 32 of shift register 12, mode their frequency was reduced to 60 kHz, without to which clock pulses from terminal 30 are supplied. changing the width thereof. The power consumed during All of the elements of the calculator aforedescribed are well known and familiar to computer engineers. A serial () calculation was 30 watts while during the display mode the power consumed was 20 watts, the difference of 10 watts computer which embodies the calculator shown is de scribed for example, on pages 316 et seq. of Digital Com being represented as a reduction of heat dissipated in the integrated circuits of the calculator due to the shorter duty puter Fundamentals by Bartee (McGraw-Hill 1960) and cycle of the low frequency clock pulses. on page 367 of Analog and Digital Computer Technology It will therefore be apparent that the provision of a two by Scott (McGraw-Hill 1960). A suitable dynamic dis speed clock pulse generator will provide increased cal play unit similar to that shown is described in the articles culation speed with reduced display mode power consump Computer Generated Displays by Loewe et al., 49 Proc. tion and heat dissipation. IRE 185, January 1961), and Alphanumeric Characters The implementation of a two speed clock generator with On Any Cathode Ray Tube in Military Systems Design, July-August 1960. The shift register 12 of applicants' cir 20 a fast speed for computation mode and a slow speed for the display mode can be achieved, for example, by provid cuit is of course interchangeable with one track of the ing for clock pulse generator 28 a dual frequency astable drum type recirculating serial memory shown in Bartee. multivibrator which normally oscillates at the desired fast The operation of the calculator of FIG. 1 is apparent or high frequency rate but which can be made to oscillate from the descriptions given in the aforementioned and at the slow or low frequency rate by gating in a different other texts and will not be described in detail here. Gen set of timing resistors in response to energization of a erally, the calculator of FIG. 1 is operated by first entering “slow' input lead 34 thereof. The multivibrator 28 can be information (e.g., a multiplicand) into the recirculating made to operate at the slow rate during the display mode loop including storage register 12. Thereafter additional by connecting the slow lead 34 thereof to the display con information (e.g., a multiplier) is entered into the calcu trol lead 28 of the sequence control unit 22. Other suit 30 lator. Sequence control unit 22 is thereafter activated (e.g., able systems of implementing the operation of the two by pressing a "=" key). Control 22 will cause the cal speed clock pulse generator will be apparent to those culator to perform the assigned operation on the input skilled in the art. data, and after the operation is completed and the desired output information is circulating through register 12, con FIG. 2 trol 22 will energize lead 28 to allow the display control As stated, if the shift register 12 of FIG. 1 and option 14 to convert the binary digital information circulating ally the other logic circuits which are active during the in the loop to a suitable decimal code for application to display mode are of the type which embody active ele the Z axis input of cathode ray tube 16 in order to display the circulating information visually. This display means in 40 ment circuits which are strobed on by each clock pulse, a great reduction in power consumed and heat generated cluding elements 14, 16, and 18 is a dynamic display unit will be effected during the display mode if the low fre because it operates by writing the information circulating in the register on a temporary display medium (the face quency clock pulses utilized to drive the calculator dur ing the display mode have a shorter duty cycle than the plate of tube 16) each time the information circulates fast clock pulses. To illustrate clearly the power-saving around the register. feature of the invention, FIG. 2 shows the circuitry of In prior art calculators of the type shown in FIG. 1 the one such shift register, i.e., of the type which uses stages clock pulse generator 28 provided clock pulses of a single, which are strobed on by the clock pulses. fixed frequency only. While it is of course desirable to The shift register of FIG. 2 is composed of a plurality have the output frequency of the clock pulses supplied by of identical cascaded stages such as 50 and 52, each generator 28 as high as possible to minimize calculation of which includes six Metal-Oxide-Silicon-Transistors time, it was not possible to do so because the maximum (MOST's). Details of the construction and operation of operating speed of the display units 14, 16, and 18 was the MOST, which is also known as an Insulated Gate far less than that at which the arithmetic unit 10 could Field Effect Transistor, are given in the IEEE Trans operate. Hence the calculating speed of prior art calcula actions on Electron Devices, July 1964, pp. 324-345. In tors was below that of which the arithmetic circuits more capable. Furthermore, much unnecessary power and heat 5 5 practice, the MOST's shown are not discrete devices with external interconnections but rather are all formed was generated during the display mode when strobed logic entirely within an integrated circuit consisting of a mono and shift register circuits were used since the duty cycle lithic chip of silicon. A monolithic shift register as shown of the single frequency clock pulses was the same during having 100 stages with 6 MOST's per stage is currently calculation and display modes. According to the invention, the clock pulse generator 60 marketed by the Microelectronics Division of Philco Corporation, Santa Clara, Calif., and is described fully 28 is designed to supply dual frequency clock pulses alter in the co-pending application of Howard Z. Bogert, Ser. natively, i.e., high frequency clock pulses during the cal No. 498,026 filed Oct. 19, 1965, entitled "Memory culation mode and low frequency clock pulses during the Device,” now Patent 3,395,292, granted July 20, 1968. display mode. In this way the calculation time can be In the first stage 50 of the shift register, the source minized by supplying the clock pulses during the calcula and drain electrodes of MOST's 56 and 58 are connected tion mode at the maximum frequency which can be han in series across a negative upply source 60. The source dled reliably by the arithmetic processing units. Also, pow and drain electrodes of MOST's 62 and 64 are similarly er consumption and heat dissipation during the display connected. The gate electrode of MOST 58 is connected mode can be minimized in strobed circuits by supplying the clock pulses at the same width but at a frequency 70 to input lead 54 and the gate electrodes of MOST's 56 and 62 are connected to buses 66 and 68, respectively, just high enough to prevent perceptible flicker of the displayed image. Of course the duty cycle of the clock which supply clock pulses CP1 and CP2, respectively. pulses supplied during the display mode should be less The junction of MOST's 56 and 58 is connected to the gate of MOST 64 by way of an isolating MOST 70, and than that of the clock pulses supplied during the computa tion mode. Desirably the width of the high and lower fre 75 the junction of MOST's 62 and 64 is connected to the out 3,453,601 5 put terminal 72 of stage 50 by way of a second isolating 6 trains CP1 and CP2. If the input pulses CP occur at the MOST 74. The gate electrodes of MOST's 70 and 74 fast rate, the driving clock pulses CP1 and CP2 will are also connected to buses 66 and 68 respectively. Desir occur at a fast rate as shown by the upper waveforms ably the MOST's are designed to have the transconduct over buses 66 and 68, respectively. When the clock pulses ances indicated by the legend in the lower left hand occur at the slow rate, CP1 and CP2 will occur at a corner of the drawing. slow out-of-phase rate as indicated by the lower wave In operation, each stage of the shift register is strobed forms over buses 66 and 68, respectively. Since CP1 with out-of-phase clock pulses CP1 and CP2 which are and CP2 are generated in single shot multivibrators 82 shown for both the fast and slow modes in the wave and 84, they will have a constant width, irrespective of form diagram above the shift register. The clock pulses O their frequency. are described as "out-of-phase' clock pulses because the It will thus be appreciated by those skilled in the art pulses in each train occur during mutually exclusive time that since the duty cycle of the CP1 and CP2 clock pulses intervals. A binary digit, which may be a ONE (negative is substantially shorter at the slow rate, the shift register voltage) or ZERO (ground voltage) is supplied to the will consume substantially less power during the slow input terminal 54 of the first stage 50 of the shift register. clocking rate. In addition, if display control 14, processor The binary digit will be shifted through the shift register 10, and generator 18 are designed using strobed active by the clock pulses CP1 and CP2 and will appear at the element circuits, a greater power saving can be effected. output of successive stages of the shift register at succes The shift register at FIG. 2 can be implemented by sive intervals equal to the period of the CP2 pulses. conventional transistors connected in the same manner as Thus if the out-of-phase clock pulses CP1 and CP2 20 indicated; however, MOST's are to be preferred since occur at the fast rate, the binary digits will be shifted more MOST's can be fabricated in a given area of a through the shift register rapidly and if the clock pulses silicon microcircuit monolith at lower cost. occur at the slow rate, the binary digits will be shifted While there has been described what is at present con through the register at a slow rate. sidered to be the preferred embodiment of the invention, For example, assume that a negative voltage repre 25 it will be apparent that various modifications and other senting a binary ONE is supplied to input lead 54. This embodiments thereof will occur to those skilled in the art voltage will charge the gate electrode capacitance of within the scope of the invention. Accordingly, it is desired MOST 58 so as to bias MOST 58 in a state whereby that the scope of the invention be limited by the appended the normal substantially infinite impedance between the claims only. source and drain electrodes of the MOST will be lowered 30 greatly when a negative voltage is supplied to the drain electrode of the MOST. Thus, when the next clock pulse CP1 is supplied to the gate electrodes of MOST's 56 and 70, all three MOST's 56, 58, and 70 will be driven conductive and a low impedance path will be provided between the gate electrode of MOST 64 and ground by way of MOST's 70 and 58, Hence any charge present on the gate electrode of MOST 64 will be bled away during CP1. The next clock pulse to occur will be CP2 on lead 68 40 which supplies a negative voltage to the gate electrodes of MOST's 62 and 74, causing these devices to become conductive. Since no charge is present on the gate elec trode of MOST 64, this device will not conduct; hence a low impedance path will be created between negative source 60 and the gate electrode of MOST 58' of stage 52 by way of MOST's 62 and 74. Thereby a negative output voltage will be provided on lead 72 which is indicative of the transference of the binary ONE from stage 50 to stage 52. The aforedescribed sequence of events will thereafter 50 be repeated in stage 52 in an identical manner when the next CP1 and CP2 clock pulses arrive, causing the binary ONE to appear at the output of stage 52 one cycle later. If a ZERO is supplied to input lead 54 of stage 50. 55 We claim: 1. A recirculating arithmetic calculator, comprising, in combination: (a) a Source for supplying clock pulses at either a relatively high frequency or a relatively low fre quency, (b) a serial arithmetic processor for performing arith metic operations on digital information at a speed governed by the frequency of said clock pulses, (c) a shift register for continuously receiving digital information in serial form from said arithmetic proc essor and recirculating said information, at a speed determined by the frequency of said clock pulses, through a plurality of stages thereof, to said arith metic processor, (d) dynamic display means for visually displaying, in response to a display command signal, said informa tion at the same location in a temporary display medium each time said information circulates through said register, (e) sequence control means for programming the op eration of said arithmetic processor and providing said display command signal to activate said display means upon completion of said arithmetic opera tions, and (f) means for causing said source to supply said clock no charge will be placed on the gate electrode of MOST pulses (1) at said relatively high frequency while 58 and the CP1 clock pulse will turn MOST's 56 and said arithmetic operations are performed and (2) at 70 on, providing a relatively low resistance path between said relatively low frequency while said display negative source 60 and the gate electrode of MOST 64 means is activated. by way of MOST's 56 and 70. When the next clock pulse 60 2. The calculator of claim 1 wherein means are pro CP2 is supplied to the gate electrodes of MOST's 62 vided for supplying said clock pulses to at least said shift and 74, all three MOST's 62, 64, and 74 will be turned register at a substantially constant width irrespective of on, providing a low impedance path between the gate the frequency of said clock pulses, and wherein each stage electrode of MOST 58' and ground by way of MOST's of said shift register comprises at least one series circuit 74 and 64, thereby providing ZERO volts on lead 72 connected across a biasing source, said circuit including and “transferring the binary ZERO to stage 52. two Serially-connected variable impedance devices, each The out-of-phase clock pulses CP1 and CP2 can be of Said devices having an impedance control electrode, derived from the input clock pulses applied to input said digital information being supplied to the control elec terminal 32 by first providing the inversion of the clock trode of one of said devices and said clock pulses being pulses (CP) at terminal 80 (e.g., by inverting the input 70 Supplied to the control electrode of the other of said clock pulses or by connecting a lead to the other side devices, whereby the average power consumed by said of astable multivibrator from which the input clock shift register will be less when said clock pulses are sup pulses were derived). The clock pulses CP and ("I plied to said shift register at said slow rate. are then applied to respective single shot multivibrators 3. The calculator of claim 2 wherein said means for 82 and 84 which provide the respective out-of-phase pulse 75 supplying said clock pulses to said shift register is ar 3,453,601 8 said calculator being characterized in that (1) said clock pulse source is arranged to supply clock pulses at either a relatively high frequency or a relatively low frequency, (2) means are included for causing said colculator being characterized in that (1) said relatively high frequency while said arithmetic op erations are performed and (b) at said relatively low frequency while said display means is activated. electrode of the first MOST of said first circuit, the gate 7. The calculator of claim 6 wherein each stage of said electrodes of said second MOST's of said first and sec register includes at least one series circuit connected ond series circuits being driven by said first and second 10 shift across a bias source, said circuit including at least one pulse trains, respectively, the junction of said MOST's impedance device which has a high impedance state when of said MOST's of said first circuit being connected to not supplied with a strobe pulse and a low impedance the gate electrode of said first MOST of said second cir state when supplied with said strobe pulse, and including cuit by way of a first isolation MOST whose gate elec means for deriving from said clock pulses strobe pulses trode is driven by said first pulse train, the junction of said of proportional frequency and supplying said strobe MOST's of said second circuit being connected to an out pulses to each of said controllable impedance devices of put terminal of said stage by way of a second isolation said shift register, the duty cycle of said strobe pulses MOST whose gate electrode is driven by said second being smaller when said clock pulses occur at said rela pulse train. 4. The calculator of claim 1 wherein said dynamic dis 20 tively low frequency, whereby said shift register will consume less power while said display means is activated. play means comprises a cathode ray tube and associated 8. The calculator of claim 7 wherein each stage of said means for converting digital numerical information circu shift register is fabricated of a plurality of MOST's and lating through said register into a decimal display across wherein a plurality of stages of said shift register are the face of said cathode ray tube. formed within a monocrystalline silicon monolith. 5. The calculator of claim 1 wherein said (f) means 9. The calculator of claim 6 wherein said dynamic dis is arranged to cause said source to change the frequency play means comprises a cathode ray tube and means for of said clock pulses from said relatively high frequency writing said binary-encoded information circulating in to said relatively low frequency in response to said dis said register across the face of said cathode ray tube in play command signal. form by means of an electron beam each time 6. A recirculating arithmetic calculator which includes 30 decimal said information circulates through said register. a serial arithmetic processor for performing arithmetic 10. The calculator of claim 6 wherein means are pro operations on binary-encoded information at a rate gov vided for causing said source to change the frequency erned by the frequency of received clock pulses, a shift said clock pulses from said relatively high frequency register arranged to receive said information from an of to said relatively low frequency in response to said display output of said arithmetic processor and circulate said in command signal. formation through a plurality of stages thereof and back References Cited to an input of said arithmetic process at a rate governed by the frequency of received clock pulses, dynamic dis UNITED STATES PATENTS play means arranged to display visually, in response to 40 3,257,645 6/1966 Lekven ----------- 340-172.5 a display command signal, said information at the same 3,293,614 12/1966 Fenimore et al. --- 340-172.5 location in a temporary display medium each time said 3,362,014 1/1968 Hauck ----------- 340-172.5 information circulates through said register, a sequence controller for programming the operation of said arith metic processor and providing said display command sig 45 GARETH. D. SHAW, Primary Examiner. nal to said display means upon completion of said arith RAULFE B. ZACHE, Assistant Examiner. metic operations, and a clock pulse source for driving all U.S. C. X.R. of the aforelisted elements at a rate governed by the fre 235-152; 340-324 quency of clock pulses supplied thereby, 7 ranged to supply first and second out-of-phase trains of pulses, the pulses in each train being of constant width irrespective of the frequency of said clock pulses, and wherein each stage of said shift register contains first and second of said series circuits, each circuit including first and second series-connected MOST's, each stage hav ing an information input terminal connected to the gate 7" UNITED STATES PATENT OFFICE CERTIFICATE OF CORRECTION Patent No. 3, 453,6Ol Dated July 1, 1969 Inventor(s) H. Z. Bogert and J. G. Miner It is certified that error appears in the above-identified patent and that said Letters Patent are hereby corrected as shown below: - Column 8, line 5, "Colculator being Characterized in that (l) " should read -- source to Supply Said clock pulses (a) at --. SIGNED AND SEALF) OCT 2 1969 (SEA) Attests award floather, Jr. Ahtesting Officer IAN E. Scaura R, R. Giedgioner of Patant