Historical Document · 1969
The SRI-developed Friden display, filed 8 July 1965 and granted 25 February 1969: staircase generators for position, a segment counter, weighted stroke origins and an oscillator sweep for the strokes.
Feb. 25, 1969 CATHODE RAYJ.TUBE J. BIALIK ETAL 3,430,095 BEAM POSITIONING SYSTEM EMPLOYING COMPOSITE SIGNALS Filed July 8, 1965 m s2 eFs -- E ww.---- m n m r --- 3.3.3. e to -O Sheet /... of 44 . od . . JACK J. BALK DALE 2 MASHER WL AM W. STEVENS INVENTORS BY a vaca-ts. ATTORNEY i Feb. 25, 1969 J. J. BAK ETA 3,430,095 CATHODE RAY TUBE BEAM POSITIONING SYSTEM Filed July 8, 1965 EMPLOYING COMPOSITE SIGNALS VERTICAL STAR CASE GENERATOR 1 4 sigNAL HVERT. MIXER 2 of 44 19 VERTICAL DEFLECTON AMP. | WEIGHTED GEN. Sheet sit 6 INHIBIT -12 3. TMNG AND OSc LLATORy ENABLE 56NAL CONTROL O GENERATOR N-BIT WEGTED SISN. GEN, 22 ) 70 24 28 HORIZONTAL AOR. MIXER DEFLECT ON Horizontal STARCASE GENERATOR NN AF 27. ZA HoRNOUTPUT 9 26 JACK J. BALK DALE P. MASER WILLIAM W. SEVENS INVENTORS, J. J. BAK ET All 3,430,095 CATHODE RAY TUBE BEAM POSITIONING SYSTEM EMPLOYING COMPOSITE SIGNALS Sheet D – I T E :ET 3 of 44. Feb. 25, 1969 J. J. BALIK ETAL 3,430,095 CATHODE RAY TUBE BEAM POSITIONING SYSTEM EMPLOYING COMPOSITE SIGNALS Filed July 8, 1965 Sheet 2 N1 7N 1a/Y V 20 GeO4S 6 FF 9 VyN2 8 7 6 4 of 44 O NAN GeGC GeO4S N1 - FF / 1VVn N-1 N1 A Ya n2V 4-4. E. 2 -Gé TRANSFER -G NEG. LEVEL -GeB) POS. TRANSiTION -C) COMPLEMENT -CD POS, LEVEL -4s. RESET -D6) NEG. TRANSiTION -St. SET Feb. 25, 1969 CATHODE RAYJ.TUBE J. BIALIK ET AL 3,430,095 BEAM POSITIONING SYSTEM EMPLOYING COMPOSITE SIGNALS Filed July 8, 1965 Sheet TMING GENERATOR MU - 5.3 5 of 44. Feb. 25, 1969 J. J. BAK ET AL CATHODE RAY TUBE BEAM POSITIONING SYSTEM 3.430,095 EMPLOYING COMPOSTE SIGNALS Filed July 8, 1965 Sheet 6 of 44. - 2v ENABLE GATES (NSERT) s e 7; L 40 f:3R 2 7.2 8 73 R 4. 7: R2 8: L3, 8: L2O C 8 C 7:R3 8; L 15, 8.18, 8: L25 CDov 7: L3 7:3R 7. A 8 2 - 8 s 7:R4 8: ill, 8: L5, 8: il O 2e ey 7:3R4 CD 0. 8 Ž - 7: R5 82 CD C. 7: L7 49 7:3R2 7:18 7:3Rf AND - a. OMU-2,6 a. 4 - e. 7: Res 8: L7, 8; L 22 le a. DO 7: L9 40 7:3R2 7:LO s - 4 +2 s 7: R7 89 2. 7:3R4 E. Gall (7:1) Feb. 25, 1969 Filed July 8, 1965 J. J. BIALIK ET AL CATHODE RAY TUBE BEAM POSITIONING SYSTEM EMPLOYING COMPOSITE SIGNALS 3,430,095 Sheet / 7 of 44 s 7:2 2 2 - e. 7:3R4 7.2.2 7:2R 8: L4, 8 L8, 8til 13, 8: L24 o 7:3R6 7:23 2 7:3R4 7:24 e 7:3R7 7:25 .. e 4e -4 7:2R3 8: L6, 8 L 2, 8 LI7, 8: il 23 7:3 R3 7:27 o -- 2 8: Lil, 8: :2R4 9 - Feb. 25, 1969 CATHODE RAYJ.TUBE J. BIALIK ET AL 3,430,095 BEAM POSITIONING SYSTEM Filed July 8, 1965 EMPLOYING COMPOSITE SIGNALS Sheet 8 of 44 7:3R 7: L 2, 7: L3, 7, IL5 7:3R2 7: Lt, 7 L7, 7: L9, 7, 29 7:3 R3 7:2L6, 7: 2 Li 7:3R4 7: L4, 7: ILO, 7.2L, 7:23, 7:2L12 7: L6, 7, 2L2, 7:25, 7:27 7:3R 7 7: 8, 7: 2L4 73 R8 7 5:4R6 READ FROM K4. M/U-2. R Feb. 25, 1969 CATHODE RAYTUBE J, J. BIALIK ET All 3.430,095 BEAM POSITIONING SYSTEM Filed July 8, 1965 EMPLOYING COMPOSITE SIGNALS Sheet SET STRK, OFF SET STRK. 6 FF SET STRK. 5 FF ST STRK. 4 FF SET STRK. 3 FF SET STRK. 2 FF Set SRK. FF 9 of 44. Feb. 25, 1969 Filled July 8, 1965 9: J. J. Balik ETAL CATHODE RAY. TUBE BEAM POSITONING SYSTEM EMPLOYING COMPOSITE SIGNALS 3430,095 Sheet 70 of 44 SET STRK. O. FF READ KS aCEC A to CC DMU-3.O 9 : 12 SET STRK. IFF O/U-3,9 K 8: R7 9: STRK 8:res RESET HORIZ OL3 9:R4 9 : SET 4 STRK. 3 FF STEP VERT O:L2. 8: R5 3. r 9:RS S RESET SEG, SEN. 0:5 9 : L5 SET SRK 4 FF 9 : L6 SET STRK. 5 FF 8:R3 4 9:R7 D/U- 4.6 STEP HORIZ. RESE WERT. Ot 9: R8 5: 4R2 9: L7 s SET SRK 6 FF 8: R2 X 9:R9 TO GRD OF CRT Feb. 25, 1969 CATHODE RAYJ.TUBE J. BIALIK ETAL 3,430,095 BEAM POSITIONING SYSTEM Filed July 8, 1965 O L EMPLOYING COMPOSITE SIGNALS STEP HOR ARESET VERT Sheet II of 44. WERT STARCASE OR WER. 9:R7 STAR CASE O: L2 STEP WERT GEN. 3. AU - 4.7 HOR. O. L3 RESET HOR SARCASE 9:R3 HOR SARCASE O:R2 GEN, : 2 DAU-48 O: IL4 SHIFT a1a 9:R eva : E SEG, FF3 SEG. G : ORS 2 OR4. 8 O; L5 RESET SEG GEN 9: R5 SEG 2 OR5 6 SEG 2 FORS fl: IL3, it: L9 SEG, 4. Ef O: R7 it 14, II: L7, I L IO E (IO: ) SEG. (4) HOR . : O: R8 5 SEG. (4").veRT. . . Io:IR9 Feb. 25, 1969 CATHODE RAY ,TUBE J. BALK ET All 3,430,095 BEAM POSITIONING SYSTEM EMPLOYING COMPOSITE SIGNALS Filed July 8, 1965. tl: L Sheet 12 of 44 SEG (4"). VERT O:R9 Ov OSC : L2 SEG. : L3 SEG. 2 t; 4 SEG. 4 i: L5 SEG, (4) HOR 6 SEG 2 O: R5 | L7 SEG, 4. O: R7 | L8 SEG. OR4 il: L9 SEG. 2 LO SEG. 4 O: R7 : Lil O. R. VERT. DEF. --) :R VERT, DEF (-) :R2 HOR. DEF (-) :R3 HOR. DEF. (-) :R4 VERT STAR SLANT AD. D/U-6.3 i : 12 O. R2 HOR STAR ( :) Feb. 25, 1969 J. J. BALIK ETAL 3,430,095 CATHODE RAY TUBE BEAM POSITIONING SYSTEM EMPLOYNG COMPOSITE SIGNALS Filed July 8, 1965 Sheet FLP FLIP FLOP "o" "" FF out MGND, POS, VOLTAGE LEVEL NW - 6VOLTS OR - 2 VOLTS = N EGWOTAGE LEVE /3 of 44 Feb. 25, 1969 CATHODE RAYJ.TUBE J. BIALIK ETAL 3,430,095 BEAM POSITIONING SYSTEM Filed July 8, 1965 EMPLOYING COMPOSITE SIGNALS Cl o RS2 39K - 6V - PHILIPS "B892o Oo Sheet 4 of 44 Feb. 25, 1969 Filed July 8, 1965 J. J.; BAK ETAL CATHODE RAY TUBE BEAM POSITIONING SYSTEM EMPLOYING COMPOSITE SIGNALS 3,430,095 Sheet /3 of 44 PHLPS - -l * 2p 727 or Feb. 25, 1969 Filed July 8, 1965 J. J. BALK ETA CATHODE RAY TUBE BEAM POSITIONING SYSTEM EMPLOYING COMPOSITE SIGNALS 3,430,095 Sheet /6 of 44. - Feb. 25, 1969 CATHODE RAYJ.TUBE J. Balik Etal 3,430,095 BEAM POSITIONING SYSTEM Filed July 8, 1965 EMPLOYING COMPOSITE SIGNALS Sheet /7 ONE-SHOT DESIGNATION FIG. N-Nis? SNONE SHOT NO. ONE SHOT (WTHN FIG.) CAC ONE SHOT TYPE CODE (SEE FIG. BELOW) --k2 N3O5 UNLESS OTHER WSE NOTED of 44 Feb. 25, 1969 J. J. BIALIK ET All CATHODE RAY TUBE BEAM POSITIONING SYSTEM EMPLOYING COMPOSITE SIGNALS Filed July 8, 1965 3,430,095 Sheet Philips B8 95ool S.G. N. S.G. OUT C4 /8 of 44. Feb. 25, 1969 CATHODE RAYJ.TUBE J. BIALIK ETAL 3,430,095 BEAM POSITIONING SYSTEM Filed July 8, 1965 EMPLOYING COMPOSITE SIGNALS RS 2K RS2 4.7 K RS 6.8K RS3 47OK Sheet /? of 44 Feb. 25, 1969 J. J. BALK ETA Filed July 8, 1965 CATHODE RAY TUBE BEAM POSITIONING SYSTEM EMPLOYING COMPOSITE SIGNALS 3,430,095 Sheet 20 of 44 F.G. N.O. NVERTING OUTPUT N "AMPLIFIER" DESIGNATION AMPLIFER NO. AMPL FIER TYPE CODE NSIDE PARENTHESES (WITH N FIG.) (SEE FIG. BELOW) F. G - 8 a 2i ( B WOLTS D.C. - 2 c TERMINAL F B B - 1.8 ) R3 E. E. N. KLOHMS Feb. 25, 1969 CATHODE RAYJ.TUBE J. BAK ET AL 3,430,095 BEAM POSITIONING SYSTEM Filed July 8, 965 EMPLOYING COMPOSITE SIGNALS Sheet at of 44 OUT IN < E. FG NO. "GATE DESIGNATION GATE NO. (WITH IN FIG) IN OUT COMMON LOAD RESSTOR (R) SOURCE VOLTAGE (V) NEGATIVE IN KOHMS Feb. 25, 1969 CATHODE RAYJ.TUBE J. BIALIK ETAL 3,430,095 BEAM POSITIONING SYSTEM Filed July 8, 1965 -- a--use all- - EMPLOYING COMPOSITE SIGNALS - am men summaris man mm Sheet 22 of 44 mm am mains ams Feb. 25, 1969 J, J. BALK ET All- CATHODE RAY TUBE BEAM POSITIONING SYSTEM EMPLOYING COMPOSITE SIGNALS Filed July 8, 1965 3,430,095 Sheet a3 of 44 ------------- -2V - 12V -2V -2V (VERT. AMP .IOOf Q3 5V) 2N3O4. (HOR. AMP. 5OOuf - 9 OV RS5 33KS -90 V RS7 33K -90V -90V -2V - 2V 2V ) RS4CRS6 S-33K 333K RS .5 x D RS2 K Q2 RSO RS3 2N398A SN 2N398A K 47Or DEF. A. M. P. E Feb. 25, 1969 J. J. BALK ET AL EMPLOYING COMPOSITE SIGNALS Filed July 8, 1965 r H. u 3,430,095 CATHODE RAY TUBE BEAM POSITIONING SYSTEM Sheet V - n c) a i (V) Ca N r 24 of 44 J. BALIK ETAL 3,430,095 Feb. 25, 1969 CATHODE RAYJ.TUBE BEAM POSITIONING SYSTEM Filled July 8, 1965 ! 482 + | EMPLOYING COMPOSITE SIGNALS Sheet 25 of 44 s1m8g.2sg14. (E8=21'I_E-C)T•G Feb. 25, 1969 CATHODE RAYJ.TUBE J. BAK ETA. 3,430,095 BEAM Pos ITIONING SYSTEM EMPLOYING COMPOSITE SIGNALS Filed July 8, 1965 Sheet 24 of 44 ENTRY CNTR SOFF esor 6ORS5 16op 6ORS C I 162L2 SOC SORS2 - SW SOC2 6OR2 62.6 SORS9 SORS6 - SW SOR3 62 SORS6 SOC3 SORS3 6V 6Oc4 6OFF3 SOR4 627 6ORSO 6ORS7 -- 6W SOR5 623 6ORS7 SOD3 6ORS3 SO 5 C SORS4 SORS 625 - SW 6OO6 is OFF 4 6ORS 6ORS8 O s lege D - SW 6ORSB SORS4 m SORS5 -- SW 4 Eas (6O) 6OC SOR7 624 Feb. 25, 1969 J. J. BIALIK ET All CATHODE RAY TUBE BEAM POSITIONING SYSTEM EMPLOYING COMPOSITE SIGNALS Filled July 8, 1965 - 2V 6 RS K4 READ HEAD 8 7 63 6L2 165R2, 167B5 16FRS 6 Ol 6RSO 6 N SRS3 3,430,095 Sheet 27 of 44 Feb. 25, 1969 CATHODE RAYJ.TUBE J. BIALIK ETAL 3,430,095 BEAM POSITIONING SYSTEM Filed July 8, 1965 EMPLOYING COMPOSITE SIGNALS Sheet 28 of 44 62R S2 6OR3 62R2 633 62 R3 163LIO 62.2 is OR 623 6OR5 62R4 63 62 R5 632 tes 24 6OR7 62RS 636 tes 25 ISORS 62R7 637 62 R8 634 S2R9 632 62RO 63.5 62.6 SOR2 62R 638 627 6OR4 62R2 639 62R3 163L (62) Feb. 25, 1969 Filed July 8, 1965 J. J. BALK ETAL CATHODE RAY TUBE BEAM POSITIONING SYSTEM EMPLOYING COMPOSITE SIGNALS 3,430,095 Sheet 64. 30 of 44. 64 R 63R), 16784 63R, 16784 S4 FF W S4R2 ab G 67 1642 64R3 703 C64FF2 ab a W Q64FF 4. 645 G. s. s os4FF5 4. 646 a OS 4F6 G 64ff. ab G G - SW EFG 2 (64) Feb. 25, 1969 J. J. BIALIK ET AL Flied July 8, 1965 CATHODE RAY TUBE BEAM POSITIONING SYSTEM EMPLOYING COMPOSITE SIGNALS 3,430,095 Sheet - -2V 3/ of 44 - 2V - 2V 65. 67B3, 166L RS BUS (38T) 65RSS 65RS5 652 RS BUS (38T2) Feb. 25, 1969 CATHODE RAYJ.TUBE J. BALIK ETA3,430,095 BEAM POSITIONING SYSTEM EMPLOYING COMPOSITE SIGNALS Filed July 8, 1965 Sheet 94 of 44 - 2V T - 2V 68RS2 68 N ONE ts2 68RS4 & Shot r 66R3 68R2 V 69 68RSO MI68D2 H 2W -2V 68RS8 68RS 68RS5 leg s 68C3 68R3 72 683 66R 68O 68 C2 68RS6 68RS9 Es (168) Feb. 25, 1969 Filed July 8, 1965 J. J. BALK ET AL CATHODE RAY TUBE BEAM POSITIONING SYSTEM EMPLOYING COMPOSITE SIGNALS 3,430,095 Sheet 35 of 44 (e) --2W 69 RS6 69 RS4 69D 69C2 D 69 68R2 69 RS2 723 69 Ol 69C 69 RS 169RS5 369RST I V769D2 -2V 69 RS8 69RS3 169 Ni ER C EF ONE SHO VI - 69 R 4 (169) Feb. 25, 1969 Filed July 8, 1965 J. J. BIALIK Et AL CATHODE RAY TUBE BEAM POSITIONING SYSTEM EMPLOYING COMPOSITE SIGNALS 3,430,095 Sheet 36 of 44 7 OFF 7OR 733 7OL 7 7 O2 | 67 T2 7O 3 64 R3 7OR4 736 7O R5 72, 173 L4 7OR6 7 L3, 173L5 7O R8 75 7OR9 74 (17O) Feb. 25, 1969 CATHODE RAYJ.TUBE J. Balik Et Al 3,430,095 BEAM POSITIONING SYSTEM Filed July 8, 1965 EMPLOYING COMPOSITE SIGNALS Sheet, fes of 44 72A VERT DEF (CRT - O 22 7R2, 73 R2 723 72R2 VERT DEF (CRT - 9) 72R3 HORIZ DEF (CRT - 6) 724 17 R4, 173 R3 HORIZ DEF (CRT-7) Feb. 25, 1969 Filed July 8, 1965 J. J. BIALIK ET All CATHODE RAY TUBE BEAM POSITIONING SYSTEM EMPLOYING COMPOSITE SIGNALS Sheet 40 of 44 EFES E m 74 (74) 74C3 74R 175LI 3OV RMS 2O MA 74r2 752 74R3 75.3 9 O V RMS SO MA 4R 4 754 742 AC NE 74 RS2 7W 74 RS CRT - 2 7.43 AC NE re- 7OO V RMS 3 MA A74 D3 ( M74D14 74 C I 4RS. CRT - A 74RS 4C 4 74RS22 74RS23 74 RS2 74 RS9 74 R7 2 RESISTOR - DODE PARS EN SERIES CRT-1, CRT-3 e 6.3 V FLAMEN 74 R CRT - 2 Feb. 25, 1969 Filed July 8, 1965 75 L J. J. BALK ET AL. CATHODE RAY TUBE BEAM POSITIONING SYSTEM EMPLOYING COMPOSITE SIGNALS 3,430,095 Sheet All of 44 75RS 752 75RS8 - 9 OV 75.3 75RS3 75RSO E. G. E. (75) 75R4 CRT - 8 - Feb. 25, 1969 J. J. BALK ET AL CATHODE RAY TUBE BEAM POSITIONING SYSTEM EMPLOYING COMPOSITE SIGNALS Filed July 8, 1965 Vr H d r e o Cd A. a) 5aa. VO N - u l 8 N l V L L- - S. l o O if f f f & Sd SC S o d N d d 3,430,095 Sheet 42 of 44 Feb. 25, 1969 CATHODE RAYJ.TUBE J. BALK ETA 3,430,095 BEAM POSITIONING SYSTEM EMPLOYING COMPOSITE SIGNALS Sheet 901 Feb. 25, 1969 CATHODE RAYJ.TUBE J. Balik Et Al 3,430,095 BEAM POSITIONING SYSTEM Filled July 8, 1965 EMPLOYING COMPOSITE SIGNALS Sheet 44 of 44 YPCA, CHARACTER RASTER / 4 -les STROKE (SEGMENT) NO, 3- 5 3 2 -- O -- 4 2 O -- 6 RELATIVE WEGHTING - O 2. fill E a SROKE ORIGN FLP-FLOP OUTPUTS HORIZ. STROKE WER. SROKE HORZ, STROKE STROKE NO. WERT. COORONAE HORIZ. COORD NATE RELAWE WEIGHTING RELATIVE WEIGHTING (UNTS OF VOLTAGE ) (UNTS OF VOLTAGE) United States Patent Office 1. 3,430,095 Jack J. Bialik, Saint Germain-en-Laye, France, and Dale P. Masher, Menlo Park, and William W. Stevens, Palo Alto, Calif., assignors to Friden, Inc., San Leandro, ABSTRACT OF THE DISCLOSURE Patented Feb. 25, 1969 2 solution of the problem of providing a novel character display signal generating apparatus and method charac terized by low cost, compactness and ease of maintenance that the present invention is directed. It is therefore an object of the present invention to provide character display signal generating apparatus and methods which are substantially free from the need for special components that characterize present character CATHODE RAY TUBE BEAM POSITONING SYS TEM EMPLOYING COMPOSTE SIGNALS Calif., a corporation of Delaware Filed July 8, 1965, Ser. No. 470,370 U.S. C. 315-18 16 Claims Int. C. H01j29/72 3,430,095 O display signal generators. It is another object of the instant invention to provide character display signal generators employing noncritical circuitry throughout. It is a further object of the instant invention to pro vide methods of generating character display signals, There is disclosed an apparatus for and method of which methods may be carried out without the use of controlling the position of a cathode ray tube beam used 15 critical apparatus. in character display systems. The beam position is con It is yet another object of the instant invention to trolled by producing both horizontal and vertical deflec provide a method of generating predetermined symbols tion signals, each deflection signal being produced by upon the faces of fugitive pattern tracing display devices, mixing a beam position signal and a stroke position sig which method may be practiced without the employment nal. Provision is made for adding an oscillatory signal 20 of critical circuits or components, or circuits or com to each stroke position signal and for inhibiting the ponents specially adapted only to the practice of that oscillatory signal in response to the condition of a bi stable device. method. It is still another object of the instant invention to provide apparatus and methods for generating character This invention relates to improved character display display signals of minimum band width, thereby ensuring signal generator apparatus and to improved methods for that said apparatus will be characterized by minimum generating character display signals. Character display criticality, and maximum ease of maintenance. generators are well known in the prior art, being described It is a yet further object of this invention to provide in United States Patent No. 2,762,862 to Bliss, in United 30 a deflection system responsive to a binary counter type States Patent No. 2,766,444 to Sheftelman, in United Segment generator system. States Patent No. 2,875,951 to Schreiner, in United States It is a yet further object of this invention to provide Patent No. 3,090,041 to Dell, and in United States Patent a voltage weighting circuit responsive to the count of a No. 2,834,831 to Giffard. A character display signal gen segment generator for providing proper input voltages erator, then, may be defined as a device capable of pro 3 5 to vertical and horizontal amplifiers of a display. ducing a plurality of synchronized electrical signals It is a still further object of this invention to provide which, when applied to the proper input terminals of a an oscillator controlled varying signal to the inputs of cathode ray tube, an oscilloscope, or the like, cause one vertical and horizontal amplifiers for providing line stroke or more symbols to be displaced thereupon; said symbols Segments defining characters to be displayed on a cathode and their configuration, e.g., in rows and columns, being 40 ray tube. selectable by input signals, keyboard actuation, or the It is a yet further object of this invention to provide like. More particularly, the present invention relates to a pair of input signals to a deflection amplifier of a character display signal generating apparatus and methods CRT display system composed of a first predetermined which are free from the necessity of employing the costly, Weighted voltage and a second varying voltage, the combi specialized and critical components and subcircuits which nation thereof providing a line scan at a predetermined -mutumn characterize the devices of the prior art. position on a cathode ray display tube. It is a yet further object of this invention to provide patents, many of the devices of the prior art were charac a deflection system responsive to a binary device for terized by the employment of specialized, costly and criti forming a vertical or horizontal stroke depending upon cal components and circuitry. 50 the condition of said binary device. The device of the Bliss patent, for instance, employs It is a yet further object of this invention to provide a a flying-spot cathode ray tube scanner, or a kinescope, pair of input signals to a deflection amplifier, one such within the signal generator itself, in addition to the cath input signal being a varying voltage and the second being ode ray tube employed to display the symbols resulting a ramp function for providing a deflection signal. from the generated signals. Other objects of the instant invention will in part be 55 Giffard employs a tube of the class known as mono obvious, and will in part appear hereinafter. Scopes, or phasmajectors, and also a Williams-type stor The instant invention, accordingly, comprises the sev age tube, both within the signal generator, in addition eral steps and the relation of one or more of such steps to the cathode ray display tube. to each of the others, and the apparatus embodying fea The device of Sheftelman is also characterized by the tures of construction, combinations of elements, and ar employment of costly, specialized and critical compon 60 rangements of parts which are adapted to effect such steps, ents, viz., a plurality of closely-matched delay lines, each all of which are exemplified in the following detailed dis having a plurality of critically located taps. As can be seen from the afore-mentioned United States closure. The Scope of the instant invention will be indi It will be clear from the above, then, that one of the cated in the claims. principal problems in the character display signal gen 65 For a fuller understanding of the nature and objects erating apparatus of the prior art is the high cost, com of the invention, reference should be had to the following plexity and criticality of certain components and circuits detailed description, taken in conjunction with the accom found therein. As is well known to those skilled in the panying drawings, in which: art, these characteristic features of the devices of the FIGURE 1A is a block diagram of the display device prior art render them applicable only to highly specialized 0 according to the invention. FIGURE 1 is a pictorial description of the output sig maintenance are not primary considerations. It is to the nals from track 1, track 2 and track 6 read head circuits applications, wherein cost, compactness and ease of 3,430,095 3 4. of the magnetic drum including a reference scale desig is coupled through inhibit device 12 and combined with nated T. the output of weighted signal generator 14 in vertical FIGURE 2 is a pictorial description of track 1 of the mixer 16. The output of mixer 16, along with the signal magnetic drum. from vertical staircase generator 18, are coupled to verti FIGURES 3 and 4 are pictorial explanations of the cal amplifier 19 which provides the vertical deflection definition of the signal time periods. signal. A second output from oscillatory signal generator FIGURE 5 is a pictorial description of the registers of 10 is coupled through inhibit device 20 and combined track 4 of the magnetic drum and the relationship of the with the output of weighted signal generator 22 in hori read head therefore. zontal mixer 24. The output of mixer 24, along with FIGURE 6 is a description of the timing signals ob O the signal from horizontal staircase generator 26, are cou tained from the timing circuits and the levels of these pled to horizontal amplifier 28 which provides the hori timing signals during the various time periods of opera Zontal deflection signal. The vertical and horizontal deflec tion. tion circuits, including enable means 30, are under the FIGURE 7 is a symbolic diagram of a flip flop as used control of timing and control unit 32. All the above ele in the logic diagrams of FIGURES 10 to 17. 5 ments are described in greater detail below. FIGURE 8 is a description of symbols utilized in the TIMING description of the logic diagram of FIGURES 10 to 17. FIGURE 9 is a symbolic diagram of a one shot as used Since the operation of this display device is primarily in the logic diagrams of FIGURES 10 to 17. dependent upon the timing therein, it is initially essential FIGURES 10 to 17 comprise a logic diagram of the 20 to understand the operation of the timing pulse generator system and, subsequently, the timing required for the per display device in accordance with the present invention. FIGURE 18 is a symbolic diagram of a flip flop as used formance of each operation of the display. The basic in the circuit diagram of FIGURES42 to 60. timing signals utilized in the display in accordance with FIGURE 19 is a symbolic diagram of a one shot as the present invention are obtained from the magnetic used in the circuit diagram of FIGURES 42 to 60. 25 tracks located on the drum of a calculator such as de FIGURE 20 is a circuit diagram of a type I flip flop. scribed in the application of Ragen, Ser. No. 398,902 filed FIGURE 21 is a symbolic diagram of a type I flip flop. Sept. 24, 1964. This subject matter is incorporated herein FIGURE 22 is a circuit diagram of a type II flip flop. by reference. FIGURE 23 is a symbolic diagram of a type II flip flop. FIGURE 1 sets forth the output of the read heads of FIGURE 24 is a circuit diagram of a type III flip flop. 30 tracks 1, 2 and 6 of the drum indicated as TK1, TK2 and FIGURE 25 is a symbolic diagram of a type III flip TK6, respectively. It is assumed that the drum is rotating flop. toward the left as indicated by the arrow in FIGURE 2. FIGURES 26 and 27 describe the circuit of certain one Track 1 produces H. pulses, track 2 produces R pulses and shots used in the circuit diagram of FIGURES 42 to 60. track 6 produces dipslay pulses. Each pulse in FIGURE 1 FIGURE 28 is a circuit diagram of a type I one shot. 35 represents a change in the state of the magentic materal FIGURE 29 is a symbolic diagram of a type I one shot. on the drum, this change being sensed by the reading heads FIGURE 30 is a circuit diagram of a type V one shot. associated with the drum to produce a bit pulse. FIGURE 31 is a symbolic diagram of a type V one Track 1 produces H pulses, these pulses comprising shot. two individual pulses per revolution of the magnetic FIGURE 32 is a circuit diagram of a type VI one shot. 40 drum, these pulse bits being closely spaced on the drum as FIGURE 33 is a symbolic diagram of a type VI one shown in FIGURE 2, The short space of time between shot. these H pulses lettered H1 and H2 is referred to as "dead FIGURES 34 and 35 describe the circuit of the in time” since no operations of the display circuit take place verters used in the circuit diagram of FIGURES 42 to 60. during this time period. Track 2 produces 101 equally FIGURES 36 and 37 describe the circuit of certain spaced pairs of timing pulses positioned in time from gating circuits used in the circuit diagram of FIGURES TOB to T100C. These pulses are set forth in FIGURES3 42 to 60. and 4 at the B and C times. It will be noted that B time FIGURE 38 is a circuit diagram of the read head cir occurs one half bit time prior to A time (the A times cuit used in the circuit diagram of FIGURES 42 to 60. being equally spaced between B and C times) and the C FIGURE 39 is a symbolic diagram of the read head time corresponding to the second bit of the R bit pair circuit of FIGURE 38. 50 occurring one half bit time after an A time. FIGURE 40 is a circuit diagram of the vertical and Track 6 produces display pulses, these pulses com horizontal deflection amplifiers used in the circuit diagram prising seven spaced pulses appearing in the period slightly of FIGURES 42 to 60. after a C time and before the following B time. There FIGURE 41 is a symbolic diagram of the vertical and fore, seven negative pulses will appear in the period just 55 after T0C and before T1B of FIGURE 1. Also, seven such horizontal deflection amplifiers of FIGURE 40. FIGURES 42 to 60 comprise a circuit diagram of the pulses will appear in the time period between T1C and display in accordance with the present invention. T2B and so on for each of the one hundred time periods FIGURE 61 is a timing diagram of the operation of reprSented in FIGURE 1. These pulses are shown in more the segment flip flops of the display unit and a description deai in FIGURES 62 and 63. of the timing signals obtained from the magnetic drum 60 In Summary, it can therefore be seen that in the opera track 6 read head circuit. tion of the drum, first an H1 pulse will appear, then FIGURE 62 is a pictorial description of the output there will be a short period of "dead time' when no op signal of the vertical staircase generator and the hori erations occur. There will then be a first R pulse at time Zontal staircase generator of the display device. TOB (FIGURE 1) then, one bit later at TOC time, an FIGURE 63 is a timing diagram of the unblanking cir 65 H2 pulse and a second R pulse at time T0C. This is fol cuitry of the display system. lowed by 7 bit pulses occurring via track 6, these 7 bit FIGURE 64 is a diagram of a typical character raster pulses occurring in the time period from just after the TOC produced on the face of the cathode ray tube of the dis time until just prior to the next following T1B time. The play unit. above time periods are set forth on the exemplary time FIGURE 65 is a table of the weighting of the output 70 scale T of FIGURE 1. This sequence will continue for signals of the segment flip flops of the display unit. one hundred such pulse groups about the track until GENERAL SYSTEM time T100B has been reached, whereupon an H1 pulse and an R pulse are received and then a "dead time' FIGURE 1A shows the display device in block diagram returns until the following R pulse which occurs one bit form. A first signal from oscillatory signal generator 10 75 time prior to the next H2 pulse. 5 3,430,095 Referring now to FIGURE 5, the track therein is labelled track 4 of the magnetic drum and includes a space marked H which corresponds to the space between position H1 and H2 of track 2 or the "dead time.” This space is not restricted as to size. Immediately upon oc currence of the H2 signal, the following track space, which corresponds to the portion of track 4 corresponding to times TOC to T1A of track T in FIGURE 1, is the area in which the least significant digit of a number to be stored in the temporary storage register No. 1 (T1) will be stored by the reading therein of a number of bits equal to the value of the number to be stored therein. As shown, 6 signal commences at time TOC by going, at that time, from a positive voltage level to a negative voltage level and remaining in this negative state until the next follow ing B time whereupon this signal reverts to its positive voltage level until the next following C time whereupon this signal again reverts to its negative level. This cycle commences for 100 T periods. Similarly, the positive volt age level RS. signal on bus 138T2 is identical in all re spects to the RS. signal on bus 138T3 except that this O signal goes from a negative voltage level to a positive voltage level at the identical times that the RS. signal on bus 138T3 goes from a positive voltage level to a negative voltage level and vice versa. These RS signals are obtained by reading the signals the number “4” is stored therein. The portion of scale T corresponding to the time period from time T1A to time T2A, corresponds to the portion of track 4 labelled 15 from track 2 as shown in FIGURE 1 with the track 2 T2, this portion of track 4 being similar to register T1 and reading head 138RA (FIGURE 43), these signals being being utilized as a second temporary storage register. The inverted in the inverter 138A1 and transferred to the com portion of track 4 corresponding to track T in time T2A plement inputs of the RS flip flop. 138FF1. Upon reading to T3A is referred to as the accumulator (ACC) whereas the signal on track 2 corresponding to the B time of FIG the portion of track 4 corresponding to times T3A to 20 URES 3 and 4, the RS flip flop. 138FF1 is set by a posi tive-going voltage pulse thereto, and provides a negative T4A is referred to as the entry register (ENT). Each of track portions T1, T2, accumulator register and entry voltage level output on RS bus 138T2. Simultaneously, a register indicated as 1/1, 1/2, 1/3 and 1/4, repectively, positive voltage level signal is applied to the RS bus 138T1 will store the least significant digit of a number to be through inverter 138A4. When the following bit pulse stored in the entire temporary register T1 or T2, ac taken from track 2, which corresponds to the time C of cumulator register or entry register. During subsequent FIGURES 3 and 4, is received from track 2 read head, this signal will provide a second positive-going voltage times as referred to in the T scale of FIGURE 1, track 4 will continue to include space for more significant digits level and reset the RS flip flop. Thereby, the voltage of the storage register T1, storage register T2, accumula levels on the RS buses 138T1 and 138T2 are inverted to tor register and entry register until at time T100A there 30 provide significant voltage levels on these buses only in will have been 25 of each of these registers. The registers the time period between a C time and the following B set forth in track 4, as indicated supra, are referred to by time on the drum. utilization of two numbers located in each register block, W TIMING SIGNAL the top number of which indicates the significance of the The pulses on bus 138T3 (FIGURE 43) are transferred digit and the bottom number of which indicates the par ticular register, i.e., temporary storage register T1 (1), through a diode 137D1 (FIGURE 42), a time delay one temporary storage register T2 (2), accumulator register shot 137N1, and the inverter 137A1 to the complement (3) or entry register (4). A read head is positioned ad inputs of the RA flip flop. 137FF2. This RA flip flop, along jacent track 4 for reading therefrom. with the RB flip flop 137FF1, comprises a binary counter Referring now to FIGURE 6, there is shown a timing 40 with four states. Therefore, for each positive-going tran diagram of the various timing signals provided by the sition on the RS flip flop RS. bus, there will be a corre timing circuitry of the display device. The T scale indi sponding change in state of the counter composed of the cates the various time periods from TOC to T100A, identi RA and RB flip flops. It can be seen that the RA and RB cal to the T scale of FIGURE . flip flops are initially both in the reset condition due to a H. TIMING SIGNALS 45 positive-going transition resetting signal applied on the H. bus 137T5. This positive voltage level on the bus 137T5 disables the one shot 137N1 through diode 137D3 by holding the one shot input at a positive voltage level. should be noted that the H flip flop. 138FF2 and the then shifts back to the negative voltage level. This signal 50 RSItflip flop 138FF1 are synchronized by the positive volt is indicated as H. It will be noted that the portion of the age level on bus 137T5, which level is applied through drum between the H1 and the following H2 signal is the the diode 137D2 to the RS. bus 138T3, thereby setting the “dead time' indicated in FIGURE 2, RS flip flop for time synchronization with the H flip flop. This H signal is provided by the circuitry set forth in When the voltage level on the H bus 137T5 then goes to FIGURE 43, wherein the H2 indication on track 1 on a negative voltage level, the RA, RB and RS flip flops and the drum is sensed by track 1 read head 138RA2 and 55 the one shot 137N1 are unlocked. transferred through inverters 138A2 and 138A3 to the in Concurrently with the unlocking of the RS, RA and RB The H signal shifts from the negative voltage level at time TOC to the positive voltage level and remains at the positive voltage level until time T100C when this signal put terminals of the H flip flop 138FF2. The input signal flip flops and the one shot 137N1, an input signal to the provided by inverter 138A2 is a positive-going pulse, also RS flip flop. 138FF1 resets this flip flop, this resetting hav the signal provided by inverter 138A3 is a positive-going 60 ing no effect on the timing circuitry. At time T1B, a posi pulse. The positive-going pulse produced by inverter tive-going transition to the complement input of the RS 138A2 is applied to the input of the flip flop 138FF2 and flip flop 138FF1 sets this flip flop and provides a positive sets this flip flop, thereby providing negative voltage level going transition on the RS. output bus thereof. This posi signal on the H. bus 138T4. This signal will appear and transition is delayed in the one shot 137N1, the will remain on bus 138T4 until the next following H2 65 tive-going negative-going output therefrom being inverted by the pulse which will reset the H flip flop. 138FF2 and invert inverter 137A1 and setting the RA flip flop. 137FF2 at the voltage level on this bus. The output on the bus 138T4 TA. At time period TC, a positive-going transition passes through the emitter follower 137C1 and is inverted time to the input of the RS flip flop 138FF1 will reset this flip by the inverter 137A2 to provide an H. signal on the out flop, producing a negative level on the RS. bus, this nega put bus 137T5. tive level having no effect as before. This procedure is 70 RS TIMING SIGNALS continued for each T time to thereby step the counter composed of the RA and RB flip flops and provide various The negative voltage level RS. signal is obtained on bus significant voltage levels on the buses 137T through 138T3 100 times during each revolution of the drum from 137 T4 in accordance with the condition of the RA and time TOC to T1B, T1C to T2B . . . T99C to T100B as indicated in FIGURE 6. It will be noted that the first RS. 75 RB flip flops. The voltage levels on these buses 137T1 3,430,095 7 8 through 137T4 will aid in providing the W timing signals cated on the flip flop of FIGURE 7 at terminals 14, 15 as will be described hereinbelow. and 21 thereof. These three symbols always occur to The RA and RB signals are utilized to provide the W1 gether and are defined to indicate that the impressing of a signal on the bus 139R4 in the display. As shown in positive-going voltage transition on terminal 14 will trans FIGURE 6, the W1 signal remains in its negative volt fer the voltages on the terminals 15 and 21 respectively age level condition except during times indicated as T1, to the terminals 12 and 11. That is, if a negative voltage i.e., the time period between times T0C and T1A, the is located on terminal 21 and a positive voltage is located time period between times T4A and TSA, . . . . It will on terminal 15, the application of a positive-going transi be seen that this W1 pulse is provided at every fourth tion on terminal 14 will set the flip flop, or, in other time period beginning with time TOC. It should also be 10 words, place a negative voltage level at the FF. output noted that the W1 pulse extends in time from a first A terminal and a positive voltage level at the FF. output time to the next succeeding A time as shown in FIGURE terminal thereof. Of course, if the flip flop is already set, 3 for all time periods except T0. This extended range is no change will take place. Also, if the terminals 15 and provided by the time delay obtained in the one shot 21 each have a negative signal thereon, no change will 137N1 since the RA and RB counter advances during the take place. positive-going portion of the RS signal on bus 138T3. The symbol on terminals 17 and 20 indicates that the It can now be seen that, in the time period between occurence of a positive-going transition on one of the time TOC to T1A, the H bus 139L9 will have a significant said terminals will reset the flip flop. The symbol on negative voltage level signal thereon as explained supra terminals 19 and 16 indicate that the occurrence of a and shown in FIGURE 6. Also, since at time TOC the 20 positive-going transition on one of the said terminals RA and RB flip flops 137FF1 and 137FF2 will both be in will set the flip flop. The symbol on terminal 18 indicates the reset state and thereby provide a negative voltage that the occurence of a positive-going transition on this level output signal on the RA bus 137T4 and 139L10 terminal will complement the flip flop, i.e., change the and a negative voltage level signal on the RB bus 137T3 state of the flip flop from the set condition to the reset and 139L11. Accordingly, at this time and the AND gate condition or from the reset condition to the set condition, 139G4 is enabled and provides a negative voltage output depending upon the initial condition of the flip flop. therefrom, this negative voltage level being inverted by The symbol on terminal 10 of the flip flop indicates inverter 139A4 to provide a positive voltage level output that the placement of a positive voltage level thereon on the W bus 139R4. will reset the flip flop. The symbol on terminal 13 of the At time T1B, the RS flip flop is set and applies a delayed 30 flip flop indicates that the placement of a positive voltage positive-going signal through the one shot 137N1 to set level thereon will set the flip flop. The above symbols and the RA flip flop 137FF2 at time T1A. Accordingly, at this the other symbols set forth in FIGURE 8 can be used to time, the RB bus 137T3 will remain in its negative voltage depict each of the operations of the flip flops utilized in condition whereas, the RA bus 137T4 and 139L10 have display to be described hereinafter. now changed from a negative voltage level condition to theThe symbols set forth in FIGURE 8 are also utilized a poistive voltage level condition, thereby disenabling the to depict the various gate circuits utilized in the present AND gate 139G4. invention. The gate circuits set forth in FIGURES 10 The next positive-going transition on the bus 138T3, to 17 are labelled as either AND gates or OR gates. The as before, will again change the count of the RA and symbols at the input and output terminals are defined RB flip flops by “1” and, accordingly, the RAbuses 137T4 40 to indicate the type of input and output terminals are de and 139L10 will be at a negative voltage level, and the fined to indicate the type of input required to provide the RB buses 137T3 and 139L11 will be at a positive voltage designated output. That is, assuming an AND gate, if level. all input terminals thereto are provided with the negative At the next positive-going transition of the RS signal level symbol of FIGURE.8 and the output terminal there on bus 1388T3, as before, the counter composed of flip of is provided with the positive level symbol of FIGURE 45 flops 137FF2 and 137FF1 will again change in count 8, the symbology states that if a neg