Historical Document · 1968
US Patent 3,388,384: Zero Suppression Circuit (General Micro-electronics, Victor 3900)
The Victor 3900's leading-zero suppression for its CRT display.
Historical Document · 1968
The Victor 3900's leading-zero suppression for its CRT display.
June 1, 1968 H, Z. BOGERT ETAL 3 388,384 ZERO SUFFRESSION CIRCUIT Filed March 8, 1966 5 Sheets-Sheet li June 11, 1968 3,388 384 H. Z. BOGERT ETA EERO SUPPRESSION CIRCUIT Filed March 8, 1966 5 Sheets-Sheet 2 OST !|† | | | !| 69 69 1(J||Å9E-HO181A0B INVENTORS. HOWARD Z., BOGERT ALAN E. POUND GEORGE E. AVERY BY ???? ??? ATTORNEY June 11, 1968 H. Z. BOGERT ETA 3,388,384 ZERO SUPPRESSION CIRCUIT Filed March 8, 1966 5. Sheets-Sheet 3 FIRST CYCLE ZERO SUPPRESSION ACT VE BT S. GNAL O COOED SIGNAL t ? X DI GIT MARKER P DGTS MARKER LAST BIT OF DATA STREAM SERIAL DATA AT So SERIAL DATA AT S SERIAL DATA AT sa SERIA DATA AT S? TERMINATE ZERO SUPPRESSION ???d U O3 s INVENTORS. FG.2 EgyipéR85Rt BY GEORGE E. AVERY M. hJ? ATTORNEY June 11, 1968 H. Z. BOG ERT ETAL- 3,388,384 ZERO SUPPRESSION CIRCUIT Filed March 8, 1966 5. Sheets-Sheet 4 SECOND CYCLE THIRD CYCLE P. D. D2D3D4 * Pe. D D2 D3 D4 x P D. De Os D4 X e D. D2O3 4 x ?????????????? BLANK 5 4 O OBANK7 2 O 3BLANK 3 BLANK ??n nerv? 5 4 O BLANK 7 2 O 3 BLANK 3 BANK BLANK 3 5 4 O OBLANK 7 2 O 3 BLANK S 5 4 O BLANK 7 2 O 3 BLANK BLAN ? 3 5 4. ? ? BLANK SK 3 5 4. ? B lK B l K 7 2 ? 3 B l K 8L K 3 5 4. BLAN K B K 7 2 ? 3. B L? INVENTORS. F G.2-O HOWARD Z. 806ERT ALAN E. POUND GEORGE E. AVERY BY ????? M.ATTORNEY 4-lawa June 11, 1968 H. Z. BOGERT ETA. 3,388,384 ZERO SUFPRESSION CIRCUIT Filed March 8, 1966 5 Sheets-Sheet 5 FOURTH CYCLE D. D2 D3, D4 X e D. D2 D C x P O D2 D3O4 x 1 Pe D 02 5 4 BLANKBLANK 7 2 O 3 BLANK 3 5 4BLANKBLANK7 2 O 3 3 5 4 B AN K B AN ? 3 BLAN K 3 5 4. BLA N K BLA N K 7 s BANK 7 2 EANK BANK 2 ? BK BLK 3 5 4 ELK ELKBLK 7 2 O 3 ELK BK 3 ?L 5 4 SLK 8 K 7 2 4Šieu# 2 O 3 BK | BK 3 5 4 BLK BUKKY 2 RS3. FG 2 b A HowARS256Ert ALAN E. POUND GEORGE E. AVERY ?? A. J(ATORNEY United States Patent Office 3,388,384 ZERO SUPPRESSION CIRCUIT Howard Z. Bogert, Cupertino, Alan E. Pound, Sunnyvale, and George E. Avery, Saratoga, Calif., assignors to General Micro-Electronics Inc., Santa Clara, Calif., a corporation of Delaware Filed Mar. 8, 1966, Ser. No. 532,659 15 Claims. (Cl. 340-172.5) The present invention relates in general to electronic calculators, and more particularly to a zero suppression circuit for an electronic calculator. Heretofore, electronic calculators displayed a prede 3,388,384 Patented June 11, 1968 2 significant digit, are examined simultaneously. If the most significant digit is detected as a digit other than a Zero, then there is no zero to be suppressed. Hence, a ter minate suppression signal is generated and no further action takes place with respect to this particular data word. On the other hand, should the most significant digit be a Zero, it is then coded as a blank, and the completed data word is again recirculated through the zero sup 0 pression circuit 10 with the least significant digit first. The most significant digit, which is now coded as a blank, is followed by the adjacent successive digit, which is a less significant digit. As the serial data word is advanced through the zero suppression circuit 10 least significant termined number of digits in scanning a horizontal dis play line regardless of whether all of the digits, such as 5 digit first, the most significant digit is examined with the less significant adjacent digit. With the most significant the zero digits to the left of the most significant non-zero digit coded as a blank and with the adjacent less significant digit of an integer, were significant in the displayed num digit coded as a zero simultaneously, a signal is generated ber. which codes the less significant digit as a blank after a An object of the present invention is to provide a Zero suppression circuit for an electronic calculator, 20 delay in time of one digit. If the less significant digit is a non-zero digit, a terminate suppression signal is gener whereby insignificant ciphers to the left of the most ated. significant non-zero digit are not displayed in an integer Thus, the criterion for the zero suppression is a more produced by the electronic calculator. significant blank code and an adjacent less significant zero Another object of the present invention is to provide a zero suppression circuit for an electronic calculator that 25 code. If the blank code is adjacent to a less significant non zero code in succession, then Zero suppression is termi blanks out serially unwanted zeros in the data stream. nated. Should the examination for non-significant Zeros Another object of the present invention is to provide a continue, the data word is recirculated with the more circuit for examining a serial data word, or a series of significant digit coded as a blank and adjacent to the next data words, containing numerical data with insignificant zeros in the words and for removing all zeros in the word 30 succeeding digit, which is the less significant digit. As the serial data word is again recirculated through the Zero or words that are insignificant by inserting a blanking suppression circuit 10, it examines all digits in succession code or signal in their place to prevent their display on a two adjacent digits at a time during each recirculation cathode ray tube or other indicating device. of the data word. The more significant digit is examined Other and further objects and advantages of the pres ent invention will be apparent to one skilled in the art 35 to determine whether it is coded as a blank and the less significant digit is examined to determine whether it is from the following description taken in conjunction with coded as a zero digit. Should both conditions exist si the accompanying drawings, in which: multaneously, a blank signal is generated which codes the FIGS. 1 and 1-a, with FIG. 1-a below FIG. 1, are a less significant digit as a blank after a delay in time of circuit diagram of the zero suppression circuit of the pres one digit. ent invention illustrated with data processing circuits and The data word is continuously recirculated through the a display device of an electronic calculator. zero suppression circuit 10 and the procedure is re FIGS. 2, 2-a and 2-b, with FIG. 2-a to the right of peated for each recirculation of the data word until a FIG. 2 and FIG. 2-b to the right of FIG. 2.-a, are a graphical illustration of the signals employed in or pro 45 non-zero digit is detected adjacent to a more significant blank or when the end of the word is reached. Thus, if the duced by the operation of the zero suppression circuit in data word is 0.0245, the sequence is as follows with "B" a predetermined series of data words. denoting a blank code: FIG. 3 is a diagrammatic illustration of a total data stream format. Word time: Data word In the zero suppression circuit 10 of the present inven 50 Before start ------------------------ 000245 tion, a completed data word, or data words, with nu 1 ---------------------------------B0245 merical data therein is advanced through the Zero Sup 2--------------------- ? ?-------- - ?--?? BB0245 pression circuit 10 least significant digit first. As viewed 3 --------------------------------- BBB245 on a display, the digit on the extreme right-hand side of --------------------------------- 1BBB245 a horizontally disposed integer or word is considered to 55 i Generate Terminate Suppression Signal. be the least significant digit. Any digit to the left of the If the data stream consists of more than one data word next adjacent digit is considered herein to be the more significant digit. Conversely, any digit to the right of the the terminate suppression signal will not be generated next adjacent digit in a horizontally disposed integer or until all data words have had all their insignificant zeros word is considered herein to be the less significant digit. 60 suppressed. Illustrated in FIGS. 1 and 1-a is the zero suppression Each completed data word is followed by an extra digit, circuit 10 of the present invention for an electronic cal which is coded as a zero and is not part of the data word. The zero suppression circuit 10 examines all digits in culator 20 that serves to blank out serially in a horizontal scanning line insignificant ciphers to the left of the most succession two adjacent digits at a time starting with the least significant digit. This occurs once during each cir 65 significant non-zero digit in a data word or a series of culation of the data word being examined. However, the data words, to prevent the display of the insignificant suppression of insignificant zeros, if any, will be in the ciphers on a cathode ray tube 21 or other display device of the electronic calculator 20. order of the more significant digit preceding the less The electronic calculator 20 may be a conventional significant digit. During the first examination in the test ing of the completed data word, the extra digit is coded 70 and well-known electronic calculator which includes as a blank. During the second circulation cycle, the extra digit, which is now coded as a blank, and the most conventional data processing cricuits or digital computer circuits 22. The data processing circuits 22 are connected 3,388,384 3 4 to the horizontal and vertical deflecting plates of the delay circuit 32 and the first binary coded digit signal cathode ray tube 21 to form an integer or data word advances simultaneously to the 1 digit delay circuit 33. comprising a plurality of decimal digits along a horizontal At the time the serial data storage circuit 30 feeds the path on the cathode ray tube 21. The data processing cir fourth binary coded digit signal representing the fourth cuits 22 are continuously producing decimal digits under decimal digit to the 1 digit delay circuits 31, the third the control of an operator. However, the integer or data binary coded digit signal advances simultaneously to the word is not produced on the cathode ray tube until the 1 digit delay circuit 32, the second binary coded digit completion of the zero suppression action. signal advances simultaneously to the 1 digit delay cir The zero suppression circuit 10 of the present invention cuit 33 and the first binary coded digit signal is trans recognizes the blanking code and through its connection () mitted simultaneously from the 1 digit delay circuit 33 over a conductor 34. with the control grid of the cathode ray tube 21 selectively blanks out through a blanking amplifier 11 the insigni From the foregoing, it is to be observed that binary ficant ciphers to the left of the most significant non-zero coded digit signals are transmitted less significant digit digit in the integers or data words along the horizontal first successively and sequentially from the serial data scanning path. While the preferred embodiment of the 5 storage circuit 30 and advance serially and successively present invention makes reference to a cathode ray tube, through the 1 digit delay circuits 31, 32 and 33 in the it is apparent that any suitable calculator display device consecutive order named. may also be employed. Connected to the output of the 1 digit delay circuit As shown in FIG. 1, the zero suppression circuit 10 31 is a comparator 40 for testing for a blank coded digit comprises a serial data storage circuit 30, which may be 20 signal. The comparator 40 comprises a conventional and a well-known clock synchronous, binary coded, memory gale logic circuit, which has an input thereof connected circuit, connected to the output of the data processing to the output of the 1 digit delay circuit 31. The and-gate circuits 22. logic circuit of the comparator 40 checks a binary coded The memory device 30 may be of the type described in digit signal at the terminal So for an existing blank code. detail in the pending patent application by Robert H. 25 Should the comparator 40 detect a blank code signal Norman el al., Ser. No. 385,444, filed on July 27, 1964, from the output of the 1 digit delay circuit 31, it produces for Memory Device. The assignee of the present applica in its output a logic zero signal for the entire digit time. tion is also the assignee of the aforesaid application filed On the other hand, should the and-gate logic circuit not by Robert H. Norman et al. detect a blank coded signal, its output produces a logic 1 Although the display of the integer or word on the 30 signal for at least 1 bit time during the digit time. cathode ray tube 21 is in decimal digits, the output of As previously described, the last digit of any word or the data processing circuits 22 fed to the serial data stor integer, which is the last digit examined for each data age circuit 30 is in the form of binary coded decimal word transmitted by the serial data storage circuit 30, digits. More specifically, each decimal digit number is which is considered herein as the extra digit, is coded as represented by four binary bits. In the exemplary em 35 a blank. It is not part of the data word. Toward this bodiment, the digits are in the form of the excess three end, a series of timing pulses herein referred to as X binary code. Thus, four consecutive binary bits advance digit marker (FIGS. 1 and 2) are transmitted to a con least significant bit first through the Serial data storage ventional inverter circuit 41 to indicate the end of a word circuit 30 to represent one decimal digit and each integer or integer. The X digit marker is in the logic 1 state only or data word along the horizontal scanning line of the 40 during the time when an X digit is being advanced from cathode ray tube 21 is a plurality of decimal digits. 1 digit delay circuit 32 to 1 digit delay circuit 33. In Accordingly, advancing continuously through the serial turn, the output of the inverter circuit 41 is connected data storage circuit 30 in clock synchronism are binary to an input of the comparator 40 to form a blank coded coded signals. In the exemplary embodiment, there are signal for the extra digit so that the output of the com six words with each word containing twenty data digits, 45 parator 40 for the extra digit or the end of a word is a an extra digit and three additional non-data digits. Hence, logic 0 signal for the entire digit. Thus, the last digit of the data processing circuits 22 are continuously producing any word transmitted to the 1 digit delay circuit 31 by signals representing binary coded words and the serial the serial data storage circuit 30 is treated as a blank data storage circuit 30 advances continuously and suc by the comparator 40 in response to the X digit marker cessively signals representing binary coded words. 50 received through the inverter circuit 41. Connected to the output of the serial data storage cir From the foregoing, it is to be observed that the extra cuit 30 are serially connected 1 digit delay circuits 31-33. digit of any word or integer will be treated as a blank The 1 digit delay circuits are well-known. The assignee of and cannot be used as part of the data word. The preced the present application is also the assignee of the afore ing or less significant binary coded digits may or may not said application filed by Howard Z. Bogert. 55 be coded as blanks. The comparator 40 serves to detect The first binary coded digit signal representing the each binary coded digit transmitted thereto by the 1 first decimal digit is transmitted from the serial data digit delay circuit 30 to determine whether it is coded as a blank. storage circuit 30 to the 1 digit delay circuit 31. One digit later, the second binary coded digit signal repre Connected to the output of the 1 digit delay circuit 32 senting the second decimal digit is transmitted from the 60 is a comparator circuit 45 which serves to compare the serial data storage circuit 30 to the 1 digit delay circuit signal fed thereto with a zero coded signal to determine 31. Simultaneously there with, the signal representing whether the binary coded digit transmitted thereto is a the first binary coded digit advances from the 1 digit de Zero digit. The binary coded digit signal transmitted by lay circuit 31 to the 1 digit delay circuit 32. At this time, the 1 digit delay circuit 32 is delayed one digit in time the binary coded digit signal advancing to the 1 digit 85 with respect to the binary coded digit signal transmitted delay circuit 32 represents the least significant digit and by the digit delay circuit 31. Hence, the binary coded the binary coded digit signal transmitted to the 1 digit digit signal transmitted by the digit delay circuit 31 is delay circuit 31 represents a more significant digit. The more significant than the binary coded digit signal trans serial data storage circuit 30 transmits the less significant mitted by the 1 digit delay circuit 32, However, the binary digit first followed by an adjacent successive more signi O coded signal transmitted by the 1 digit delay circuit 32 ficant digit. to be examined for a zero coded signal is on time, while When the serial data storage circuit 30 transmits the the more significant binary coded signal transmitted by bniary coded digit signal representing the third decimal the 1 digit delay circuit 31 to be examined for a blank digit to the 1 digit delay circuit 31, the second binary coded signal is one digit time earlier. coded digit signal advances simultaneously to the 1 digit The comparator circuit 45 compriscs a conventional 5 3,388,384 6 ously a blank code for the more significant digit and a Zero code for the less significant digit, then there is no zero to be suppressed for the less significant digit, and a logic signal will be transmitted from the 1 digit delay cir cuit 65 to initiate a terminate suppression signal during the succeeding word cycle. The 1 digit delay circuit 65 comprises a conventional and-gate logic circuit 66, which has an input thereof conductor 48. P digit markers are in a logic 1 state only connected to the output of the flip-flop circuit 57 of the when P digits are being advanced from a digit delay cir cuit 32 to 1 digit circuit 33. The P digits are the miscel 10 comparator circuit 55 and another input thereof con nected to the conductor 59 over which is transmitted bit laneous digits in a word other than the X digit marker, 1 of every digit signal (FIGS. 1-a and 2). The conductor which represents the last digit of a word. nor-gate logic circuit 46, which has an input thereof con nected to the output of the 1 digit delay circuit 32 at the terminal S. Another input of the nor-gate logic circuit 46 is connected to a conductor 47 over which a zero coded signal is transmitted (FIGS. 1 and 2). In addition there to, P digits marking pulses (FIGS. 1 and 2) are trans mitted to an input of the nor-gate logic circuit 46 over a The conductor 47 and the cutput of the 1 digit delay circuit 32 are also connected to a conventional and-gate 59 is also connected to an input of a conventional nor gate logic circuit 67. Connected to the output of the and gate logic circuit 66 and the nor-gate logic circuit (67 is a conventional nor-gate logic circuit 68. A conventional Cr-gate logic circuit 69 has an input thereof connected to logic circuit 49 of the Zero comparator circuit 45. In turn, the output of the and-gate iogic circuit 49 and the nor gate logic circuit 46 are connected to a conventional nor the output of nor-gate logic circuit 68. The output of the gate logic circuit 59. Through this arrangernent, the com of-gate logic circuit 69 is connected to a conventional parator circuit 45 checks for a zero coded binary digit signal at the output of the 1 digit delay circuit 32. If a 20 bit delay circuit 70. It is the output of the 1 bit delay cir cuit 70 that is connected to another input of the nor-gate zero coded binary digit signal is detected, the comparator logic circut 67. It is to be observed that the output of the circuit 45 produces a logic Zero signal in its output for the 1 digit delay circuit 65 is obtained at the output of the entire digit time. In the event a non-zero coded binary nor-gate logic circuit 68. digit signal is detected, the comparator circuit 45 produces The output of the nor-gate logic circuit 68 is con a logic 1 signal in its output for at least one bit time dur nected to a 1 digit data blanking circuit 75. The set in ing the digit time. put of the flip-flop circuit 57 for the comparator circuit The output signals of the zero comparator circuit 45 55 always goes to a logic 1 at the beginning of each digit. and the blank comparator 40 are fed simultaneously to a This is accomplished through the pulses transmitted over comparator circuit 55. As the Serial data word advances continuously through the Serial data storage circuit 30, a 30 the conductor 59 to a signal bit 1 of every digit. The same signal prepares the 1 digit delay circuit 65 for operation less significant digit precedes a more significant digit. The at the end of each digit or the beginning of zero sup comparator circuit 55 examines simultaneously two digits pression examination. The reset input of the flip-flop cir in succession during each recirculation of the completed cuit 57 will be activated if either the output of the blank data word. In sc doing, the comparator circuit 55 deter comparator circuit 40 or the zero comparator circuit mines whether the more significant digit is coded for a 45 is a logic 1 signal at any time during the digit. If blank and whether the less significant digit is coded for the reset input of the flip-flop circuit 57 is not activated, a zero. Should both conditions exist simultaneously, then the output of the comparator circuit 55 remains a logic 1 the signal transmitted by the comparator circuit 55 is a as long as the output signal of the comparator circuit logic 1 signal. 40 is a logic zero signal and the output of the com The comparator circuit 55 comprises a conventional or parator circuit 45 is a logic zero signal. This indicates the gate logic circuit 56 which has one input thereof con more significant digit is a blank and the less significant nected to the cutput of the bank comparator circuit 46 digit is a zero. and has another input thereof connected to the output of The output of the comparator circuit 55 under the the zero comparator circuit 45. Connected to the output just-described conditions is a 1 digit wide blank signal, of the or-gate legic circuit 56 is the reset input of a con which is delayed approximately 1 digit in time by the 1 ventional set-reset fip-flop circuit 57 in which the reset digit delay circuit 65. As a consequence thereof, the input overrides the set input. The set input of the flip-flop zero coded signal examined by the comparator circuit circuit S7 is connected to the output of a conventional 45 at the terminal S1 arrives at the 1 digit data blanking Cr-gate logic circuit 58. In turn, an input of the or-gate circuit 75 at the same time as the blanking signal is logic circuit 58 is connected to a conductor 59 over transmitted to the 1 digit data blanking circuit 75. It which are transmittcd pulses representing bit 1 of every is recalled that the zero coded signal after advancing binary coded digit signal (FIGS. 1-a and 2). from the 1 digit delay circuit 32 advances through the 1 The flip-flop circuit 57 at the beginning of each digit digit circuit 33, which feeds the zero coded signal to time is set to a logic 1 through the pulses transmitted over the conductor 54 and the cr-gate logic circuit 58. The 5 5 the 1 digit data blanking circuit 75. In a like manner, the logic 1 signal transmitted by the comparator circuit output of the filip-flop circuit 57 remains at a logic 1 55 advances through the 1 digit delay circuit 65, which in the event the output of the blank comparator circuit then feeds the blanking signal to the 1 digit data blank 49 is a logic zero and the output of the Zero comparator ing circuit 75. Hence, the zero coded signal advancing circuit 45 is a logic zero. Accordingly, the output of the coimparator circuit 55 is a logic i when the more sig 60 from the serial data storage circuit 30 arrives at the 1 digit data blanking circuit 75 at the same time as does niicant digit is a blank and the less significant digit is the blanking signal produced by the zero-blank compara a zero simultaneously. tor circuit 55. The output of the comparator circuit 55 is fed to the The output of the 1 digit delay circuit 65 is fed to input of a 1 digit delay circuit 65. The output of the a 1 digit data blanking circuit 75, the output of the 1 i digit delay circuit 65 is timed to coincide with the less digit delay circuit 33 is fed to the 1 digit data blanker significant digit. Hence, the output of the 1 digit delay 75, and a zero suppression active signal is fed to the 1 circuit 65 produces a one digit wide blanking or sup digit data blanking circuit 75 over a conductor 84. The pressing signal which is timed with the less significant digit data blanking circuit 75 serves to transmit a blank digit. Therefore, should two digits in succession be ex amined with the less significant digit being coded a zero 70 coded signal at the terminal S3 to the data processing circuits 22 in timed sequence with the advancement of digit and the more significant digit being coded a blank, the insignificant digit to the serial data storage circuit. the less significant digit will be changed to a blank code A blanking signal will be generated by the blanking as it circulates or advances through the Zero suppression circuit it. Should the comparator circuit 55 not detect simultane amplifier 11 on the control grid during the digit time the insignificant digit would appear on the cathode ray 3,388,384 7 8 tube 21 in response to the recognition of the blank flip-flop circuit 90 remain in the logic 1 state when the coded digit produced by the 1 digit data blanking cir last bit of serial data stream pulse signal is transmitted cuit 75. over the conductor 85, the operation of the zero sup Should the output of the 1 digit delay circuit 32 pressor circuit 10 is ended and the zero suppression active represent a significant non-zero coded signal, then the 5 state signal will go to the logic zero state. output of the comparator circuit 55 will be driven to For terminating the operation of the zero suppression the logic zero state. As a consequence thereof, the 1 circuit 10, a conventional and-gate logic circuit 95 has digit data blanking circuit 75 does not produce a blank one input thereof connected to the conductor 85 over coded signal for the transmission to the data processing which is transmittcd the last bit of serial data stream sig circuits 22, but instead a logic zero signal for terminat nal. Another input thereof is connected to a conductor 84 ing the zero suppression is transmitted from the output 10 over which is transmitted the zero suppression active of the 1 digit delay circuit 65 to a zero suppression corn State signal. The last input of the and-gate logic circuit 95 plete circuit 80. is connected to the output of the flip-flop circuit 90. The The 1 digit data blanking circuit 75 comprises a con Output of the and-gate logic circuit is connected to an ventional inverter circuit 81 which has its input connected input of the or-gate logic circuit 58 of the blank-zero com to the 1 digit delay circuit 33 and has its output con parator circuit 55 and to an input of the 1 digit delay nected to a conventional nor-gate logic circuit 82. In circuit 65. the 1 digit data blanking circuit 75 is also a conventional In case all digits in the word, or words, are zeros, the and-gate logic circuit 83 which has an input connected zero suppression operation is terminated by using the P to the 1 digit delay circuit 68 and an input connected 20 digits Inarker on conductor 48 to force the zero compara to the conductor 84 over which is transmitted the zero tor circuit 45 output to the logic 1 state during the P suppression active state signal (FIGS. 1-a and 2). The digit line. This prevents the comparator circuit 55 output output of the and-gate logic circuit 83 is connected to from changing to the logic 1 state, which in turn prevents another input of the nor-gate logic circuit 82. In turn, the 1 digit delay circuit 65 output from generating a signal the output of the nor-gate logic circuit 82 is connected 25 to reset the flip-flop circuit 99. This action, in turn, causes to the data processing circuits 22 and the control grid of the terminate Zero suppression state signal to be produced the cathode ray tube 21 through the blanking amplifier 11. over the conductor 91. At the beginning of a word or integer, a zero suppres FIG. 3 illustrates a total data stream format wherein sion active state pulse signal transmitted over the con m represents the number of words in the serial data stream ductor 84 conditions the 1 digit data blanking circuit 30 circulating through the serial data storage circuit 39 75 for operation. The zero suppression completed cir least significant digit first; cuit 80 is connected to the conductor 84 to receive there in represents the number of data digits per word; from the zero suppression active state signal. The Zero v represents the extra digit or the digit adjacent to the suppression active state signal prepares the zero Sup most significant digit of each data word and is coded pression completed circuit 80 at the beginning of each as a Zero; zero suppression operation. Also connected to the input p represents the number of miscellaneous P digits per of the zero suppression completed circuit 80 is the out word in addition to the extra digit; put of the 1 digit delay circuit 65. Should thc signal LSD represents the least significant digit of each data from the output of the 1 digit delay circuit 65 be a word. logic signal to represent a significant non-zero digit signal, 40 The total numbcr of digits per word is: then the zero suppression completed circuit 80 emits a n-p--1 where 1 represents digit X signal to terminate zero suppression state. The zero suppression completed circuit 80 comprises The total number of digits in the serial data stream is: a conventional inverter circuit 86, which has its input connected to the conductor 84 over which the Zero Sup pression active state pulse signal is transmitted. One in Each digit in the exemplary embodiment is assumed to put circuit of a conventional or-gate logic circuit 87 be 4 bits long and will be in the excess 3 binary coded is connected to the output of the inverter circuit 86 and decimal format. A blank coded digit is defined herein as another input thereof is connected to the output of the all bits of the digit equal to a logic zero. 1 digit delay circuit 65. In turn, the output of the or-gate In the operation of the zero suppression circuit 10, let it logic circuit 87 is connected to the reset input of a con be assumed by way of example or illustration that the ventional set-reset flip-flop circuit 90. Connected to the completed words or integers recirculated by the data proc set input of the flip-flop circuit 90 is the conductor 85 essing circuits 22 are 0.045 and 0302. Graphically, the over which the last bit of serial data stream pulse signal operation is described as follows: is transmitted. The output of the flip-flop circuit 90 is connected to a conductor 91 over which is transmitted StreaIn? Time X2 Word P. Xi Word 1 ]” a signal to terminate zero suppression state for Zero Sup ~~--— Before Suppression.------------ 0. O302 0 ??5 3 pression circuit 10. Cycle 1.-----------E3 (302 7 B ?5 3. Cycle 2. B B302 7 B B045 3. The flip-flop circuit 90 is always set to a logic 0 state Cycle 3B 3302 7 B BB45 3 at the beginning of the zero suppression operation by 60 Cycle 4? ? ? ? ? ? ? ? ? ? ? ? ? B B302 B BB45 3 3 BB45 3 the zero suppression active state signal transmitted over After Suppression.------------- B B302 the conductor 84 through the inverter 86 and through "Terminate zero suppression. the or-gate logic circuit 87. The flip-flop circuit 90 is The serial data storage circuit transmits the east sig then set to the logic 1 state at the end of the first word nificant digit first and under the present example the ad cycle by the last bit of the serial data stream signal 65 vancement of binary digits therethrough appear in the transmitted over the conductor 85. When the logic 1 following order 354.000720300. However, the examina signal is produced in the output of the 1 digit data delay tion for insignificant ciphers to the left of a significant circuit 65, the flip-flop circuit 90 is reset to a logic zero non-zero digit is in the reverse order. During the first cir state and does not produce a terminate Zero suppression of the data words, the extra digit X is zero coded state signal. On the other hand, should the output of 'culation and advances through the 1 digit delay circuits 31 and 32. the 1 digit delay circuit 65 be a logic zero signal to in 70 At the terminal St, the zero coded extra digit X is trans dicate all the zeros have been suppressed, the flip-flop mitted to the comparator circuit 45 where it is detected circuit 90 is not reset and remains in the logic 1 state. is a Zero coded digit. At the same time the successive P As a consequence thereof, a terminate zero suppression digit is transmitted to the comparator circuit 40 where signal is transmitted over the conductor 91. Should the it is treated as a blank coded digit by means of the 3,388,384 transmission of the X digit marker signal through the inverter circuit 41. In a like manner, the extra digit Xa during the first circulation of the data words is zero coded and advances through the 1 digit delay circuits 31 10 cuit 10 examined each two adjacent digits of words 1 and 2, such as 3-5, 5-4, 4–0, 0-0, 0-0 for word 1 and 7-2, 2–0, 0–3, 3-0, 0-0 for word 2, there was not present simultaneously a more significant blank code followed by a less significant zero code. However, the X digit marker pulse causes the output of the comparator circuit 40 to go to a logic zero during the time a P digit is read out of the 1 digit delay circuit 31. Hence, the logic out put of the flip-flop circuit 57 of the comparator circuit 40 where it is treated as a blank coded digit by means of the transmission of the X digit marker signal through O 55 went to a logic 1 and the blank coding operation of the 1 digit data blanking circuit 75 was activated. This the inverter circuit 41. As the extra digits X and Xa blank-coded the extra digits X and X2. The Zero Sup advance through the 1 digit delay circuits 32 and 33 and pression completed circuit 80 did not produce a terminate then through the 1 digit data blanking circuit 75 to re zero suppression signal, since it was reset by the output turn to the data processing circuits 22 for recirculation, of the 1 digit data blanking circuit 75 going to a logic 1. they will be blank coded as they travel through the blank and 32. At the terminal S1, the zero coded extra digit X is transmitted to the comparator circuit 45 where it is detected as a zero coded digit. At the same time, the successive P digit is transmitted to the comparator circuit ing circuit 75, data processing circuits 22 and the serial During the second recirculation of the data words, the binary coded digit 0 will advance through the 1 digit delay circuit 32 while the blank coded extra digit X ad vances through the 1 digit delay circuit 31. Thereupon, the comparator circuit 40 connected to the terminal So ex amines the blank coded digit and simultaneously the comparator circuit 45 examines a zero coded digit. The output of the comparator circuit 40 is a logic zero and the output of the comparator circuit 45 is a logic Zero for the entire digit time. Concurrently, the output signals of the comparator cir data storage circuit 30. During the succeeding cycle, the most significant digit of data word 1, the X1 extra digit, the most significant digit of data word 2 and the X2 extra digit are blank coded processing circuits 22 and the serial data storage cir while the data words are recirculated through the data cuit 30. When the less significant digit 0 of word 1 advances through the 1 digit delay circuit 32 to terminal S1 and the blank coded most significant digit of word 1 advances through the 1 digit delay circuit 31 to terminal So, the comparator circuit 45 detects a zero code and the con parator circuit 40 detects a blank code. In the manner previously described, the 1 digit data blanking circuit 75 is timed sequence with the advancement of the less sig cuits 40 and 45 are fed to the comparator circuit 55. The flip-flop circuit 57 of the comparator circuit 55 is set at 30 nificant zero to the data processing circuit 22 causes the less significant digit to be blank coded. As the data words the beginning of each digit for a logic 1 output through 1 and 2 are again recirculated through the serial data the bit 1 of every digit signal transmitted over the con storage circuit, the extra digits X and X2, the most sig ductor 59 and the orgate logic circuit 58. Since the com nificant digits of the data words 1 and 2, and the just parator circuit 40 detected a blank extra digit X and the mentioned less significant Zero digit are blank coded. comparator circuit 45 detected a zero most significant digit The zero suppression circuit 10 continues to examine for data word 1, the flip-flop circuit 57 maintains the logic the two adjacent successive digits, such as 3–5, 5–4, 4-B, 1 signal in its output. B-B, B-B for data word 1 and 7-2, 2-0, 0–3, 3-B and The most significant digit of data word 1 advances B-B for data word 2. Since the comparator circuits 40 through the 1 digit delay circuit 33 and through the 1 digit data blanking circuit 75. In timed sequence, the logic 4) and 45 did not detect simultaneously a more significant blank code and an adjacent less significant Zero code, 1 output signal emanating from the comparator circuit the logic output of the flip-flop circuit 57 of the com 55 advances through the 1 digit delay circuit 65 and parator circuit 55 went to zero, and the blanking code through the 1 digit data blanking circuit 75, where the operation of the 1 digit data blanking circuit 75 was not Zero code is changed to the blank code. Now, the most activated. significant digit of word 1 is blank coded as it advances At the time the digits 3-5 were re-examined, the zero for recirculation through the data processing circuits 22 suppression completed circuit 80 was conditioned for and the serial data storage circuit 30. operation by the last bit of the serial data stream signal During the same recirculation of the data words, the transmitted thereto over the conductor 85. Thereupon, most significant digit zero of word 2 advances through the 1 digit delay circuit 32 and the blank coded extra digit 50 the output of the flip-flop circuit 90 of the zero sup pression completed logic circuit 80 goes to the logic 1 X advances through the 1 digit delay circuit 31. There state and will not be reset by any blanking signal from the upon, the comparator circuit 40 connected to the terminal 1 digit data blanking circuit 75. Since the flip-flop cir So examines the blank coded signal and simultaneously cuit 90 is not reset at the time the succeeding last bit of the comparator circuit 45 examines a zero coded digit. serial data stream signal is transmitted thereto, a ter Concurrently, the output signals of the comparator cir minate zero suppression signal is transmitted from the cuits 40 and 45 are fed to the comparator circuit 55. flip-flop circuit 90 of the zero suppression completed cir The flip-flop circuit 57 of the comparator circuit 55 is cuit 80 to terminate the zero suppression operation. Thus, at the beginning of each digit for a logic output through appearing on the cathode ray tube 21 are the data words the 1 bit 1 of every digit signal transmitted over the con ductor 59 and the or-gate logic circui