Historical Document · 1967
The Wyle Scientific display, filed 16 December 1963 and granted 21 February 1967: digits drawn from gated sine and cosine arcs, timed from a cyclic memory.
Feb. 21, 1967 T.J. scuitTo 3,305,843 DISPLAY APPARATUS Filed Dec. 16, 1963 . 3. Sheets-Sheet l a 42 D CounTER 2O . WCOL, NTER 22 27 Y S Go Na WOD Ry N Go. RANS EN &E/WOVA A PPARATuS CY RCA D ADDER A5o 2O 2. D /a -- 27 X of GNAL TRANst NT Mob FYNG A PPARATus REMOVA c Rcu y - - - - --1 \ 53 \ 56 - AD PR 52 & P/A 1) Count R. - Z77. 4 77/o4As A sco//77o INVENTOR. ?ula 4 la A77 orweY5 Feb. 21, 1967 T.J. scuit to 3,305,843 DISPLAY APPARATUS Filed Dec. 16, 1963 16 - F 3. Sheets-Sheet 2 - - TER - 2V J > ') Y -3CW GCB GDxD GEX B G X D GGX INVENTOR. Z27.2 Tin A 56 Z//77 o BY all-e 26-4A-l A77 oaways Feb. 21, 1967 T. J. scuiTTo 3,305,843 DISPLAY APPARATUS Filed. Dec. 16, 1963 3. Sheets-Sheet 3. P. P. P. P. P. P5 PP, R, Ro - xo s t asks o stas Z77. 3 1. P7 as -4 3th N -1 El 1. o, E N 7N N d L ya s (4 1 ket? yoA Ko H 1. YSE 77/o/M4s Msco/77 o INVENTOR, Oru. A 1/g.0.4 A7 forways United States Patent Office 3,305,843 3,305,843 Patented Feb. 21, 1967 2 D counter. The states of the W and D counters are cou pled to the cathode ray tube deflection means through re Spective digital-to-analog converters for positioning each display digit. Gating means are provided which are re Sponsive to each state of the W counter for coupling the California output of a different memory register to the logic gates. Filed Dec. 16, 1963, Ser. No. 330,843 Synchronization between the display apparatus and the 7 Claims. (C. 340-172.5) digital memory is assured by utilizing the square wave This invention relates generally to display apparatus output signal developed by the B counter to generate the and more particularly to a relatively simple, inexpensive, O sine and cosine signals used to control the cathode ray and reliable apparatus for displaying numeric data. DISPLAY APPARATUS Thomas J. Scuitto, Malibu, Calif., assignor to Wylie Laboratories, El Segundo, Calif., a corporation of U.S. patent application Ser. No. 314,387, filed Oct. 7, 1963, entitled "Calculator Apparatus,' and assigned to the same assignee as the present application, discloses an electronic apparatus for performing arithmetic opera tions, which apparatus in its preferred embodiment is characterized by the use of both a digital memory includ ing a plurality of registers for storing numbers, and a tube beam deflection. The novel features that are considered characteristic of this invention are set forth with particularity in the ap pended claims. The invention itself both as to its orga nization and method of operation, as well as additional ob jects and advantages thereof, will best be understood from the following description when read in connection with the accompanying drawings, in which: display device for continually displaying the contents of FIGURE 1 is a logical block diagram illustrating the those registers. Each stored number can be comprised 20 apparatus for coupling a digital memory to logic gates for of a plurality of digits and the value of each digit is rep controlling the application of signals to cathode ray tube resented by the number of marks or pulses recorded in deflection means; the corresponding memory digit sector. As mentioned FIGURE 2 is a schematic diagram of the signal modi in the cited patent application, any of several different fying apparatus utilized to control the X deflection means; display devices could be used for displaying the stored 25 FIGURE 3 is a chart illustrating the shapes of each digits. of the deflection signals developed to cause the cathode It is an object of the present invention to provide a ray tube beam to trace each decimal digit; and particularly simple, inexpensive, and reliable display ap FIGURE 4 is a block diagram illustrating the appa paratus suitable for use with the above-mentioned calcul ratus coupling the X and Y modifying apparatus to the 30 lator apparatus. cathode ray tube deflection means. More specifically, it is an object of the present inven Attention is now called to FIGURE 1 which illustrates tion to provide an apparatus which is responsive to a a digital memory 10 of the cyclic type, such as a magnetic total number of pulses sensed during each of a plurality drum or disc, from which information is accessed in a of successive periods for displaying successive digits each serial manner. It is assumed that the memory 10 in corresponding to the total number of pulses sensed during cludes six register tracks and a clock track. Each of the a different period. register tracks is divided into a plurality of digit sectors, In accordance with the invention, a cathode ray tube each digit sector capable of containing sufficient infor is provided together with means for generating sine and mation to represent a decimal digit. Thus, a register cosine signals. By selectively applying either the sine track comprised of twenty-four digit sectors can repre or cosine signal to the cathode ray tube deflection means 40 sent a twenty-four decimal digit number. Each digit and by simply manipulating bias and amplitude levels sector includes a plurality of bit positions, herein arbi and signal polarity, the tube beam can be caused to trace trarily assumed to be twelve. The initial bit position any desired decimal digit. (P) and the last two bit positions (P10, P1) in each More particularly, in response to the serial sensing of 45 digit sector are provided for control purposes. The nine pulses recorded in a cyclic digital memory, a first count intermediate bit positions (P1-P9) in each digit sector er is incremented during each digit period to a state cor are utilized to store a mark or pulse. The number of responding to the number of pulses sensed during that pe pulses recorded in each digit sector defines the value of riod. At the end of each digit period, the count in the the decimal digit stored in that sector. first counter is transferred to a second counter which can The clock track has a pulse recorded in alignment with 50 comprise a static register, whose output is decoded. The each bit position around the surface of the disc or drum. output sets up certain logic gates which are enabled dur The output of the clock track is coupled through con ing different bit periods during the subsequent digit pe ductor 14 to an incrementing input terminal of a B riod. The logic gates control the application of the sine counter 16. The B counter is a scale of twelve counter and cosine signals to the cathode ray tube horizontal (X) and consequently has a cycle time equal to the time it and vertical (Y) deflection means and in addition deter 55 takes for stored information to be read from a complete mine whether a full or half amplitude signal should be digit sector. applied. The logic gates are also capable of selectively The B counter 6 is coupled to a D counter 18 such reversing the polarity of the signal applied to the deflec that in response to each complete cycle of the B counter, tion means and of applying different levels of direct cur 60 the D counter is incremented by one. Thus, the state of rent bias thereto. Further, a beam blanking circuit is the D counter at all times indicates the digit sector in the provided which is also responsive to the logic gates. memory which is in position to be read. The D counter A significant feature of the invention involves the 18 is coupled to a W counter 20 such that the W counter means for synchronizing the operation of the display is incremented in response to cycles of the D counter. The apparatus with the operation of the digital memory. A 65 W counter is a scale of six counter and functions to suc source of clock pulses, preferably in the form of a clock cessively couple the information stored in each of the track provided in the memory, supplies a clock pulse dur register tracks to the display apparatus to be described ing each bit period. The clock pulses are used to incre hereinafter. The output terminals of the W counter 20 are coupled through a decoding circuit 22. The decoding ment a bit (B) counter. A digit (D) counter whose states define different digit periods is incremented in re O circuit 22 is provided with six output terminals, each one of which is connected to the input of a different And gate sponse to each cycle of the B counter. A word (W) counter is incremented in response to each cycle of the 24. The second input to each of the And gates 24 is 3,305,843 3. connected to the readout head associated with a different one of the register tracks of memory 10. The outputs of all of the And gates 24 are coupled to the input of an Or gate 26. The output of Orgate 26 is connected to the incrementing input terminal of an N counter 28. A decoding circuit 30 is connected to the output termi nals of the B counter 16. The decoding circuit 30 is provided with twelve output terminals, each of which is 4. switching circuit 49 which, under the control of gate GAx selectively couples the filter output signal to the switching circuit output terminal 50. Switching circuit 49 includes a pair of serially connected resistors 5 and 52. Con nected to the junction between resistors 51 and 52 is the collector of a grounded emitter PNP transistor 53. The base of transistor 53 is coupled through resistor 54 to the collector of a grounded emitter PNP transistor 55 which is controlled by the output of gate GAx. Resistors O 56 and 57 respectively couple the collector of transistor 55 to a -30 volt potential and to terminal 50. When energized in response to the B counter defining its initial gate GAx is enabled, transistor 55 conducts so that ap state or bit period P. Conductor 32 is connected to the proximately ground potential appears on the collector reset input terminal of N counter 28 such that at the selectively energized in response to a different state of the B counter. Decoding network output conductor 32 is thereof thus cutting off transistor 53. A sine wave signal beginning of each scan of a digit sector, the N counter provided by filter 46 is thus coupled through resistors 51 28 is cleared. During the subsequent bit periods of that and 52, impressed upon a negative bias level established digit sector, the N counter is incremented in accordance by the potential drop across resistor 57, to output termi with the number of pulses sensed on the register track nal 50. When gate GAx is not enabled, transistor 53 is associated with the enabled And gate 24. A different forward biased thereby clamping the junction between And gate 24 will be enabled in response to each different 20 resistors 51 and 52 to substantially ground potential and state of the W counter 20. the sine wave signal supplied by filter 46 is not coupled The Q counter 34, like the N counter 28 is capable of to terminal 50. Switching circuit 58, identical to circuit defining ten different states, each different state corre 49, couples filter 48 to terminal 50 and is controlled by sponding to a different decimal digit. Output conductor gate GAx. 36 of the decoding circuit 30 is connected to the Q counter The output terminal 50 is connected to the base of reset input terminal and is energized when the B counter a PNP transistor amplifier 64 whose emitter is grounded. 16 defines bit period Po. In the subsequent bit period, conductor 38 is energized to enable transfer gates 40 The base of transistor 64 is connected through a resistor which cause the contents of the N counter to be trans 66 to a source of positive potential, nominally shown as -- 12 volts. The collector of transistor 64 is con ferred into the Q counter. nected through resistor 68 to a source of negative poten The output terminals of the Q counter are connected tial nominally shown as -30 volts. The collector of to the input of a decoding network 42 which is provided transistor 64 is also connected to the base of transistor with ten output terminals respectively identified as Do, amplifier 70 whose emitter is grounded and whose col D1, and D2 through D9. A different one of the decoding circuit 42 output terminals is energized in response to lector is connected through a resistor 72 to the -30 each possible state of the Q counter 34. The output ter volt source. Feedback resistors 65 and 71 respectively minals of decoding circuit 42 are coupled to logic gates couple the collectors of transistors 64 and 70 to their bases. 44 forming part of the signal modifying apparatus of FIGURE. 2. The signal modifying apparatus is com It should be apparent that if a sine wave is applied prised of two identical portions for respectively modify to the base of transistor 64, as would be the case if ing signals applied to the cathode ray tube X and Y 40 transistor 54 were forward biased, the sine wave would deflection means. These two portions are identical in appear at the collector of transistor 70 and a signal hav structure and differ only in the inputs provided to the ing a reverse polarity would appear at the collector of various logic gates 44 contained therein. transistor 64. Similarly, if a cosine signal were applied As will be seen hereinafter, sine and cosine signals, to the base of transistor 64, the cosine signal would properly modified, can be applied to the X and Y deflec appear at the collector of transistor 70 and a signal of opposite polarity would appear at the collector of tran tion means of a cathode ray tube to cause the cathode sistor 64. ray tube beam to trace any decimal digit. Signal modi fication in accordance with the invention involves three The collectors of transistors 64 and 70 are respectively distinct aspects. Initially, either a sine, cosine, or zero connected to identical resistance networks 74 and 76. signal can be applied to the deflection means at full or 50 Each of the networks includes a left-hand series path half amplitude. Secondly, the sine or cosine signal can comprised of a pair of resistors R1 and R2 and a right be applied to the deflection means with normal or re hand series path comprised of a pair of resistors respec versed polarity and thirdly, the modified sine or cosine tively having values of R1/2 and R2/2. Both resistance signal can be impressed upon any one of three direct networks 74 and 76 are connected to the junction 78. current bias levels. In addition, the cathode ray tube 55 The junctions defined in the right-hand series branches beam can be blanked where necessary. FIGURE 2 ill of each network are coupled through compensating re lustrates the apparatus for modifying the signal applied sistors 75 and 77 to the -30 volt potential source. to the X deflection means. The apparatus for modifying It should be apparent that a current entering junction the signal applied to the Y deflection means is identical 78 will be of one polarity if permitted to traverse the except for the inputs to the various logic gates. Inputs 60 resistance network 74 and of an opposite polarity if per to the gates of FIGURE 2 have not been illustrated on mitted to traverse the resistance network 76. On the the drawings and instead are represented in the chart of other hand, it should be apparent that regardless of which Table I and the logical equations of Table II set forth resistance network the current traverses, it will be of hereinafter, full amplitude if it traverses the right-hand circuit branch As noted, the B counter 16 is incremented in response and of half amplitude if it traverses the left-hand circuit to each clock pulse derived from the clock track of mem branch. Control over the amplitude of the current is ory 10. The output of the B counter 16 comprises a exercised by gate Gox and control over the polarity of square wave which is applied to a divider circuit 45 which the signal appearing at junction 78 is exercised by gate in turn provides a square wave output signal whose fre GDx. quency is equal to one-fourth of the frequency of the 70 The output of gate Gox is connected to the base of frequency of the B counter output signal. The output transistor 80 whose emitter is grounded. The base of of the divider circuit is applied to filters 46 and 48 to transistor 80 is connected through a resistor 82 to a respectively develop sine and cosine wave signals of the Source of positive potential. The collector of transistor same frequency as the signal provided by circuit 45. 80 is connected to the base of transistor 82 and to the The output of filter 46 is connected in series with a 75 anodes of diodes 84 and 86. The cathodes of diodes 84 S 3,305,843 and 86 are respectively connected to the junctions be tween the resistances in the right-hand branches of net Works 74 and 76. The base of transistor 82 is connected through a resistance 88 to the -30 volt source. The emitter of transistor 82 is grounded and the collector thereof is connected to the anode of diodes 90 and 92. The cathodes of diodes 90 and 92 are connected to the 6 122 and 124 are off-biased can be considered as a full positive bias level. When both transistors 122 and 124 are forward biased, the D.C. bias level presented at junction 78 can be considered to be a positive half bias level. When transistor 124 is forward biased and tran sistors 120 and 122 are off-biased, then the D.C. level presented at junction 78 can be considered as a negative junctions between the resistances in the left-hand branches half bias level. When none of transistors 120, 22, and in networks 74 and 76. 124 is forward biased, a negative full bias level is pre When a negative input signal is applied to the gate 10 sented. The voltage variations at junction 78 are applied Gox, transistor 80 is forward biased and thus clamps to transistor amplifier 126 and thence through a transient the junctions in the right-hand branches of the networks removal circuit 127 to adder circuitry in FIGURE 4 for 74 and 76 to ground. Thus, the current flow through application to the deflection means of a cathode ray tube. junction 78 is inhibited from traversing the right-hand The emitter of transistor amplifier 126 is grounded branches. On the other hand, when a negative input 5 and the collector thereof is connected through a feedback signal is not applied to gate Gox, then transistor 80 is resistor 128 to the base thereof. Resistor 129 connects off-biased so that diodes 90 and 92 clamp the junctions the collector to a -30 volt potential. The transient of the left-hand branches in circuits 74 and 76. Thus, removal circuit 127 is used to remove Switching transi when transistor 82 is forward biased, the current through ents which arise when, for example, the signal applied to junction 78 selects either of the right-hand branches of 20 the deflecting means of the display cathode ray tube 12 networks 74 and 76. is abruptly switched from a sine to a cosine wave signal. The particular network, i.e. either 74 or 76 is selected The circuit 127 operates by momentarily decoupling the dependent upon the inputs to gate GDx. The output output of transistor amplifier 126 from the adder cir of gate Gpx is connected to the base of transistor 94. The cuitry in FIGURE 4 in response to each pulse derived base of transistor 94 is connected through resistor 96 25 from the clock track in FIGURE 1. to a source of positive potential and the emitter thereof Circuit 127 includes diodes 130 and 131 which respec is grounded. The collector of transistor 94 is connected tively have their cathode and anode connected to the col to the base of transistor 98 and to the anodes of diodes 100 and 102. The cathodes of diodes 100 and 62 are lector of transistor 126. The anode of diode 130 is con nected to the anode of diode 132 whose cathode is con respectively connected to the junctions in the right and 30 nected to the base of transistor 134. The cathode of left-hand branches of the network 76. The base of tran diode 131 is connected to the cathode of diode 33 whose sistor 98 is connected through resistor 104 to the -30 volt source and the emitter thereof is grounded. The anode is connected to the base of transistor 134. The junction defined between the anodes of diodes 130 and collector of transistor 98 is connected to the anodes of 132 is connected through a resistor 135 to a +12 volt 35 diodes 106 and 108 whose cathodes are respectively con potential. The junction defined between the cathodes of nected to the junctions in the left and right-hand branches diodes 131 and 133 is connected through, a resistor 136 of network 74. to a -30 volt potential. The base of transistor 134 is When negative input signals are applied to neither gate connected through a capacitor 37 to ground. In normal Gox nor gate Gox transistors 80 and 94 are off-biased 40 operation, the sine or cosine wave signal appearing at the and transistors 82 and 98 are forward biased. Thus, collector of transistor 126 is coupled through diodes 130, current into the junction 78 transverses the right-hand 31, 132, and 133 to transistor 134. Current continually branch in network 76. On the other hand, when nega flows from the -- 12 volt source through resistor 135 tive input signals are applied to both gates Gox and and diode pairs 130, 131 and 132, 133 through the resis Gox transistors 80 and 94 are forward biased and thus tor 136 to the -30 volt source. The voltage swing ap the active current path is the left-hand branch in net 45 pearing at the collector of transistor 126 is consequently work 74. The right-hand branch in network 74 is chosen reflected at the base of transistor 134. when transistor 80 is off-biased and transistor 94 is for In order to prevent switching transients from being ward biased. The left-hand branch in network 76 is coupled to the adder circuitry of FIGURE 4, the transis chosen when transistor 80 is forward biased and tran tor 126 is effectively decoupled from the transistor 134 sistor 94 is off-biased. Thus, it can be seen that the 50 each time a clock pulse is generated. This is accom current flowing into junction 78 can be controlled with plished through the utilization of circuitry coupled to respect to its amplitude and polarity. Compensating the anode of diode 146 and the cathode of diode 141. resistors 75 and 77 are used to cause the sine and cosine The cathode of diode 140 is connected to the junction wave signals to oscillate about the same voltage level between the cathodes of diodes 13 and 133 and the regardless of whether half or full value currents are 55 anode of diode 141 is connected to the junction between coupled. the anodes of diodes 130 and 132. A negative signal is The alternating current signal appearing at junction applied to capacitor 142 in response to a clock pulse. 78 is impressed upon a direct current bias level which is Capacitor 142 is coupled through resistor 143 to the base dependent upon which of transistors 120, 122, or 24 of transistor 144. The base of transistor 144 is coupled is forward biased. The output of Or gates GEx, GEx, 60 through resistor 145 to a --12 volt source and through a and Gox, are respectively connected to the bases of diode 146 to ground. The emitter of transistor 144 is transistors 120, 122, and 124. The bases of each of grounded. The collector of transistor 144 is connected these transistors is connected through a resistor to the to the anode of diode 140. Thus, the application of a source of positive potential while the emitters of each of negative signal to capacitor 142 forward biases transis these transistors are connected to ground. The collector 65 tor 144 thereby clamping the junction between diodes 131 of transistor 120 is connected through a resistor R3 to and 133 at ground. The collector of transistor 144 is the junction 78. The collectors of transistors 122 and connected through a resistor 147 to a -30 volt potential 124 are respectively connected through resistors having and through a parallel RC circuit to the base of transis values 2R3 and 4R3 to the junction 78. Additionally tor 148. The base of transistor 148 is connected through the collectors of transistors 120, 22, and 24 are each 70 a resistor 149 to a --12 volt source. The emitter of connected through resistors to the -30 volt source. If transistor 148 is connected to a -12 volt source. When it is assumed that the D.C. bias level presented at junc transistor 144 is forward biased, a positive potential is tion 78 when the transistor 122 is forward biased repre coupled to the base of transistor 148 and it becomes for sents a zero bias level, then the bias level presented Ward biased thereby applying a negative clamping poten when transistor 120 is forward biased and transistors 75 tial to the junction between diodes 130 and 132. Thus, 3,305,843 peg periods P1 through PA and a negative half value direct whereas the signal appearing at the collector of transis current voltage bias is impressed during periods P5 through tor 126 is normally coupled to the base of transistor 134, P8. The digit 3 is traced identically to the digit 8 except it is not coupled for a short interval after each clock pulse thereby preventing any switching transients from however that the cathode ray tube beam is blanked during periods P1 and Pa being applied to the adder circuitry of FIGURE 4 and In order to cause the beam to trace the digit 6, the appearing on the cathode ray tube 12. beam is blanked during periods P1 and P. At the begin The apparatus illustrated in FIG. 2 is employed to ning of period P the horizontal deflection signal is at control the X deflection means of a cathode ray tube. As Zero and begins to go negative. The vertical deflection previously noted, identical apparatus, except for the in puts to the various gates, is utilized to control the Y 10 signal is at a maximum positive and begin to go toward deflection means. Attention is now called to FIGURE 3 which illustrates the various waveforms applied to the X and Y deflection means for causing the cathode ray tube beam to trace the various decimal digits. Table I il lustrates the bit periods during which each gate is en abled to cause the tracing of each of the different digits. The symbol P is used to represent the bit periods P. through P. zero. Thus, the starting point for the beam trace is at the vertical top and horizontal center of the elemental display area and during period P the beam is caused to move to the vertical center and left side of the elemental area. During period P the beam is moved back to the horizontal center but to the vertical bottom of the elemental display area. It is to be noted that with the normal values of the X and Y deflection signals, the vertical deflection of the TABLE I GBLANK P1, Ps. P1, P2. P1, P2. P3--P4--Ps---Ps-Ps--------- beam is actually twice that of the horizontal deflection. In order to equate the deflections, the gate Goy is enabled so that a half value of the vertical deflection amplitude is selected. Gate Goy is enabled during period P5 and in addition the vertical deflection signal is impressed upon a negative half value direct current bias level. At the deflection means. Note that the illustrated waveforms end of period P5 the beam is positioned at the right-hand will in fact cause the beam to trace the decimal digit "O.' side of the elemental area approximately one-quarter of At the beginning of bit period P the valve of the signal the way up from the bottom of the area. During period applied to the X deflection means is zero and consequently the beam is positioned in the horizontal center of an ele 50 P the beam is moved to the geometrical center of the area and during period P the beam is swept to a position mental tube area. The value of the signal applied to the at the left edge of the area approximately one-quarter of Y deflection means is at a maximum and the beam is therefore positioned at the upper portion of an elemental the way up from the bottom. The digit 9 is traced in substantially the same manner tube area. At the end of period P1 the X deflection signal has become maximum and the Y deflection signal has 55 as the digit 6 but however the polarity of the horizontal and vertical deflection signals are reversed and instead of fallen to zero to therefore cause the beam to be deflected using a negative half value bias level, a positive half value to the center of the right side of the elemental display bias level is employed. area. At the end of period P the X deflection signal is The remaining digits, i.e., 2, 4, 5, 7, and 1 are traced by zero, causing the beam to again be positioned in the horizontal center of the area and the Y deflection signal 60 the utilization of techniques identical to that described for the previously referred to digits. The movement of is at its negative maximum to therefore position the beam the beam can be determined by considering the variations at the bottom of the elemental area. During period P3 in the deflection signals applied to the X and Y deflection the beam is swept to the vertical center and left-hand side means. The S and Y deflection signals can be caused to of the elemental area and during period P4 the beam is returned to the top horizontal center of the elemental 65 vary in the manner illustrated in the waveforms of FIG URE 3 by enabling the gates in accordance with the area. During periods P5 through Ps the digit is merely entries in Table I. Logical equations representing the retraced. input terms which must be applied to the various gates of In order to trace the digit 8 a sine wave is applied to FIGURE 2 are set forth in Table II. the X deflection means, the sine wave being reversed during periods P1 through P4. A cosine wave is applied 70 TABLE II-X GATE LOGIC to the Y deflection means with its amplitude being reduced to half value through periods P1 through Ps. The polarity PD =P--Pa-Pa-Pa-HPs--Ps--P1--Pa Thus, in order to cause a cathode ray tube beam to trace the digit 0, a sine wave is applied to the X deflec tion means and a cosine wave is applied to the Y deflection means. During bit period Po, gate GEY is enabled so as to establish the initial level of the signal applied to the Y of the cosine waveform is reversed during periods P1 GAx Gex through P while a positive half value direct current bias is impressed upon the vertical deflection signal during 75 =PD' (Do-I-D8+-D3--D6--D9-HD2) -- (P --P2) D4 = (P --P4) D4+ (P --P2--P3+Ps--P--Ps) D5 --PDD 8,305,843 9 Gox GDx = (P5--Ps--P--Pa.) D. = (P1--Pa--P3--P4) Ds-- (P --Pa--P8--PA) D --PDD9-HPDD2-- (Ps--Ps--P--Pa.) Ds GEx = (P5+-Ps--P-Ps) D4--Po (Ds--D) GFX =Po (Do-HDs--D3--Ds--D9--D2--D4--D1) --Pro (Do--Ds--D3--Ds--D9-Da-D-HD1) -- (P3--Pa.) D4-- (P --P--P5--Ps--P --P) D5 Gox = (Ps--Pg-HP--P8) Dr. GBANK = (P --P8) D3-- (P1--P2) Ds-- (P1-P2) Dg --PD--PDA GAY = (Ps--Pg-HP--Pa.) D4-- (P5+-P6 GBY --P--P) D5--PDD =PD (D-I-D--D3-HDs--Ds) -- (P1-Pa-P3 +P.+Ps (D-I-P.D4+ (P +P) D5+(Ps Goy GDy --Ps--P--P8)D =PD (D3-Ds) --(Ps--Ps--P--Ps) D6 -- (Ps--Ps--P--Ps) D9-- (P1--P2--P3 --PA) D2- (P1--P--P3-P4--P5 --Ps--P) D5 = (P --P-P-I-P) Da-- (P1-P2--P3--PA) D3 10 Serial pulses can comprise a digital memory of the cyclic type such that it functions to inherently repeatedly pro vide information signals which are particularly suitable for refreshing cathode ray tube displays. The provided signals are employed to activate appropriate means for modifying sine and cosine signals for application to the cathode ray tube vertical and horizontal deflection means for appropriately deflecting the tube beam to cause it to trace selected digits. Appropriate modification of the O sine and cosine signals merely involves selecting either a full or half value amplitude and either a normal or re Verse polarity and then impressing that modified signal upon either a full or half valued direct current bias level which can also be either positive or negative. It should be 5 apparent that in deflecting the cathode ray tube beam, it will not always move with constant speed in tracing Various parts of the various figures and as a consequence noticeable intensity variations may occur. By providing a feedback System for varying the intensity in accordance 20 With the applied voltages, these intensity variations can be --PDDs-- (P --Pa-P3--PA) D2- (P1-P2 --P--P) D4--(P1--P2--Pa--PA) D5 Gory avoided. What is claimed is: - 1. In combination with a source of pulse signals, each signal randomly occurring during a different one of suc =P(Do--Ds--D) -- (P --P2) (D4--D5 25 cessive bit periods, means for counting the total number --(P--Pa-Ps--P4) (D) of pulse signals occurring during each of a plurality of =Po(D8--D3--D6--D9--D2+D4+D.)--PD (Do --D--D1) -- (P1--Pah-Pa-PA) (Ds--Ds--D6 Successive digit periods, each digit period comprised of --D) -- (P --P4--Ps--Pg--P1--Pa.) D4--(P5 a predetermined number of bit periods, and for displaying a plurality of digits, each digit representing the total num --Ps--P--Ps) D-- (Ps--Pa--Ps--Ps--Pt) D5 30 =P(D--D3) -- (P1--P2--Pa--PA) D2-- (Ps--Pg ber of pulses counted during a different digit period, said means including: --P--P) (Ds--Ds)--(P3--Pa-Ps) D5 a first counter; Thus, it should be recognized that the signals developed means for incrementing said first counter in response to at junction 78 by both the X and Y signal modifying ap each of said pulse signals; paratus are useful for causing the beam to trace a digit 35 a second counter; designated by the energized output terminal of encoding means for clearing said first counter and for transfer circuit 42 of FIGURE 1, in an elemental area whose posi ring the count therein to said second counter once tion is designated by the states of the W and D counters. during each of said digit periods; That is, it will be recalled that for each state of the W means having a plurality of output terminals counter, the contents of a different one of the registers 40 decoding and responsive to each possible count in said second is applied to the N counter and through the Q counter to counter for energizing a different one of said output the decoding circuit 42. It should also be recalled that terminals; for each successive state of the D counter, information means for generating sine wave and cosine wave signals; representing successive digits stored in each register is ac first and second signal modifying circuits each having cessed. Thus, by causing the state of the W counter to 45 an input terminal and an output terminal; control the vertical position of the elemental area, and means responsive to the energized decoding means out by causing the state of the D counter to control the hori put terminal for selectively applying either said sine Zontal position of the elemental area, all of the digits in each register can be displayed as they would be conven tionally written, i.e. in a horizontally extending line. The 50 Wave signal or said cosine wave signal to the input terminals of said first and second signal modifying means in each of said signal modifying circuits respon circuits during each of said bit periods; contents of each of the registers would be vertically spaced from one another as a result of the output of the W counter controlling the vertical deflection means. FIG URE 4 illustrates the apparatus for coupling the deflec tion signals to the display cathode ray tube 12. The out 55 put of the W and D counters 20 and 18 are respectively applied to the inputs of digital-to-analog converters 150 and 152. The outputs of the digital-to-analog converters 150 and 152 are respectively applied to the inputs of adder circuits 154 and 156. The output of amplifiers 126 asso 60 ciated with the Y and X signal modifying apparatus re sive to said energized output terminal for selectively reducing the amplitude of the signal applied thereto during each of said bit periods; means in each of said signal modifying circuits respon Sive to said energized output terminal for selectively reversing the polarity of the signal applied thereto during each of said bit periods; means in each of said signal modifying circuits respon sive to said energized output terminal for applying output of adder 156 is connected to the horizontal deflec 65 a cathode ray tube including beam generating means and horizontal and vertical beam deflecting means; Spectively are also coupled to the inputs of adder circuits 154 and 156. The output of adder circuit 154 is cou pled to the vertical deflection means of tube 12 and the tion means thereof. a Selected direct current bias level signal to the corre Sponding signal modifying circuit output terminal during each of said bit periods; and The output of gate GBLANK referred to in Table I is means for respectively coupling said first and second connected to the input of a blanking circuit 158 which is signal modifying circuit output terminals to said connected to a control grid in tube 12 for selectively horizontal and vertical deflecting means. blanking the display. 70 From the foregoing, it should be appreciated that a dis 2. The combination of claim 1 wherein said source of pulse signals comprises a cyclic memory including a play apparatus has herein been provided which can be suit ably used with a source of serially supplied pulses wherein plurality of register tracks and a clock track, each track the total number of pulses supplied during each digit having a readout means coupled thereto; period represents a digit to be displayed. The source of 75 Switching means for successively coupling a different 3,305,843 register track readout means to said first counter; a cyclic bit counter; means responsive to pulses stored on said clock track for incrementing said bit counter; 5 a cyclic digit counter; and means responsive to each cycle of said bit counter for incrementing said digit counter. 3. The combination of claim 2 wherein said means 2 periods, either said sine wave signal or said cosine wave signal to said input terminals of said horizon tal and vertical signal modifying circuits; first logic means in each of said signal modifying cir cuits responsive to each of said plurality of different numeric signals for selectively reducing the ampli tude of the signal applied thereto during each of said periods; second logic means in each of said signal modifying circuits responsive to each of said plurality of differ ent numeric signals for selectively reversing the polarity of the signal applied thereto during each of said periods; third logic means in each of said signal modifying cir cuits responsive to each of said plurality of differ ent numeric signals for applying a selected direct current bias level signal to each of said signal modi fying circuit output terminals; and means for respectively connecting said horizontal and vertical signal modifying circuit output terminals to said horizontal and vertical beam deflecting means. for generating said sine wave and cosine wave signals includes filter means coupled to said bit counter. 10 4. The combination of claim 2 including a cyclic word counter; means responsive to each cycle of said digit counter for incrementing said word counter; and means coupling said word counter to said Switching 15 means for causing a different register track readout means to be coupled to said first counter in re sponse to each different state of said word counter. 5. The combination of claim 4 including first and second digital-to-analog converters respectively coupled 20 to the output of said digit and word counters; and 7. The combination of claim 6 wherein each of said means respectively coupling the output of said first and second digital-to-analog converters to said horizontal signal modifying circuits includes first and second im pedance networks, each having at least two parallel cir and vertical deflecting means. 6. Display apparatus responsive to each of a plurality 25 cuit branches having different impedance values; means in each of said signal modifying circuits for of different numeric signals applied thereto for display a