Schematic · c. 1980
Radio Shack's service manual for the TRS-80 Pocket Computer (26-3501) and Cassette Interface (26-3503), with Radio Shack part numbers: specifications, block diagram, signals, disassembly, cassette tests, check program, schematics and parts lists.
Radice Shaek Service lVianua TRS-80 Pocket Computer and Cassette Interface abe PRES SS + . 26-3501 Catalog Number: 26-3503 CUSTOM MANUFACTURED FOR RADIO SHACK BSA DIVISION OF TANDY CORPORATION €OSE/LOSE-92 TABLE OF CONTENTS Lay Ge EIA I 5 ig 0 sa 5554 fe HRN UAE Wa SINAN ONS OE RE 1 2. BLOCK TAAGR AR oii sae sis 5 SS Se Oe 8 Oe LEE SIGNAL DESCRIPTIONS |e: 26:0 5:0:sas w aib ae mes eRe SRA EER SRNR AOS. 10 A: WEPORE SERVICING 555i eee CE US ASSES ORS SS 14 5. CASSRTTE: TAPE 0 TRETERE AGE «0. «..0:0:6:6:0-0-0:0 418: 9:016 60:60 sie Wig sae aip acne 14 6, CASERT TE CPRRATI oo iets awe ewesebaw WET eae Kanes eee wae 15 7: CHORE, FROIN 3 odoin we tn s © She eae ee ' 29 8. CIRCUIT DIAGRAM PARTS & SIGNALS POSITION ................044. Openstbon GU Magra 66 eee etree eer sese eect sescwsceses 28 SPR T AGN. fh isesie wkseNiais eA WA CESS WASHES SSUES ERR 24 EGY CHOU 66 s.din.o 0.0.6. 6.5.0.0.9.0.8,6.0)0.5.0,0/6 00.568 KAS 86d 86 e 8 ee 5 8b 25 LC te Sore rire ere Tree Tere eT Tee Ree eT Tre ea 26 RO SIIS CECA GUI v5 so 650 '0'ni0'n 800 0 9:00.60604. 20005-4000, 5.0500-04 27 DR GIUARTTRE 65.0 WO Ne CNTR A NAAM EW EL hea eee 27 Di PARTS EAST FOR SOB OOl cise passivica Sint ieee es sie cisea waaswewn 28 ID FARIS LST POR 266908 ss 956 606saess neces cesicemeswweaeen a2 1. SPECIFICATIONS CAT RREAR (rv) (2) le} CO Oy tw] @ (Ce) Ce) (7) ' * + : ES . | _ Rr os en SS ' Lo) fej) [4] (8) [6 %*| NODE Fe] {eo] tw} | K f.l fell ; fond } ot } J l if if J 2 1 2 3 a | ll @J ij) © © & ™@ we |l_enren | ms | suxamcevs] (0) (2) fey (+) [e5 Display © Display tube: LF8017JE ® Display method: 5 x 7 dot matrix liquid crystal © Display capacity: 24 columns (alphanumerics and symbols) Basic functions @ Computational capacity: 12 digits of mantissa and 2 digits of exponent. @ Computational method: According to mathematical formula (with priority consideration and judge function) © Capacities: Program memory; 1424 steps, max Data memory; Fixed memory 26 memories Flexible memory (commonly usable with the program memory) 178 memories, max Reserve program; 18 kinds, 48 steps, max Input buffer: 80 steps @ Buffers: Data buffer: 8 stages Functional buffer; 16 stages (but 15 stages for parenthesis) Subroutine buffer: 4 stages “FOR NEXT” stagement buffer: 4 stages Arithmetic functions Add (+}, Subtract (—), Multiply (+), Divide (/), Power raising (A) Trigonometric function: SIN (sine}, COS (cosine), TAN (tangent) Inverse trigonometric functions: ASN (sine *), ACS (cosine), ATN (tangent “') Logarithmic functions: LOG (common logarithm), LN (natural logarithm [In] ) Exponential functions EXP (exponential) Angular transformations: DMS (decimal notation to sexagesimal notation), DEG (sexagesimal notation to decimal notation) Square root extraction: Vv Signum function: SGN Absolute value: ABS (|X|) Integration INT Execution of arithmetic operation is commanded by the ENTER key, Editorial functions Cursor shift: > (right), < (left) Insertion INS Deletion: DEL Line control 4 (down), t (up) Programming language BASIC (Beginner's All purpose Symbolic Instruction Code) Power source Battery: Four MR44 (mercury batteries) Battery life: 300 hours Power consumption: O.011W Automatic power shutoff: About 6 minutes Miscellaneous Data protection: Program memory, data memory, reserve program memory Peripheral unit Audio cassette unit (recording/reading of the program memory, data memory and reserve program memory) Optional: 26-3503 (audio cassette interface) Physical dimensions: 17S(W) x 70(D) x 44(H) mm (6,8(W) x 2.7(D) x 1.7(H) inches) Weight: Approx. 170g (0.37 Ibs) ... 26-3501 Approx. 240g (0.53 Ibs) (with batteries) ... 26-3503 NR penton reread LN WA | BllA zs = v7 MMO = aan RA = ’ VA 5 aT dno ha Cob Blk 8 rer) { £ NO aM OX . "ns +1s sis [ yold~tole ii es aL ep 8 y= ay wy) Lehvas reper f ado ass ass” 1 nd 1 eos ip LED ans [ lf esa~eial era WS | r Of TYNOLLdO Eel ld 1 aya oa es] = I TYNOIS F.LOWA = =] = | +N~ 10 IWD a y "ta Viva ("td TOHINOD TYNOLLdO = r TYNOS ONIGVOT aes r We LW Cota | ory’ ev s TYNDIS ONIGHODTY t LW) = ny4u * 4 Ss any 1 o¢ fr» ry > aqagvo ! alla \ ALAAD Eyl bed he mt li Ed Bes ata : ta’ 2a + = | ey Bp od diy seideia Ex (ezree OS) bH-H 7 &xo0tS~-IS — ~ a 2 71 WVHSVIC YD0718 “2 System configuration (see the system block diagram) The system consists of the following components: . CPUL(SC43177) 41 . CPU I (SC43178) x 1 . 4K-bit RAM (TCS514P x 3) . Display chip (SC43125 x 3, with built-in RAM) . ZAND gate (TC401 1 UBP x 1) . ZAND 20R (1C4U0 19 BP x 1) . Inverter (TC4069BP x 1) - Quard Analog Switch Multiplexer (TC4066BP) . LCD (24-digit FEM dot LCD) . Key . Crystal (CSB2560) —OWUKARMN Pwr Brief overview of CPU | and CPU Ii The CPUs are provided with internal ROM, and the CPUs have the following assignments: cPul cPuU dg Key input routine Display processing routine Input buffer Computational result Error Acknowledgement of the remaining program One instruction to one program step additional incorporation Arithmetic routine Interpreter: Character generator Progiaui execute statement Cassette routine Cassette control statement Command statement Print routing Printer control (reserved) Buzzer Execution of manual operation | Recognition of printer (reserved) (____ Power shutoff control | Power off q [ Clock stop control J { Clock stop ] © The CPU I functions to read key-in data or read the instruction to be executed from the RAM, and decides what is to be done for the control of arithmetical operations (i.e,, control of arithmetic sequence, memorizing of arithmetical data, and its readout), or interpret the syntax of the BASIC instruction for deciding what is to be executed, or determines and prepares the information to be displayed, but CPU I does not perform any execution by itself, It only arranges the data and informa- tion in proper sequence and acts to provide instruction code to the CPU Il via the buffer. On the other hand, CPU II constant- ly receives execution instructions from CPU | via the transfer buffer and executes operations per each instruction or ex- changes data, depending on the situatiun. Although: it shares exccution functiuus and performs some auxiliary CPU roles, it does not perform any decision by itself. Eg: Actions of CPU | and CPU Ul at the time of key data entry. Entry of the eey-in data into the input butter Westructron to CPU HT (display) cpu tl Notitying completion of eperation 10) crut Decoding cof tha instruc. tne cru ob For manual operation of the Pocket Computer, the instruction code (key code) is written into the RAM in the display chip (input buffer) after information is put through the keyboard and converted into the instruction code by CPU 1, then this inst- ruction code (display) is transferred to the CPU Ul via the transter butter, As CPU 1 receives this instruction, CPU I then decodes this instruction (display) and executes display processing. Upon the completion of this processing, it notifies CPU I, and CPU confirms the completion of the task by the CPU Il before terminating their functions. 4 Overview of RAM Three C-MOS RAMs (1 ~ 3 chips, 4K bits each) plus RAM incorporated in the display chip are used in this Pocket Computer, as described below: ©@ Map of 4K-bit RAM 1536 Bytes Reserve program Program or flexible memory | Fixed memories (W ~2Z) stack Subroutine | FOR NEXT statement 048 1472 1504 stack Although RAM area is mainly shared by the program, data and reserve program memories, it is also used for the subroutine stack, FOR NEXT statement stack and fixed memories (W, X, Y, Z) Map of the RAM incorporated in the display chip There are three [K-bit RAMs (128 bytes each) incorporated in each display chip (SC43125)}, with the following contigura- ticns: DISPLAY CHIP | DISPLAY CHIP 2 DISPLAY CHIP 3 YOU 8-digit display buffer S-digit display buffer 8-digit display buffer 040 Transfer buffer 048 Fixed memories Fixed memories 80-step input buffer (A~K, LL memories) (L~¥V._11 memories) 128 S-digit display buffer 40 bytes of 8-digit display buffer is used as a display data buffer during displaying and also used as a buffer memory for arithmetical results during arithmetical operations. Fixed memory The total memory of 176 bytes (from the display chip 2 and 3) is used as a fixed memories, A~V (22 memories), Tmemory ) +bit r] b———__—_ 16 bits —______| Transfer buffer 8 bytes (1 memory equivalent) of Display Chip | is used as a transfer buffer for transactions of instructions between CPU I and CPU I. Input buffer Remaining 80 bytes (10 memories equivalent) of Display Chip | is used for the input buffer, as follows. 1, Any information entered through the keyboard is stored in this buffer, allowing up to 80 steps. 2. The display contents are stored by CPU 1. and CPU II selects data. 3. When an arithmetical instruction is entered, its procedure is stored in this buffer by CPU 1, and CPUH performs opera- tions according to the procedure. 4, When a program or reserve program is to be recorded or read out during the execution of the cassette control instruction, action takes place through this input buffer. Overview of Display The contents of the display as indicated by CPU 1 is received by CPU MT via the input buffer and are converted into respective character codes, they are transferred to the display buffer in the Display Chip through the address data bus © Designation of the display data The following structure is observed in the display buffer in the Display Chip. There are 8 x 40 = 320 bits (40 bytes) of area in the display Counter/ iff. the Displav C HAa—?* dacan buffer in the Display Chip | Eg: Display numerical “4" ‘ AS AT AG AS HG HT HONS Nels 2 A xoo01 0 0.0 Res Hl PPS 2 He °*OOsso00 -OOsSOs800 >OOsSO0080 ‘SSS ee8 *OOB8O000 = fC (ee | sie H6 0 S17 H7 1 mel $1S2 $3 $4 S5 a0 ( / F 0 i F ot Address it ij atk: ‘ig DI04 DIN2 DOs DLO a | re | Abel AS=0 The numeral “4” (to be displayed by CPU Il) is converted into the relevant character code and carried through on the address data bus. First, the segment Sl is selected with the address AS~AI “OOD00000" to store the dats DI04~ DIO1 “1000” in the display buffer (see above illustration). To store the second 4 bits of the data, only AS in the address in turned “I to make the address “00010000” to store data “0001”, In the same manner, address “OO0OCO0!" is selected for storing the first 4-bit data “0100” for segment S2 and the second 4-bit data "0001" is stored with the address "00010001". Timing Signals for Displaying “4” Hé Se rde i) H? $1 HA: Clock frequency for the counter. This signal is counted and decoded to perform synchronization with the common signal, H] ~H7, generated trom CPU H. DSIP: With high level of this signal, processing of display operation is indicated (RAM data designated by HI ~HB8 is sent out on S1~S40). The data stored in the display buffer is carried through S1~S40 (illustrated above) to be fed to the LCD. (To indicate “4” on the display, H4 and H4 are engaged for S1_H3 and H4 for §?, etc., through S6 ~ $40.) Overview of Power supply A 1000 8 GND 23 VA - MR44*4 - vu 9 VE — MOS FET c 7 ze s s as aT ST yp —OVDISP Relation between temperature and VDISP VG CPUD The liquid crystal reference voltage VDISP is generated by the above circuity to avoid blurred characters or contrast varia- tions that might degrade display performance (which would be caused by a slight voltage variation in the liquid crystal reference voltage VDISP). VDD is generated in CPU Il, referenced to VGG . The gate voltage of MOS FET is controlled by the 250K? pot to regulate the voltage for VDISP. The Thermistor is provided 1o compensate for Temperature variation. ”, Reference voltage VDISP is divided by resistor combinations to provide VA, VM and VB. VDISP: Low voltage for common signals (H! ~H7) for TCD VA High voltage for segment signals (S1 ~S40) VM: Intermediate voltage for common and segment signals VB: Low voltage for segment signals. NOTE: VA, ¥Mand VB become pulses, with an amplitude of several volts, due to the influence of the LSI Adjustment ot reterence voltage VDISP VDISP had been precisely adjusted to —3.74V at an ambient temperature of 20 C and —4.29V at OPC. If it is necessary to readjust the voltage after servicing the LCD or changing some components, be sure to look at the Display from a 30° angle (from vertical) while adjusting the pot. - Eve position ov va LL ; rr -18V - &.&8ms ——4 apy vM | | 2av r i Sere | a (See nay VDISP —--=-— =3.9V 3. LSI SIGNAL DESCRIPTIONS $C43177 (CPU |) Pin No. | Signal name} In/Out Description 1 Faa Out Chip Enable signal (RAM3 select signal) 2 F3a Out Chip Enable signal (RAM2 select signal) 3 Fla Out Chip Enable signal (RAM1 select signal) 4 Fla Out Chip Enable signal (Display chip | select signal, for input buffer and transfer buffer usage) — ene During display: Low er During vead-in: turns momentarily high ~ 6 Vea In Source voltage (“—"* voltage of battery) 7 Vac In 8 Xin In Basic clock (pulse signal, 256kHz) 9 TESTI ‘ i 10 TEST2 Connected to GND 1 RESET In All Reset Switch input Normally high but turns low when the All Resct Switch is pressed. 12 R/Wa Out RAM Data Read/Write signal Duringdisplay: High ee Pressing a key causes it to momentarily go low. = 13 biol In/Out Data Bus (for address designation of the input buffer and transfer buffer in RAM and 14 DIO2 In/Out Display Chip 1) 15 DIO3 In/Out During display: High AAA. 16 DIO3 In/Out During read-in: Low ——————» 7 Ba Out Address Bus (for address designation of the input buffer and transfer buffer in RAM 18 Bla Out and Display Chip 1). 19 Boa Out 20 BSa Out During display — — Momentary generation 21 Baa Ou 22 B3a Out During read-in yy 23 Bla Out a 24 Bla Out 30 GND In Source voltage (OV) 40 $1 6a Out Busy signal to CPU Il (High during execution in CPU I) During display: Low During read in: turns momentarily high 4} Sn Out Key Strobe signal, RAM Address signa! 42 Si Out Key Strobe signal, RAM Address signal 10 Pin No. | Signal name} = In/Out Description 43 St3 Out Key Strobe signal 44 $12 Out 45 Sit Out During display: High 46 S10 Out Pressing a key causes it to momentarily go low 47 $9 Out 48 $8 Out 49 S7 Out 50 $6 Out St Ss Out $2 MS Out 53 $3 Out 54 $2 Out 55 Kil In Key input signal 56 Ki2 In 57 Ki3 In During display: Low 58 Kid In Pressing a key Causes ii to momentarily go high 59 Slob In Busy signal of CPU Il (high during execution of CPU TI) (KiS) During display: Low ig Pressing a key causes it 10 momentarily go high $C43178 (CPU Il) Pin No. Signal In/Out Description 1 F4 Out Buzzer signal a seal aa When the buzzer is off: Low | | When the buzzer is on: High 2 F3 Out Chip Enable signal (Display chip 3 select signal) 3 F2 Out Chip Enable signal (Display chip 2 select signal) 4 Fl Out Chip Enable signal (Display chip 1 select signal) During display: Low pisasace During read-in: Turns momentarily high $ Vpp Out For liquid crystal drive voltage preparation (Vpp * Vag) 6 Voc In Source voltage (“—"’ voltage of the battery) 7 Voc In & Xin In Basic clock (Pulse signal, 256kHz) MW RESET In All Reset Switch input 12 R/W Out RAM Data Read/Write signa! During display: High During read-in. Turns momentarily low iM PinNo [Signal name] = In/Out Description 13 DiIo4 In/Out Data Bus (for data transaction between RAM and display chip) 14 DIO3 In/Out During display: High 15 bIOZ InjOut During read-in; Turns low ——____ \ \ \ \ \ \ \ 16 1) (8) In/Out ae 7 B8b Out Address Bus (for address designation of the display chip) 18 B7b Out During display: B1b = high, B2b = low, B3b =low, B4b=low, BSb= high, Bob = high, 19 B6éb Out B7b = Sow, B&b = low 20 BSb Out During read-in: Turns momentarily high 21 Bat Out \ 22 B3b Ce \ 23 B2b Out 24 Bib Out 25 HA Our Display signal (Common signal counting pulse) Generated during display | | 0.5ms 26 DISP Out Display command signal During display: High During execution: Low 27 VM In LCD display voltage (Intermediate voltage of the segment signal) 28 VA In LCD display voltage (High voltage of the segment signal) 29 GND In Supply voltage (OV) 30 H4 Out LCD common signals (backplate) 3 7 Out 32 H3 Out 33 H6 Out 34 H2 Out 35 HS Out 36 HI Out 37 Vpisp In LCD display voltage (Low voltage of the common signal) 38 VB In LCD display voltage (Low voltage of the segment signal) 39 S16 Out Busy signal to the CPU I (High during exceution in CPU Hl) During display: Low es Pressing a key causes it to momentarily go high. ——_———— 40 SIS Out Record signal to the cassette tape and print data. 41 S15 Out Remote signal to the MT- 42 $13 Out Busy signal to printer 43 $12 Out Expansion signal During display: Low ae ea ™ Pressing the CA (ON) key causes an instant pulse generation. ——— 12 Pin No | Signal name In/Out Description 49 36 Out For DEF symbol display (engaged: low, not engaged: high) 54 S! Our For symbol display (SHIFT, DFG, RAD, GRAD, RESERVE, PRO, RLIN) Same waveform as the segment signal. 55 Kil In CPU 1 Busy signal (High during execution in CPU I) (Sl6a) 56 Ki2 In Expansion signal To be connected to $12 (CPU 1). $7 Ki3 In Printer Busy signal Low when the printer js not operated. 58 Ki4 In Printer connection identifying signal. Low when the printer is not connected. 59 Kis in Cassette recall signal 60 Ki6 In ON key input signal. IC Pin-out TC4O1LUBP TC 4009 P { Quah 2- input positive NAND gate HEX iwerter ) 14 13 12 1b 1 4 & ‘ois 1g ie ote 8 Von oOnononon ooomnon ) eo) a oh eS 2: eS ee “ eS 8 TE GND TC MISBE TC 4068 BP ( Quid AND-OR select gate } ( Quad Uilateral swital Kho 13 1 Cin ne + { 4 IN oor OV ay 2 1o 2 1 20 W Cin _ | §—IN gy OUT ys att ? n Cin EIN Guy OUT 40 " 10 tz a eae 7o— Cin WIN gy OUT 4NE— 0 ao— 13 4. BEFORE SERVICING e Disassembly procedure 1. Remove 2 screws (a) and 2 screws (b). g 2. From the screw side. separate the upper cabinet from Screw (a) the lower cabinet (they are latched together at three points, A, B and C). Screw (ib) ——— a @ Repairing procedure 1. The back of the arithmetic printed board will be exposed after the removal of the lower cabinet. You can check the arithmetic printed board from the back. . Replacement of the CPU 1 is possible, 3, If the key printed board is to be checked, the arith- metic printed buad has to be bent at a right angle after removing the screws (d) and (e). Inspection of the CPU 1 is possible if the buzzer is removed after removing screw (c), 4. The key printed board can be dismounted by removing 9 screws (f) and 2 screws (g). Take care as you remove the printed board, so you don’t spill the key tops. tw Lateh « Replacement of the LSI 1. Only a very fine soldering pencil should be used for replacing the LSI. 2. Be sure to first remove the key printed board from the upper cabinet, if the LSI on the key printed board is to be removed. If the LSI is removed while the key printed board is on the upper cabinet, there 1s a possibility of deforming the key rubber with the heat of the soldering pencil, 3. Be surc to cut cach pin of the defective IC. e Measuring current consumption Power source voltage. 4.72V Current consumption: After pressing the ON key Under 85024 After pressing the OFF key: Under |2yA 5. CASSETTE TAPE & INTERFACE For details of operation and connection, refer to the Owner's Manual for the TRS-80 Pocket Computer. Notes on suitable recorders While Radio Shack's CTR-80A is the intended Cassette Recorder, others can be used. The following notes may be helpful: 1. Cassettes or open-reel types can be used. 2. Mic input jack must have an input impedance of | K or less, with a sensitivity level of at least 3mV. 3. Earphone output must have an output impedance of 10K or less and an output level of 1 volt or more. . Allowable distortion is +15%, with frequency response from 2 to 4kHz. > 14 6. CASSETTE OPERATION Recording Recording method 80 steps Contents of program of reserve prograss Recording format of program or reserve program mca Data memory recording format 7 . sc o Check sum code (after every 8 steps or one data memory.) & steps of program or reserve program ~ End code of recording = This gap, composed of all “Is”, is inserted at each line to fil! up the full 80 steps, during which time the next 80 steps of data to be input is prepared in the input buffer. § = All “Is” are recorded for a period of about 6 seconds in order to avoid non-recordable area located at the beginning of the tape; it also is used for cuing of the recording head. 6 = Program or reserve program name is indicated = File name = Data memory is indicated with this code 9= Area for one data memory. w whe ~ » Recording method Data “O” and “1" are identified by changing the frequency of the recording signal (F4"") DATA “0” il ] | | | | | | 2kilz 15 Recording signal (F4’") generation circuit F4 — ei F 4" ——> To Cassette Interface cassette modulation circuit (F4") Signa! waveform at the time of recording is to be recorded, $15 is set low and signa! F4 (clock pulse of = 4kHz) is output during that period. When a reeording signal “0” is to be recorded, $15 is set high and F4 output is inhibited during that period [at which time the reverse signal of HA (clock pulse of = 2kHz) is carried on the recording signal] . This signal is supplied to the MIC jack of the tape recorder via the modulation circuit of the Cassette Interface. When a recording signal “I Reproduction Output signal from the EAR jack of the tape recorder is amplified and shaped in the Schmitt circuit, to be input to CPU 1 through KiS terminal of CPU I). htt pie cPpul VW vw Sehrwtt corcuit Amplitict circuit 16 Remote control The Cassette Interface will contro! the REMOTE jack automatically for record, playback and verify commands 0.047pF gzaKn 4 t VV ? 2 4 6 Ain Q! . NR<ATIt a a oe oy A 2 MT SOKA 5s pre REMOTE © Ww Bin Al ‘MW : (S14) - TC4528RP 3 ; : 7 1 ' 0.0472" : u 470Kn / — Vos © 1 6] 14 * I ! = . ‘ ' a L2hin app RSA 455 ; I r ‘ \ " s fF 1 ? ‘iG GNDO Bin MW bas- eas a3 PT Tessar an The TC-4528P isa mono-stable multivibrator (to perform trigger and reset functions from the single chip). “A” outputs a pulse which is dependent on the time constant of CR at the falling edge of the input signal, and “B" outputs a pulse which is dependent on the time constant of CR at the rising edge of the input signal. The relay operates ON and OFF according to the current flow to the coil, and is activated when “A” is active and deactivated when “B” js active. Stertup of the cassette operation / Termination of the cassette operation QA Activation of the relay (cassette to start running) ™ Lf” Deactivation of the relay (cassette to stop running) ad 17 Testing the Cassette Interface 1. Writing test data into the Pocket Computor First enter test data to check the Interface. No. Read in Display Remarks 1 [MODE] ~ [MODE] > RESERVE] Display RESERVE mode. 2 NEW NEW_ RESERVE 3 > RESERVE 4 Z RESERVE 5 p, #[SHFT] VA¥[SHFT ]; A(204) Z:P.#¥AW;A(208) RESERVE 6 Z; PRINT # VAY; A(204) RESERVE 7 Xx. RESERVE 8 L # [SHFT] VAV[SHFT] ; A(204) X: L #¥AW; A(204)_ RESERVE 9 X: INPUT #¥A¥; A(204) RESERVE 10 RESERVE 11 A(204) : A(204) RESERVE 12 : A(204) 3 > DEF 14 > RUN 1s | [SHFT] [Spc] = 100 A(204)=100_ RUN 16 RUN 100 2. Checking the Cassette Interface Assumes that step | has already been executed. No. Read in Display Remarks 1 2 Connect the Cassette Interface to the tape recorder 3 Connect the Pocket Compwier to the Cassette Interface. 4 > RUN Make sure that RUN is on the display (use key) b > 7 RUN Position Tape correctly. 18 Read in Display Remarks 6 > RUN Press REC and PLAY button, 7 PRINT #¥A¥. A(204)_ = RUN 8 RUN The cassette will run and produce sound 9 I RUN The cassette will stop and sound will cease. 10 > RUN Rewind the tape to the beginning of the recording, HW > RUN Press PLAY button. 12 SHFT | X INPUT # ¥A ¥; A(204) RUN 13 ENTER RUN The cassette will run and produce sound. i4 > RUN The cassette will stop and sound will cease, 15 A(2U4) RUN 16 RUN 100. 17 RUN 100. Push STOP batton,. 18 OFF 19 Disconnect units and cables, 1. Inspection is required if any of following conditions occur” 1, If cassette starts to run at Step 6. 2. If cassette fails to run of no sound is heard at Step 8. 3. If cassette does not stop at Step 9. 4. If no sound is heard at Step 13. 1. Repeat the procedure if the following occurs: . ..” is displayed at Step 13, repeat operation from Step 10. If the same indication is still on the display, When “5 ...... repeat the procedure from Step 5 after entering “A(204)=100", If the same indication remains on the display even after this, detailed inspection is required. 2. When “100.” is not displayed at Step 16, repeat operation from Step 10. If the specific indication does not appear on the display. repeat the procedure from Step 5 after entering “A(204)=100". If the specific indication is not to appear on the display even after this, detailed inspection is required. 19 Repairing the Cassette Interface Program 10 °:PRINT #°p*; LAO ] : PAUSE 1 o7:G0TO0 io Use the following procedures to evaluate the Cassette Interface Plug Tape recorder No. Read in Display Ik | % Remarks ZAR .| REM], ae PHONE MIC OTE PLAY KEC STO! | Connect Computer to Interface. 2 > RUN 1@) Oo Determine recording location on the tape 3 > RUN 1@)] .@) oO o Oo Make sure that the tape does not run, qd CS.VA RUN 0 o Oo 8) Oo 5 ENTER RIN oO i Qo io) a The tape starts to nin and recording sound will be heard. 6 > RUN Oo 1@) Oo Oo The sound will cease and the tape will stop when “>"" is displayed. 7 > RUN Oo co) Rewind tape to the begin- ning uf the recording. 8 > RUN re) te) 6) oO 9 CLO.” |SHETIWA CLO."WA_ RUN Oo oO 16) oO 10 RUN oO Oo Oo oO The display contents will disappear, tape will start and sound will be pro- duced. it > RUN ° ° ie) 1@) Sound and tape will stop when “>” is displayed 12 RUN © = Connected or activated [NOTES] 1. Check the Computer, if the cassette tape keeps running in Step 3, fails to run in Step 5, or the tape does not stop in Step 6. 2, Check the recording circuit of the Interface if no recording sound is audible at Step 5. 3. If no sound is audible at Step 10, playback another recorded tape to check it sound is audible with that tape. If sound is not audible with that tape, check the reproducing circuil of the Interface. If sound is audible with the second tape, check the recording circuit of the Interface. No. Read in Display Remarks 1 RUN RUN. RUN No tape recorder motion. 2 ENTER |=*5 RUN Recording sound is audible. 3 RUN Recording sound ceases and “10.” is displayed for about | second. 4 RUN bs Sr Ae a ninvcdii i] | J l i] L ‘i | ain disptaysfe-!2 oly!" __-sfy-__--ofo '1 ——pe-——1e rbraie Y recording! \, display | F8cOrding Indisplay recording jn display #6 pin of TC4528 and #5 terminal of the relay Of [e— trees, in fl Nl i= Activation of the relay {cassette tape to start running) #10 pin of TC4528 and #3 terminal of the relay fe msec, min fl fl Deactivation of the relay (cassette tape tu stup) Cassette ON/OFF control must be properly executed when the above signals are observed during execution of program. 21 7. CHECK PROGRAM DISPLAY READ IN ife]sfa}s[el r[e]e [sofa [ie [as|ae]asfielaz | isfie [2 2 ee ' 3 5/9 [ENTER eee ee I FE IE 5 5 4 : or a | Bicentennial 4 a 5 1 p > SHAFT) © K (SHFT) [ENTER] PTE, 9, PSS ANON 3 SP é |_2 |SHFT) Pp: OPS HP 7 \(Snet)” s (SuFt]” [ENTER] 2: ¥z"’print "sg Y - 1 tee eee 8 3B E E P 2 [ENTER 3: BEEP 2. ‘ a a a t ttt} ++ + + t—t—-+—+—+-+- } +} 5 A a il Se = EE ace] a es u 0 +4 7 (SRTEs Fa tid 4 —" a a oe oe T TT a, a A Ta A w ee — 4 4 a 13 SE a Ee eh ee ee +4 +++ +--+ ++ +—+ +—++ ad NOTE Suen src) - ALS a ar Pe oe ne meen var On a is (et) s A 0 _- (ENTER RT EO eT WES Se ae t+ $+ +4 +—++—++-++-+-+ -+-+++ 16 R + [ENTER OK, : Cate 4+—++—4—4_+_- +44 —4- ~-+—+—_+_+4+_+_+ + - t +++ +++ + 4-4 18 NTER tp ttt tt ttt tt +—+—+- 4 ee oe . + 20 tte ttt ttt ttt = a er ee a ae ee ee oe a 22 4. 4. 4. 4 44 4 +t ttt + tt ttt = | A am aa 24 $$$} $$ 4 ppt tt +—+ 25 ft tt ttt ttt ttt ttt = + +—+_+—++--++_+++ ff 27 qt ttt tt ee 28 4 4 +114 4+} $$ +4 4-4-4444 + 29 te 30 Se er er ee ee ae Facial a oe tt + + 4+ + +++ + Ht 31 eT ee eee a ewe a ce $$ tp ttt tt tt tt ttt t 32 | a i ee ee ee Te a a eT ee LE a 33 a as ll aes Se a ea IR a 84 ae oo a sa a A 85 a6 a pt ot tp 4 tt tt 37 Ft ttt tt tt tt ttt 38 ® a ee ee — ttt tt ttt tt ttt ttt tt 39 + i_.-4. 4 — oS +—+—+ 40 SYMBOL C assete s )] 21] 22 [2a | 24 [Sart] pec] Rap [crap] per [RUN | Pro|fkye | PLAY REC |STur | REMOTR ——-—+ ro ‘i oO Le) e = 8:3 12) i@) PE ats - ( O 4. oa _ Ko) | Oo ce) — ae + t oO] Oo oO a a ee | i++ +-4 +— een KO) | Oo Oo fe) ) ttt ot sy e) o i > ere ; + 4. 4. 4 4 ©) x o ojo amare 4. 4 4 de ©) L = ++ 7 * @) ° ° ++-+-+ vee Bee V i t+-+—+4 COPE SE =) is) +++ Cae 2 e) (2) ++—+ ami ar) fe) e) ie) bon 4 } ma + + -+4— + 4. a ere +—+— Pn eee - + yy 4 i. t 44 4 ' +t 4 - a — o_o T a ¥ quand +++ oler eco + -t-p— + — + 4 4. 4 + —+—t+ + poy + . + pay atte toto se +—4 + 22 Circuit Diagram 23 8. CIRCUIT DIAGRAM PARTS i Cont rot natal ‘ $15 cnt ' ‘ sis Uf REMOTO Sigal 4 ! ' ' i ' | I | | | ! ! | ! ! | ' ' 1 Optien U4 i 1 ' ' ! ' 1 ' i} | | | 1 ' i | ' ' ! ! ' ' 1 1 ' ' . i ° 1 b 5 cece. oo wcCzz Kis 22 Fila \ 1K Wa 1 { Te se Te ier r---- os wsa200 183 Bet ' re 4 7 § ' 3 eee 1 U ae Ole =F { Beh fDi t ; wore] Joo tt 1 SKK KKK OF Le aan GL ; a > ; Asu2 hase “Bio +t 7 1 Yas —4s3 t : miss A 6 St sv 1 4s Oo iH . aI be Bsa “se ep) 619 Dios pee sip SEA3178 nostee ‘ “asi TE mand uf 8 Better View biol SiN BH r eae er + ee CPU Ol 1 { y ' pa Bea 7 nd 5 ' ' is ; a Ming we + per ities td ; on 1 5 te Kin i : 1 | 4 4 s ' a too Bea Pet OKA ' Tes uBr (ae | 1 ' \ it : ‘hee Qe cx 1 ™ ; ! | 1 a Eee gt You 1 | - | I _——} Va- PR PEERY var tie Vege a Fie & SIGNALS POSITION $i Fas be TC ser =i vw Lm ¥ 5 “ Sarr oar Treat Se It ‘nase Vpist rib rH Tesoene J ' =i" ! ' u ' KAM) | La L ressupxi ' ios ] 1 > LE rr ! 1k | = GND ' a¢ ff T ; ; $< 2: bases La = teed rey ro 4 S /00Ks: gh to wy > LAs Bn 4 ' = ' - 1 2K , ; ay Vorar Ye tA ’ ‘ 4 ' D+ 4 i | ' ' | ' 1A a WA Pn gq ice Me j OKs = 4 Q = hoKe = = SUPE pe RAAAAAA Operation P.C.B. Te4019F 12) Connector ($Pin) €n5 vosiss 1.6Mo, a ee ee ee Fe dha ele Bhs she We: le “Flo Fee” Out” Gn BP Hi Hz M3 AS AZ oft OR? HA WB OSTAI Ps Bra Bea Bou Sou RESET Fa Psa Kie Si Siea TOP VIEW Sn Swe Fea Fra Xm %wo bra Bsa Bsa Bia Fz a ye are a ‘1 BOTTOM VIEW 24 Key Circuit Pp) UA west 25 aaa wera 9 ogonese 8 ‘op 5 panosen ri 2 Q § paces! oppec ee ar a EI Ej <a cov poateas nose 2 3 "8 ‘a Boooa 2 5 =] a ¢ @ o uo a e@™, 5 bo 2. 8 Dponocoe BB gonacee Diffie a Litt 3 g 20ngenn iret bee] a ae a we a Ee888 — wocflene = t oo 3 = oo 9 £8 B Bs 25 8 “GR bs 2 3 4 ofan 8 o ooore 2 = § | 2 72 = T1 nol ime aS = } z 200, b pzeze” Pe fall a TTT et agodgaa a8 ‘a oo neta sa : - 17 e a% 2 5 = +4 Ma rf . Hi b | a . - . S «tthe ‘ = . ry = 1 : “0 sas 2 oe | — - . = ss wd ~ op — = Ks0< o> ~0« —+-O~ oO +O On # 0 | ees Ss geaceao C) oo. 2 orang62 Tes) 5 po oo ooo penser 9 3 ocecoo a a Senosec ot — 2 oopon a 2 o osooo Gaconn 3 a oo oo 8 58°. 290 §9°°R Snook S 4404 | MR. 4 Key P.C.B. E) @ a) OOoOg oo BOA OOOB BOO, i oag ooeag Deoae BOG AooE Aaa Hoa POS BOO is? are tes rt = azieros | (pigrnay iv Se et 2 Sei tro8 (otereay our aa is tH aH eH oH oY zy Gis 200 O10 vH Sid “A ~ ws a 4 og vg vee me ved “ix eld ved bf 26 Interface Circuit Diagram DSI S88L1 x2 ima : YSare s70Kn ; 1 ; ‘ KELUKE dapat 0 Osa? 9 SOW OL “pow = H (Fe) © i KA . ‘ mic oon pon 1 1K Ta H , ow 4 ’ DEIESSL *& enue 22k oka : mse O- Kix<hech —— (KIS) 1.087 2/500 Veh DRLSSSLt TU Mer “i i | 2SCH6KS : im ee Hosissets KEMUTS © Ww (sis) 80K DS1588L! Vea O 8 iwy OF josF ann © Interface P.C.B. OSISeaL 1x2 27 EAR PHONE 9. PARTS LIST FOR 26-3501 ng Description tenis ps rhs 1 Special screw (M2 x 13) AHD-1586 LX -BZ1084CCZz 2 Special screw (M2 x 5) AHD-1587 LX-BZ1032CC2Z 3 Bottom cabinet AZ-5633 HDECA1765CCZz 4 Insulator sheet AHB-9950 PZETL1355CCZZ 5 Tape for intertace lock plate AHB-9951 PTPEH1062CCzz 6 Interfare lock plate Az-5634 LCHSS1091CCzz 7 Lid for interface lock plate ADA-0314 GFTAA1 246CC2ZzZ 8 Screw (M2 x 9) AHU-1588 XBPSD20?09000 9 Buzzer 8-7073 RALMB1006CCzz 10 Special screw (M2 x 5) AHD-1589 LX-BZ1060CCzz n Screw (M2 x 5) AHD.1590 XTPSD20P05000 12 All reset switch AS-0692 OQCNTM1036CCzz 13 Cushion for reset switch AHB-9952 PCUSS1081CCZZ “4 Flexible wire (22 pin) AW-2521 OCNW.-1135CCzz 15 Connector (9 pin) for Cassette Interface AJ6831 QCNCW1259CCDi 16 Rubber connector for LCD ART-2985 | PGUMS1190CCzz 7 tcp AL-1180 | VVLLF80I7JE1 18 Tape for LCD AHB.9953 PTPEH1033CCZZ 19 | Frame for LCD ART-2986 LANGK 12900Czz 20 Filter for LCD AG-0430 PFiLW1230CCzz 21 Display mask ART-2987 HDECA15270CZz 22 Display filter ART-2991 PFiLWI22aCC77 | 23 Key rubber ART-2988 _ PGUMM1254cCzz 24 Ground spring ARB.6823 MSPRC1098CCzz 25 Key top (18 key) (Left halves} AK-4274 JKNBZ1515CC04 26 Key top (17 key) (Right halves) AK-4275 JKNBZ151 5cco05 | 27 Key top (SHFT) (2C pes/1 set) AK-4219 JKNBZ1516CC02 | 28 Key top (ENTER) (10 pcs/1 set) AK-4220 JKNBZ1566CC01 29 Key top (Numeral) AK-4221 JKNBZ1621CCO1 30 Key top (CL) (20pes/1 set) AK-4222 ‘JKNBZ1622CC01 | 31 | Battery terminal (+, —) AHB-9954 QTANZI2RICC77Z | 32 Battery terminal (+) AHB-9955 QTANZ1292CCzz | 33 Battery terminal (—) AHB 9056 QTANZ1250CCz2 | 34 Screw (M2 x 4) AHD-1591 X USSD20P04000 36 Bracket for bottom cabinet AHB-9957 LANG11336CCZZ | 36 Top cabinet AZ.5635 CCABB2381CCO1 | 37 Lid tor connector ADA-0315, GFTAA1245CCZZ 38 Flexible wire (8 pin} AW-2522 OCNW-1137CCzz 39 Soft case AZ-5636 UBAGC1230CCzz 28 Fc (i ru 1/BW 470K 5% Ref — RS Manufacturer No Desription Location Part Number 40 Badge AHB-9961 HBDGE 1341CC2Z 41 Battery terminal (+, —) AHB-9958 QTANZ1293CCZZ = PCB (Key unit} AX-8546 DUNTK5567CC22 PCB (CPU unit) AX-8547 OUNTK5568CC22 Template AHB-9959 LPLTP1070CCZ2 Name label AHB-9960 TLABZ1295CC2ZZ Carbon resistor ANO583C8B RR-D2Z1006CC22 1/8W 143K 2% } : Carbon resistor ANOS84CBB RR-DZ1007CC2ZZ 1/8W 12.7K 2% Carbon resistor ANO308CBB RR-DZ1008CCZZ 1/8W 21K 2% Variable resistor (250K) AP-7105 RVR-MB5100CZZ Capacitor (Flectralytic) ACC1N52ZJCP VCEAAUIAW1070 100nF 10V +80/—20% Capacitor (Ceramic) ACC221KJCP VCKYPUTHB221K 220PF SOV +10% Diode, DS1588L1 ADX-1405 VHDDS1588L1-1 Thermister (150K) | AT-1218 VHH154KD-5/-1 LSI (Dieplay chip}, TC43125 | AXX-3032 ViliSC43125/-1 LSI (CPU-1), SC43177 | AXX.3033 VHISC43177/-1 LSI (CPU-2), SC43178 AXX-3034 VHiSC43178/-1 ic, TC4011UBP | AMX4439 VHITC4011UBP1 ic, TC4019P | AMX-4440 VHiTC4019P/.1 IC, TC4066P AMX-4441 VHiTC4066P/-1 Ic, TC4069P AMX4442 VHiTC4069P/-1 LSI (Ram) _ AXX-3035 VHITC5514P/-1__ Solid resistor ANOS536EBB VRC-MT2BG165J 1/8W 1.6Mohm 5% Carbon resistor ANO132E6B VRD-ST2BY101J 1/8W 100 ohm 5% Carbon resistor ANO311EBB VRD-ST2BY223J 1/8W 22K 5% Carbon resistor ANO281EBB VRD-ST2BY103J 1/8W 10K 5% Carbon resistor ANO371EBB VAD-ST2BY104) 1/8W 100K 5% Carbon resistor ANO445EBB VRD-ST2BY105J 1/BW 1Mohm 5% i Carbon Resistor ANO247EBB VRAD-ST2BY472) VBW 4.7K 5% Carbon resistor AN0423E88 VRD-ST2BY474J 29 1/8W 470K 5% Ref. : RS Manufacturer No. Description Location Part Number 40 Badge AHB-9961 HBDGE1341CCZZ 41 Battery terminal (+, —) AHB-9958 QTAN2Z1293CCZ22Z PCB (Key unit) AX-8546 DUNT K5567CCZ2 PCB (CPU unit) AX-8547 OUNTK5568CC22 Template AHB-9959 LPLTP1070CC22 Name !abel AHB-9960 TLAB2Z1295CC77 Carbon resistor ANO583CBB RA-DZ1006CCZZ W/BW 143K 2% Carbon resistor ANO0584CBB RA-DZ1007CCZ2Z2 WBW 12.7K 2% Carbon resistor ANO308CBB RR-DZ1008CC2Z 1/BW 21K 2% Variable resistor (250K} AP.7105 RVR-MB5100CZZ Capacitor {Electrolytic} ACC105ZJCP VCEAAUIAW1070 1OOHF 10V +80/—20% Capacitor (Ceramic) ACC221KJCP VCKYPU1HB221K 220PF SOV +10% Diode, 0S1588L1 ADX-1405 VHODDS1588L1-1 Thermister (150K) AT-1218 VHH154KD-5/-1 LSI (Display chip), TC43125 AXX-3032 VHiSC43125/ 1 LSI (CPU-1), SC43177 AXX-3033 VHiSC43177/-1 LS! (CPU-2}, SC43178 AXKX-3034 VHiISC43 1/8/-1 Ic, TC4011UBP AMX4439 VHiTC4011UBP1 ic, 1C4ao19P AMX-4440 VHiTC4019P/.1 IC, TC4066P AMX-4441 VHiTC4066P/-1 IC, TC4069P AMX4442 VHiTC4069P/.1 LSI (Ram) AXX3085 | VHITCS514P/-1 | Solid resistor ANO536EBB VRC-MT2BG 165) 1/8W 1.6Mohm 5% Carbon resistor ANO132E6B VAD-ST2BY101J 1/8W 1000hm 5% Carbon resistor ANO311E8B VRAD-ST2BY223J 1/BW 22K 5% Carbon resistor ANO281EBB VRD-ST2BY103J 1/8W 10K 5% Carbon resistor AN0371E6B VRD-ST2BY104J 1/8W 100K 5% Carbon resistor ANO445EBB VRD-ST2BY105J 1/8W 1Mohm 5% Carbon Resistor ANO247EBB VAD-ST2BY472) 1/8W 4.7K 5% Carbon resistor ANO423E8B VAD-ST2BY474J Ref RS Manufacturer No. ehhh ener Location Part Number Transistor 2SC458KS AA2SC458KS VS2SC458KS/-1 MOS FET 25540 AMX4443 VS2SJ40-///-1 Capacitor (Tantalum) ACC 104ZCTP RC-.$21005CCZZ O.1uF 10V +80/-20% Crystal (256 kHz) AMX-2780 RCRSP1024CC2Z2 Capacitor (Tantalum) ACC1IO1KJCP VCKYPUTHBIOIK 100pF 50V 210% Capacitor (Tantalum) ACC103MFTM VCTYPUIEX103M 10000pF 25V +20% Capacitor (Tantalum) ACC 105ZCTP RC-SZ1007CCzz 4uF 10V +80/-20% Carbon resistor ANO396E BB VRD-ST2BY224) 1/8W 220K 5% Capacitor (Ceramic} ACC102KJCP VCKYPU1HB102K 1000pF 50V 210% 30 mn) EXPLODED VIEWC 26-3501) 31 10. PARTS LIST FOR 26-3503 Ref. eel RS Manufacturer No. Deepen Location Part Number 1 Bottom cabinet AZ-5637 GCABA2389CC2Z 2 Special screw (M2 x 8) AHD-1592 LX-B21038CCZZ 3 Rubber foot AF.0294 Gt FGG1012CC77 4 Battery lid ADB-0356 GFTAB1247CC2Z 5 Screw (M2 x 6} AHD-1593 xX TOSD20P0G000 6 Plug with wires AW-2523 QPLGJ1008CC2ZZ cf Connector (9 pin) As-6833 QCNCM1260CCOi 8 Screw (M2 x 5) AHD.1594 XT BSD20P05000 9 Holder for lock plate LHLDZ1153CC2ZZ 10 Battery terminal (—) AHB-9962 QTANZ1266CC2Z W Battery terminal (+) AHB-9963 QTANZ1072CC2Z 12 Decoration panel A ART-2992 HDECA1775CC2Z 13 Decoration panel B ART-2993 HDECA1776CCZ2Z 4 Top cabinet AZ-5638 GCABB2390CC2Z Capacitor (Electrolytic) ACC106ZDAP VCEAAU1CW1060 1OuF 16V +80/—20% Capacitor (Mylar) ACC472KJMP VCOYKUTHM472K 0.0047uF 50V +10% Capacitor (Mylar) ACC473KJMP VCQYKU1HM473K 0.047uF 50V +10% Capacitor (Tantal) ACC103MFTP VCTYPU1EX103M 0.014F 25V +20% Capacitor (Tantal) ACC104MDTP VCTYPUINX104M O.1uMF 12V +20% Diode, DS1588L1 ADX-1405 VHODS1588L1-1 Relay AR-B127 VHINR5711//-1 Ic, TC4069P AMX-4442 VHiTC4069P/-1 IC, TC4526BP AMX-4444 VHiTC45286P-1 Carbon resistor ANO281EBB VRO-ST2BY103J 1/8W 10K 5% Carbon resistor ANO371EBB VROD-ST2BY 1045 1/B8W 100K 5% Carbon resistor ANO445EBB VRD-ST2BY105J 1/8W 1Mohm 5% Carbon resistor ANO303E8B VRD-ST2BY183J 1/B8W 1BK 5% Carbon resistor ANO3T1IEBB VRD-ST2BY2235 1/BW 22K 5% Carbon resistor ANO155E88 VRD-ST28Y271J 1/8W 2700hm 5% Carbon resistor AN0423EB8 VRD-ST2BY474J 1/BW 470K 5% 32 Ref RS Manufacturer No. Deseripxiont Location Part Number Carbon resistor AN0429EBB VRO-ST2BY564J 1/BW S60K 5% Carbon resistor ANOO87EEB | VRO-ST2EY330J 1/4W 33 ohm 5% _ | Cae __ |. Transistor 2SA733 AA2SA733 VS2SA733-//-1 Transistor 2SC458KS AA2SC458KS VS2SC458KS/-1 33 EXPLODED VIEW(C 26-3503) 34