Datasheet · 1976
TI TMS 1000 Series Data Manual (December 1976)
TI's data manual for the TMS1000 microcomputer family, including the high-voltage TMS1070 and TMS1270 that drive fluorescent displays directly, with a strobed VFD interconnect diagram.
Datasheet · 1976
TI's data manual for the TMS1000 microcomputer family, including the high-voltage TMS1070 and TMS1270 that drive fluorescent displays directly, with a strobed VFD interconnect diagram.
Information contained in this publication is believed to be accurate and reliable'. 'However, responsibility is- assumed neither for its use flor for any infringement of patents or rights· of others that may results from its use. No license is granted by lmplication or otherwise under any patent or patent right of Texas Instruments or others. Copyright © 1976 Texas Instruments Incorporated TABLE OF CONTENTS 1. THE ONE-CHIP MICROCOMPUTERS FROM TEXAS INSTRUMENTS 1.1 Description. . 3 1.2 Design Support 3 1.3 Applications . 5 2. TMS 1000/1200 AND TMS 1070/1270 MICROCOMPUTERS 2.1 Introduction . 6 2.2 ROM Operation . . . . . . 7 2.3 RAM Operation . . . . . . 7 2.4 Arithmetic Logic Unit Operation 7 2.5 Input. . . . . . . . . . 8 2.6 Output . . . . . . . . . 8 2.7 The Instruction Programmable Logic Array 8 2.8 Timing Relationships 8 2.9 Software Summary 10 2.10 Sample Program 11 2.11 Power·On . . . 14 3. TMS 1100 AND TMS 1300 MICROCOMPUTERS 3.1 I ntrod uction . 15 3.2 ROM Operation 16 3.3 RAM Operation 17 3.4 Output . . . 17 4. TMS 1000/1200 AND TMS 1100/1300 ELECTRICAL AND MECHANICAL SPECIFICATIONS 4.1 Absolute Maximum Ratings . . . 18 4.2 Recommended Operating Conditions 18 4.3 Electrical Characteristics . . . 19 4.4 Schematics of I nputs and Outputs 19 4.5 Internal or External Clock. . . 20 4.6 Typical Buffer Characteristics 20 4.7 Output, Input, and Instruction Timing. 21 4.8 Interface Between Low·Power Schottky and TMS 1000 22 4.9 Interface Between Standard TTL and TMS 1000 23 4.10 Interface Between Open·Collector TTL and MOS 24 4.11 Interface Between CMOS and TMS 1000 . 25 4.12 Typical Scanned LED Interface . 26 4.13 Terminal Assignments . . . . . . . 26 5. TMS 1070 AND TMS 1270 MICROCOMPUTERS 5.1 I ntrod uction . . . . . 27 5.2 Design Support . . . . . . . 27 5.3 Absolute Maximum Ratings . . . 28 5.4 Recommended Operating Conditions 28 5.5 Electrical Characteristics 29 5.6 Terminal Assignments . . . . . 29 6. MICROCOMPUTER SYSTEM EVALUATORS, SE-1 AND SE-2 6.1 I ntrod uction . . . . . 30 6.2 Operation . . . . . . 30 6.3 Absolute Maximum Ratings 34 TABLE OF CONTENTS (Continued) 6.4 Recommended Operating Conditions 34 6.5 ,Electrical Characteristics . . . 34 6.6 Schematics of I nputs and Outputs 35 6.7 Internal or External Clock. . 35 6.8 Terminal Assignments . . . 36 6.9 Terminal Function Description 36 7. HE-2 HARDWARE EVALUATOR 7.1 Introduction . . . . . . 37 7.2 Controls and Front Panel . . 37 7.3 Electrical and Mechanical Features 38 7.4 Connector Pin Assignments 38 8. MECHANICAL DATA 8.1 TMS 1000 NL, TMS 1070 NL, TMS 1100 NL - 28·Pin Plastic Package - Inch/Metric 39 8.2 TMS 1200 NL, TMS 1270 NL, TMS 1300 NL - 40·Pin Plastic Package - Inch/Metric 40 8.3 TMS 1000 JL, TMS 1070 JL, TMS 1100JL - 28·Pin Ceramic Package - Inch/Metric 41 8.4 TMS 1200 JL, TMS 1270 JL, TMS 1300JL - 40·Pin Ceramic Package - Inch/Metric 42 8.5 TMS 1099 JL/SE·l, TMS 1098 JL/SE·2 - Inch/Metric . . . . . . . . . . 43 LIST OF ILLUSTRATIONS Figure 1 TMS 1000 Series Algorithm Development . . . . . . 4 Figure 2 Block Diagram of Typical Application - Terminal Controller 5 Figure 3 TMS 1000/1200 Logic Blocks . . . . . . . . . 6 Figure 4 ALU and Associated Data Paths. . . . . . . . • . 7 Figure 5 oOutput PLA for Binary and Seven·Segment Encoding. . 9 Figure 6 Machine Instruction Flowchart - BCD·Addition Subroutine 13 Figure 7 TMS 1100/1300 Logic Blocks 15 Figure 8 Externally Driven Clock I nput Waveform. . . . . . . 18 Figure 9 Strobed Fluorescent Display Interconnect . . . . . . 27 Figure 10 Block Diagram of Typical Application - Prototyping System with SE·l 31 Figure 11 Block Diagram of Typical Application - Prototyping System with SE·2 32 Figure 12 Block Diagram of Typical Prototyping Systems Using the TMS 27081024 by 8·Bit Erasable, Programmable Read·Only Memory. . . 33 Figure 13 .Externally Driven Clock Input Waveform 35 LIST OF TABLES Table 1 4·Bit Microcomputer Features ......... . 3 Table 2 TMS 1000/1200 and TMS 1070/1270 Standard Instruction Set 9 Table 3 TMS 1100/1300 Standard I nstruction Set 15 Table 4 System Evaluators SE·' and SE·2 28 2 1. THE ONE-CHIP MICROCOMPUTERS FROM TEXAS INSTRUMENTS 1.1 DESCRIPTION The TMS 1000 series is a family of P-channel MOS four-bit microcomputers with a ROM, a RAM, and an arithmetic logic unit on a single semiconductor chip. The TMS 1000 family is unique in the field of microprocessors because this device is a single·chip binary microcomputer. A customer's specification determines the software that is reproduced during wafer processing by a single-level mask technique that defines a fixed ROM pattern. As summarized in Table 1, the TMS 1000 and TMS 1200 are the basic 1024'instruction ROM microcomputers. The TMS 1070 and TMS 1270 interface directly to high·voltage displays and use instructions identical to the TMS 1000/1200 devices. To increase the software capacity in one chip, the TMS 1100 and TMS 1300 provide twice the ROM and RAM size of the TMS 1000/1200. The design support for the entire series includes software assembler and simulator, hardware simulator with debl!g control, and system evaluator devices for prototype fabrication. TABLE 1 4·BIT MICROCOMPUTER FEATURES I TMS 1000 TMS 1200 TMS 1070 TMS 1270 I TMS 1100 TMS 1300 Package Pin Count 28 Pins I 40 Pins 28 Pins 40 Pins 28 Pins I 40 Pins Instruction Read Only Memory 1024 X 8 Bits (8,192 Bits) 1024 X 8 8its (8,192 Bits) 2048 X 8 Bits (16,384 Bits) Data Random Access Memory 64 X 4 Bits (256 Bits) 64 X 4 Bits (256 Bits) 128 X 4 Bits (512 Bits) "R" Individually Addressed Output Latches "0" Parallel Latched Data 11 I 8 Bits 13 11 8 Bits 13 "10 Bits 11 I 8 Bits 16 Outputs Maximum·Rated Voltage (0, R, 20 V 35 V 20 V and K) Working Registers 2-4 Bits Each 2-4 Bits Each 2-4 Bits Each Instruction Set See Table 2, Page 9 See Table 2, Page 9 See Table 3, Page 15 Programmable Instruction Ves Ves Ves Decoder On-Chip Oscillator Ves Ves Ves Power Supply ITypical Dissipation 15 V/68 mW 15 V/90 mW 15 V/l05 mW Time-Share Assembler Support Ves Ves Ves Time-Share Simulator Support Ves Ves Ves Hardware Evaluator and HE·2 HE·2 HE·2 Debugging Unit System Evaluator Device with SE·l SE·l SE-2 External I nstruction Memory (TMS 1099 J U (TMS 1099JU (TMS 1098 JU ... The H E-2 does not have a decoder for the extra a outputs. 1.2 DESIGN SUPPORT Through a staff of experienced application programmers, Texas Instruments will, upon request, assist customers in evaluating applications, in training deSigners to program the TMS 1000 series,and in simulating programs. TI will also contract to write programs to customer's specifications. TI developed assemblers and simulators for aiding software designs. These assembler and simulator programs are available on nationwide time-sharing systems and at TI computer facilities. 1276 3 A TMS 1000 series program (see flowchart, Figure 1) is written in assembly language using standard mnemonics. The assembler converts the source code (assembly language program) into machine code, which is transferred to a software simulation program. Also, the assembler produces a machine code object deck. The object deck is used to produce a tape for hardware simulation or a tape for generating prototype tooling. The TMS 1000 series programs are checked by software and hardware simulation. The software simulation offers the advantages of printed outputs for instruction traces or periodic outputs. The hardware simulation offers the designer the advantages of real-time simulation and testing asynchronous inputs. After the algorithms have been checked and approved by the customer, the final object code and machine option statements are supplied to TI. A gate mask is generated and slices produced. After assembly and testing, the prototypes are shipped to the customer for approval. Upon receiving fi nal approval, the part is released for volume production at the required rate as one unique version of the TMS 1000 family. r- I I 1 I I 1 r=l---.----.l'----,------------.,----.,J : ~ i ! I 5ia I I i I I I 1_ _ _ _ _ _ _ -'I r 1-__. ___________ 1 1 I 1 I l " I [:] HE., EDIT W" ;,:0.. ;:: i L.--.,Lr-_-_~____ -Ii ANALYZE t~~ ,...,...•.,.. (7E1ffl~ '.:./~ i I fr---L--~ I --- .' V,ROM I I "',__0~~:,,->-- __________ J : L __ ~-......J I HARDWARE SIMULATION , I "RELEASE FORM AND OBJECT DECK ARE NORMALl Y TRANSMITTED VIA THE TIMESHARE NETWORK CHOSEN BY THE CUSTOMER FOR SOFTWARE DEVELOP- MENT. WHEN TI DEVELOPS THE SOFTWARE, THE CUSTOMER AND TI COOPERATE IN THE FINAL CHECK· OUT PRIOR TO AN OBJECT DECK RELEASE. FIGURE 1 - TMS 1000 SERIES ALGORITHM DEVELOPMENT 4 1276 1.3 APPLICATIONS One major advantage of the TMS 1000 series is flexibility. The TMS 1000 series is effective in applications such as printer controllers, data terminals, remote sensing systems, cash registers, appliance controls, and automotive applications. A data terminal is a useful example. In Figure 2, a sample interconnect diagram shows how the R outputs control a universal asynchronous receiver/transmitter (UART), display scan, and keyboard scan. The ROM controls data output to the appropriate display digit or to the transmitter section of the UART. A routine in the ROM program controls selection of incoming data through the K·input ports. Two dedicated R outputs (load and ready reset) control the UART's transmit and receive modes. The remaining R outputs both scan the display and select inputs. The SN74157 TTL devices multiplex eight bits of the incoming data word, four bits of UART status,and the four key input lines. Through the TMS 1000 series' versatility, a wide range of systems realize reduced costs, fewer parts, and high reliability. LINE INTERFACE 11·DIGIT DISPLAY +-- 8 IREFERENC~I DISPLAY DRIVERS IOSCILLATOR KEY MATRIX I (32) ~ READY RESET I + I ~ XMTR I RECEIVER I TMS 6011 UART ~ V LOAD I FLAGS - I 8 I DATA I~ r-----4 ,R12 RO, v R OUTPUTS o OUTPUTS - (:I OSCl <t TMS 1200 -' .... ..jLDD OSC2 > l- ll. :;;: w K INPUTS 1 Vss 3 LOW/HIGH ORDER 4 .1 4 KEY SELECT .... In SN74157 :;; - .... tn~ Z 4/ CIl 4 4 :;; .... z 4 - CIl --- FLAG SELECT f NOTE: Discrete components for level shifting and other functions are not shown. FIGURE 2 - BLOCK DIAGRAM OF TYPICAL APPLICATION-TERMINAL CONTROLLER 5 2. TMS 1000/1200 AND TMS 1070/1270 MICROCOMPUTERS 2.1 INTRODUCTION The TMS 1000/1200 and TMS 1070/1270 are identical except for maximum voltage ratings for the K inputs and the 0 and R outputs, and the TMS 1270 has a total of ten 0 outputs. See Section 5 for a TMS 1070/1270 description. The microcomputer's ROM program controls data input, storage, processing, and output. Data processing takes place in the arithmetic logic unit. K input data goes into the ALU, as shown in Figure 3, and is stored in the four-bit accumulator. The accumulator output accesses the output latches, the RAM storage cells, and the adder input. Data storage in the 256-bit RAM is organized into 64 words, four bits per word. The four-bit words are conveniently grouped into four 16-word files addressed by a two-bit register. A four-bit register addresses one of the 16 words in a file by ROM control. The a outputs and the R outputs are the output channels. The eight parallel a outputs are decoded from five data latches. The a outputs serve many applications because the decoder is a programmable logic array (PLA) that is modified by changing the gate-level mask tooling. Each of the thirteen R outputs of the TMS 1200 and the eleven R outputs on the TMS 1000 has an individual storage element that can be set or reset by program control. The R outputs send status or enable signals to external devices. The R outputs strobe the a outputs to displays, to other TMS 1000 series chips, or to TTL and other interface circuits. The same R outputs multiplex data into the K inputs whenever necessary. There are 43 basic instructions that handle I/O, constant data from the ROM, bit control, internal data transfer, arithmetic processing, branching, looping, and subroutines. The eight-bit instruction word performs 256 unique operations for maximum efficiency. Section 2.9 defines the standard instruction set, which is optimized for most programs. Microprogramming for special appl ications is possible, and the operations of the instruction set can be modified by the same mask-tooling step that programs the ROM and the a output PLA. R OUTPUTS ('1 OR 13 BITS) 6 PROGRAM COUNTER - ROM R-OUTPUT RAM SUBROUTINE RETURN REGISTER 6 1024 WORDS 8 BITS/WORD LATCH & BUFFER 64 WORDS 4 BITS/WORD I- , ,- PAGE ADDRESS , REGISTER 4 8 2 1" U {2 t '-1 4/. PAGE BUFFER 4 REGISTER 8 4 I X-REGISTER ~ INSTRUCTION DECODER 4 4 I 4 L ~ V-REGISTER ~ ARITHMETIC OSCILLATOR 4 LOGIC l UNIT 4 4 K INPUTS (4 BITS) ¢ ACCUMULATOR} 1 i 4 REGISTER I Q-OUTPUT LATCHES & PLA CODe CONVERTER 4 J o OUTPUTS (8 BITS) FIGURE 3 - TMS 1000/1200 LOGIC BLOCKS 6 2.2 ROM OPERATION The sequence of the 1024 eight-bit ROM instructions determines the device operation. There are 16 pages of instructions with 64 instructions on each page. After power-up the program execution starts at a fixed instruction address. Then a shift-register program counter sequentially addresses each ROM instruction on a page. A conditional branch or call subroutine instruction may alter the six-bit program-counter address to transfer software control. One level of subroutine return address is stored in the subroutine return register. The page address register (four bits) holds the current address for one of the 16 ROM pages. To change pages, a constant from the ROM loads into the page buffer register (four bits), and upon a successful branch or call, the page buffer loads into the page address register. The page buffer register also holds the return page address in the call subroutine mode. 2.3 RAM OPERATION There are 256 addressable bits of RAM storage available. The RAM is comprised of four files, each file containing 16 four-bit words. The RAM is addressed by the Y register and the X register. The Y register selects one of the 16 words in a file and is completely controllable by the arithmetic unit. The TMS 1000 series has instructions that: Compare Y to a constant, set Y to a constant, increment or decrement Y, and/or perform data transfer to or from Y. Two bits in the X register select one of the four 16-word files. The X register is set to a constant or is complemented. A four-bit data word goes to the RAM location addressed by X and Y from the accumulator or from the constants in the ROM. The RAM output words go to the arithmetic unit and can be operated on and loaded into Y or the accumulator in one instruction interval. Any selected bit in the RAM can be set, reset, or tested. 2.4 ARITHMETIC LOGIC UNIT OPERATION Arithmetic and logic operations are performed by the four-bit adder and associated logic. The arithmetic unit performs logical comparison, arithmetic comparison, add, and subtract functions. The arithmetic unit and interconnects are shown in Figure 4. The operations are performed on two sets of inputs, P and N. The two four-bit parallel inputs may be added together or logically compared. The accumulator has an inverted output to the N selector for subtraction by two's complement arithmetic. The other N inputs are from the true output of the accumulator, the RAM, constants, and the K inputs. The P inputs come from the Y register, the RAM, the constants, and the K inputs. Addition and subtraction results are stored in either the Y register or the accumulator. An arithmetic function may cause a carry output to the status logic. Logical comparison may generate an output to status. If the comparison functions are used, only the status bit affects the program control, and neither the Y register's nor the accumulator register's contents are affected. If the status feedback is a logic one, which is the normal state, then the conditional branch or call is executed successfully. If an instruction calls for a carry output to status and the carry does not occur, TOY ADDRESS LOGIC FROM CONSTANT AND K INPUTS FROM RAM 4 TO RAM AND 4 4 OUTPUT 4 LATCHES 4 4 4 STATUS OUTPUT TO ~------~L--------+----~PROGRAM CONTROL LOGIC AND STATUS 4 OUTPUT LATCH FIGURE 4 - ALU AND ASSOCIATED DATA PATHS 7 then status will go to a zero state for one instruction cycle. Likewise, if an instruction calls for the logical'comparison function and the bits compared are all equal, then status will go to a zero state for one instruction cycle. If status is a logic zero, then branches and calls are not performed successfully. 2.5 INPUT There are four data inputs to the TMS 1000-series circuit, K1, K2, K4, and K8. Each time an input word is requested, the data path from the K inputs is enabled to the adder. The inputs are either tested for a high level ("" VSS), or the input data are stored in the accumulator for further use. The R outputs usually multiplex inputs such as keys and other data. Other input interfaces are possible. An external device that sends data out to the K-input bus at a fixed rate may be used with the TMS 1000 series when an initiating "handshake" signal is given from an R output. Data from the K inputs is stored periodically in synchronization with the predetermined data rate of the external device. Thus, multiple four-bit words can be requested and stored with only one R output supplying the control signal. 2.6 OUTPUT There are two output channels with multiple purposes, the R outputs and the a outputs. Thirteen latches store the R output data. The eight parallel 0 outputs come from a five-bit-to-eight-bit code converter, which is the a-output PLA. The R outputs are individually addressed by the Y register. Each addressed bit can be set or reset. The R outputs are normal