Datasheet · c. 1972
TI TMS0117 Arithmetic Processor Datasheet
Datasheet of the TMS0117, a member of TI's TMS0100 single-chip calculator family: pinout, timing and functions.
Datasheet · c. 1972
Datasheet of the TMS0117, a member of TI's TMS0100 single-chip calculator family: pinout, timing and functions.
ae TMSON7NC isi 10 DIGIT DECIMAL ARITHMETIC PROCESSOR 10 Digits, 3 Registers BCD Input and Output Direct Add, Subtract, Multiply, Divide Implied Constant in 4 Basic Modes Add to Overflow, Subtract to Zero Shift Left, Shift Right Exchange Registers Busy/Ready Interlocks On-Chip Digit Clock 100 ms Maximum Operation Time TTL Compatibility description The TMS 0117 NC is an MOS/LS| digital building block designed to process numerical data in BCD format. The device performs the most commonly required arithmetic operations, and numbers of up to ten digits can be processed in under 100 milliseconds. Even when only partially utilized, the TMS 0117 provides a considerable cost saving when compared with more con- ventional arithmetic techniques. Its applications include automatic control systems, on-line data analysis, digital correlators, weighing machines, and computing counters/frequency meters. The device requires a minimal amount of external control logic, and complex problems may be solved by using it as a ‘mini’ central processor unit (CPU) in conjunction with SN74188 bipolar integrated circuit Programmable Read Only Memories (PROMs) as the micro- program store. In addition to the four basic processes (Add, Subtract, Multiply, Divide), the TMS 0117 performs operations such as Increment, Decrement, Shift Left, Shift Right, Exchange Operands, Add to Overflow, and Subtract to Zero. A BUSY/READY signal generated on the chip discriminates between the BUSY condition (output data invalid, no data can be entered) and the READY condition (output data valid, data can be entered). Data input and output are in serial form. An output clock generated on the chip can be used to off load the output data into a memory. operation Functions that the processor will perform may be Classified into three types — arithmetic, register, and internal contro! (‘housekeeping’). Register and simple arithmetic operations, such as data interchange and add/subtract 1 require a minimal amount of internal microprograms and are rapidly executed. More complex arithmetic operations, such as multiplication and division, use a considerable portion of the program space and take proportionately longer to execute. The time taken to carry out housekeeping instructions, e.g. reset after error flag, is variable, being depen- dent on the state of the internal program. The operations are defined as follows: e Multiply Multiply the contents of the output register (multiplicand) by the last data entry (multiplier) and transfer the product to the output register. — continued TEXAS INSTRUMENTS TMS 0117 NC APRIL 1973 - operation (continued) ve mie the ee of the output register (dividend) by the last data entry (divisor) and transfer th the output register. e Add Add the last data entry to the contents of the output register. e@ Subtract 3 Subtract the last data entry from the contents of the output register. ent s | 3 (eat lea ghee e pohly the contents of the output register. (Decimal point and sign are ignored in this operation. e Decrement aed Subtract 1 from the contents of the output register. (Decimal point and sign are ignored.) e@ = Add to Overflow oe Continuously increment at the rate of 1 per D scan, the contents of the output register until overflow e Subtract to Zero ek Continuously subtract 1 at the rate of 1 per D scan from the contents of the output register until ze e Equal oh Execute instruction. Causes the processor to carry out the last stored instruction. Equal also constant (last data entry and last function). © = Right Shift in Geeta Move the contents of the output register one place toward the least significant digit (LSD). © Left Shift wha lea Move the contents of the output register one place toward the most significant digit (MSD). e Exchange Operands , Interchange the last pair of numeric entries, e.g. a+ b becomes b = a. ; bi : . | aan a ; . ; Clear all stored instructions and data registers. ns & e Reset 5 Reset is a master clear and will operate under all conditions. It is used when the proc state, i.e. error flag, and it resets the internal programs. Lae The basis for the timing is an external clock applied to the device. Nominal frequenc of An internal state time is equivalent to 3 external clock cycles. A digit time is equivalent to 13 interna 39 clock cycles or nominally 186 microseconds, A digit time (D-time) corresponds to the time dur . ae is displayed. A blanking of one state time is on the leading and trailing edge of each D output terminals are used to scan the data entry logic and to multiplex a display. Only one digit tim: a ha eek displayed in scanning mode, thus any digit is displayed for one D-time and di playe (A D-cycle is equivalent to 11 D-times — i.e. 1.72 milliseconds.) rere) a a SE timing (continued) TIMING DIAGRAM One Digit Time e JUAN texTernat cLock) O30 A Sle i ed Bo es LS eel ee Lede ed a (INTERNAL CLOCK) 3. fan ius Us ie 45126520653 201 PS S506 © SS7 OS SIPS DPSSIP<E1 j<SRe<Si<Ste «STATE TIMES SEGA ~] fad ITs SEGB _f~ 1 SEGC SEGD | 2 DIGN J l DIG (N-1) ad a ee DIG CLOCK WA RS Sea | Two Digit Times, Displaying Number 97 3 7 (8) sA @— —@ (2) sc r= —_@ (1) sD @— —_@— —® DIGITCLOCK SP e © e—® Do @— —@ Dn-1 ‘ e— —e The table below shows the time required to complete the functions indicated for a nominal 250-kHz clock rate. FUNCTION TIME Numer entry, single digit 5.2 ms maximum Operation instruction entry 6.9 ms maximum Shift left or right 1.72 ms Increment or decrement 3.4 ms Exchange operands . 5.2 ms Add, subtract 8.6 ms Multiplication 70 ms (worst-case numeric inputs) Division 80 ms (worst-case numeric inputs) genes Digit cycle time 1.72 ms RS Digit time ’ 156 us RR: gms 0117 INPUTS, OUTPUTS, CONTROL TERMINALS DATA OUTPUT | SA ere eH ; iF RESET —»— KO 38 [o> SC) PARALLEL BCD, DECADE SD }-—e—1 /) SERIAL USY /READY _ SERIAL DATA IN —?— > Ka Be BUS / 2 sG /-—»—ERROR DECIMAL POINT —®—4 KN sp |-—»— DIGIT CLOCK — D1 ENABLE —®— KP } . . clock —=—4 ? ; 5 D111 There are two types of data input, both of which are entered on the KQ terminal. Mey Oe e Numerical data i iigesos as akon ahaha neanae © —— Operation commands The serial data input line requires its information in the form of a ‘sertal five-bit word. instruction code and the fifth bit as a control. The control determines whether the four-bit code is interpre or as an instruction. . uta aS et OG INPUT CODING : 4 ONTROL BIT ee ae NOTATION 9% SS 35 33 at 30 i oH i) 0 (9) 0 1 LEDS: 0 0 0 1 0 2:5 0 0 0 RNG avian ah ts) 0 1 0 0 4 0 o- 1 0 1 5 0 0 4 i ieeeenses aK) 6F 0 0 1 1 1 7 0 1 0 0 ) 8 0 1 (9) (i fase rete ake hh Q- 1 0 0 0 0 Clear ethos i 1 0 10) 0 1 Equals Went § es 1 0 0 1 0 Multiply eee A a 1 Cy) 0 Pacer Divide Sie tA 1 0 1 i) 0 Add Sat nis 2) 1 0 1 0 1 Add 1 : 4 1 1 0 Subtract i} p wy 1 1 Subtract 1 vi ie : ; 0 0 Add 1 to overflow _ ee ; i 4 0 1 Subtract 1 to zero ‘f eae sy . 1 | 0 Shift right : Homecd 1 1 Shift left | mY is 0 ) Exchange Operands: : : ap i iH 1 No operation — 4 i Hb pps pate No operation — _ No operation — data input (continued) In order to reduce the number of package pins required for data entry, the five-bit code is serialized. The processor generates sequential digit strobes, D1 to D1 1, that enable the input data to be serialized. The data input lines are KN, KO, KP and KQ. The boxes represent a logical or direct switch connection between the digit lines D1 to 011 and K inputs. DATA INPUT AND DIGIT LINES Vss KP a ENABLE KO RESET CONTROL 23 22 21 20 Fa eee DATA ENTRY KQ a DECIMAL POINT” KN «———_| D111 D10 DS Ds D7 D6 D5 D4 D3 b2 D1 * Decimal Point — one switch and only one switch permanently closed. A gate implementation of the entry function and a simplified timing diagram are shown below. ENTRY FUNCTION TIMING DIAGRAM Vv, Vv: t r 20 cc Ss goers eng D1 int" Dt Aa Ke rn. ps DATA D3 ee 32 TMS 0117 a ae =) D1 +e 525 . fA D7 Bs ED os : 1 = D7 . . CONTROL aie Dii}-> D10 ; Tl pt Sa ey DN KQ INPUT — INST. SUB. eel KQ INPUT — DATA The data entries are controlled by the enable input, as described under Input Coding. Numeric entries are limited to ten digits. Any zeros that are required to fill the unused most-significant-digit positions preceding number entry (leading zeros) need not be entered; but if, from a systems point of view, it is necessary to enter them, they will be ignored by the processor. Data are entered most-significant-digit first. — continued RE ne data input (continued) SRAESEE terminal is an interrupt signal. It will clear all registers and status information under any conditions, This ts the only key operational after the machine enters a locked state. The CLEAR opcode clears in the same manner but cannot be used once in the locked state (overflow). RESET operates independently and does not need to be followed by an ENABLE. data output The TMS 0117 has two types of data output — numeric and status. : numeric data Numeric data is presented as digit serial, bit parallel, Binary Coded Decimal (BCD) during digit times D10 (MSD) to D1 (LSD) on outputs SA to SD. This serial information repeats after 11 digit times, i.e. once every digit cycle. Outputs D1 to D10 can be used to strobe an external display or indicate the beginning and end of the output data word. An Output digit clock is provided on output SP to enable the user to clock output data into an external register. The digit clock timing is arranged such that output data is valid on either edge of the digit clock. Similarly digit strobes D1 to D11 also inset the data outputs. SA SB» SC | SD SE SF SG DIGIT ( 0 ) 0 ) ) ft) 0 0 0 0 0 1 0 0 0 1 0 0 1 0 0 0 0 2 0 0 1 1 18) 0 0 3 ) TO 80 OsaAKOnEiaO 4 i pata { OO 05 8050 5: rT LaReEsy Renn antes) OsOy HO 6 = 0 1 1 1 0 0 0 7 ‘Ke 1 (8) 0 0 0 0 is) 8 & 1 Ox20 1 Ot 0< 90 9 NOTE: Data is extracted from MSD (D10) first to LSD (D1) last. status information is Status information, i.e. the internal state of the processor (housekeeping), is available on Outputs SE to SG during D11 time. Output D11 may be used to clock outputs SE to SG into an external register. STATUS CODING r 4 SA SB SC SD SE SF SG t 0 0 0 0 1 x 0 Busy fa 0 0 0 0 0 x 0 Ready INTERPRETATION 0 0 0 0 0 0 0 Sign Positive (where X represents a 0 0 0 0 0 1 0 Sign Negative don’t-care condition) 0 0 0 0 Xx x 1 Error Error ah: Sign OUTPUT , Bo) Busy/Ready ‘ i — continued data output (continued) During D11 time, outputs SA to SD are zero. Output SG indicates an error, such as numeric overflow or an invalid operation. Status outputs have the following priorities: Error output SG invalidates all other numeric and status outputs. If an error indication occurs, the proces- sor enters a locked state and must be reset. Busy/ready output SE invalidates numeric and sign data, unless it indicates that the processor is ready to accept new data or instructions, i.e. only when there is no error and the ready signal is present are the sign 1) 2) and numeric outputs valid. An example of the data output timing is shown below. DATA OUTPUT TIMING EXAMPLE D1 il D2 Ee, os “fecal D4 1 D5 1 Ds f-1 D7 ea Ds [aml Ds fo fay D10 ERIS page Beli D11 AS Bo bets sD eee Pomona Ei ney Ceca proeemmenenmeer een | [ ERE Ka 2M ST sc S EE Et tiaras a SB J FS be SA | ie Sard Kok DIGITCLOcKk ___J1. | py BCC py PY oy ERY pk eee 9 a Se eee SE SF aude PRY L SG i) 3 as BION ie 1 9 0 6 5 4 ) 0 3 READY As shown, the serial output data represents -0190654003, The numeric and si id si As : a 3 gn outputs are valid since th indicates that it is READY and there isno ERROR during D11 time. Paras decimal point (DP) The processor operates in fixed-point mode on input and output. The point is not interposed between input digits, i.e there is no input or output data code representing DP, DP is, in fact, implied by the digit time at which input KN is taken to a logic High. Decimal-point format is shown below. , — continued Ee lasses asi spo eis cid uisene d amanisaeieebeiaciruicboniantasaei ace a decimal point (DP) (continued) DECIMAL POINT FORMAT OUTPUT REGISTER MSD LSD Ree eRe Kee RR ' ° DIO >) RO KK FR I OR ATR D9 KeaKO Ke RR WR a b8 ROOK KEK OR KR OK OKO D7 : : ‘ . - ‘ ‘: “ : : : Be Digit time at which KN = Vgs > >, GAM GM, GEES Ga GS ea Cae D4 > Suis, Ue Ges, Gone, Whee, Cae, Oh Tae Teas D3 Sahni Gas GRA Gui. Gia am Geet di ab D1 Y, KN may be taken to a logic High by means of a fixed link with the required digit output D1 to D10. If the position is to be determined by means of logic inputs, then open collector gates can be used to determine the KN-digit connection | in a manner similar to data entry. The decimal point is not input in the normal flow of entering numbers but is set for any calculation by a switch. The NOTES: position of the switch does not affect an addition or subtraction problem, but it does affect multiplication and division (see the problem set below). The decimal is not stored internally; therefore, erroneous answers will result if the decimal switch is changed while performing a series of calculations. To prevent errors, RESET or CLEAR the chip after changing the decimal-point switch. PROBLEM SET DISPLAY NUMBER ENTRY DECIMAL POINT AT POSITION: 0 2 4 500000 500000. 5000.00 50.0000 + 500000. 5000.00 50.0000 400 400. 4.00 0.0400 x 500400. 5004.00 50.0400 30000 30000. 300.00 3.0000 ie (OVF) 0. 1501200.00 150.1200 400 (OVF) 0. 4.00 0.0400 = (OVF) 0. 375300.00 3753.0000 RESET 0. 0.00 0.0000 1 i 0.01 0.0001 A 1. 0.01 0.0001 3 3. 0.03 0.0003 = 0. 0,33 0.3333 90 90. 0.90 0.0090 = 30, 30.00 30.0000 4 4. 0.04 0.0004 EXCH OP 3. 0.03 0.0003 = 0. 0.75 0.7500 1; 2. For clarity, insignificant leading zeros are not shown. Decimal point is external to chip. overall operation The timing of the data entry and contro! is determined by the enable input in conjunction with the status outpiits ¥ is best expressed in ‘digit times’, i.e. the time between leading edges of successive digit pulses, and ‘digit cycles!/it'e tx ' time between leading edges of successive D1 pulses. Bg To initiate a data entry cycle, the enable input KP is taken to a logic High (Vgs). After a variable delay, the status out. puts will indicate that the processor is in the BUSY mode. Data entry will be possible during the READY mode only The TMS 0117 will ignore inputs when performing an operation. The entry cycle will last 14 to 23 D-times, depending on which digit is On when the enable connects to Vgg. Enable must be released within 5 D-times from BUSY soriat unless a special mode of operation is desired. In the special mode the enable is kept High throughout the Operation Data inputs are changed each time the processor goes from the READY to the BUSY state until the entire sequence is completed. This speeds up data input since the processor may be ready internally to accept new data, but, because of the multiplexed output, the READY output cannot be given until D11 time. Since data entry and some operations such as Add 1, Shift Right, etc., are short, the BUSY time will only be 1 to 3 digit cycles. * Data and instructions are entered in the same order as with a +, —, = type of keyboard. In addition to chain operations eg. z x b x c =, there is an implied constant. The processor retains the last operator and number entry before an Equal operation, as a constant. The + and — code is interpreted as a sign after a Multiply or Divide operation, and as an operation at any other time. Successive Equal operations cause multiple executions of the previously stored instructions and the associated data, i.e. constant mode operation. Examples: Entry Display Comments Entry Display Comments 1) 100 100 Display entry 3) - 0 Stored as sign/instruction = 100 Stored as instruction 5 5 Display entry 3 3 Display entry x —5 Enters instruction and interprets— = 97 Executes previous instruction as sign and displays = 94 Constant mode, instruction is 3 3 Display entry sub 3, executes and displays a! —15 Executes previous instruction and 94 Stored as instruction displays result * 50 50 Display entry = 44 Executes previous instruction 4) oa 0 Stored as sign/instruction = —6 Constant mode instruction is 5 5 Display entry sub 50 x —5 Enters instruction and interprets— = —56 Constant mode instruction is as sign and displays sub 50 - —0 Enters sign and displays 5 —5 Enters data and displays with 2) 100 100 Display entry eS associated sign 100 Stored as instruction = 25 Executes previous instruction and 3 Display entry displays result + 97 Causes previous instruction to bast: be carried out and stores 5) 100 100 Display entry current instruction. + 100 Enters add instruction: 10 10 Display entry = 200 Enters sub instruction and executes + 107 Previous instruction carried out previous instruction and stores current instruction 3 KS) Display entry 3 3 Display entry = 197 Executes previous instruction and _ 110 Executes previous instruction and displays result i stores current instruction 4 9 p f 6) 100 100 Display entry 9 99 Display entry é q i A <¥ 11 Executes previous instruction and x 100 Fanters sub [nateushan . : - 0 Enters sub instruction and executes stores current instruction fs ; . ; ' previous instruction 12 12 Display entry ’ Pm tenia = ig E : fa ineeen cabarets 5 5 Display entry xecutes previous instruction a A —5 Executes previous instruction and isaireh es (2 ; displays result absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage Vpp range (See Note 1) Supply voltage VGG range (SeeNote1) . . ...... . NEI RG TP ee PRIS awa rep Vito 0:3'V. Clock input voltage range (SeeNote1) . ........ ey MeL SOT eM EstO uate ie Rees ZO WO Osi: Data input voltage range (SeeNote1). . . 2... 2. TELE NE Chet Nore, Bae Bove ty 5 20 VITO O3V Applied output voltage range (SeeNote1) ....... . sei) tes Se eRe he ee Pon oat =O Vite O.3:V Operating free-air temperaturerange . 2 2... . . eee ee ee 0° to +70°C Storage temperature range. 9.0 SPO ee i aie Wines ne carls CSih —55°C to +150°C NOTE 1: These voltage values are with respect to Vss (substrate). recommended operating conditions CHARACTERISTICS CONDITIONS MIN NOM MAX UNIT Operating Voltages (See Note 2) Drain supply Vpp (See Note 3) 0 0 te) Vv Substrate supply Vss 6.6 7.2 8.4 Vv Gate supply VGG —8.1 —7.2 —6.6 Vv Clock Levels Clock high level Voy Vss —1.5 Vss —0.5 Vss Vv Clock low level Vet V6G-—1 VGG V6G+1 Vv Applied Output Voltage —0.3 18 Vv Clock Timing (See Clock Timing Diagram) Frequency 100 250 400 kHz Period T4 2.5 4 10 us Half-period T2 1.25 2 5 us Half-period T3 1.25 2 5 Bs Clock T, and T¢ f clock = 100 kHz 30 1000 ns Clock T; and Ty f clock = 250 kHz 30 650 ns. Clock T; and T¢ f clock = 400 kHz 30 300 ns Input Level K Lines Low VGG Vpp ~ Vss-6 v High Vss -1.5 Vss -0.5 Vss Vv NOTES: 2. Effective zero suppression depends on a transient free rise of Vsg and VGG during power-up. With certain supply systems it may be necessary to capacitively damp the supplies to ensure zero suppression. 3. Vpp is voltage reference. CLOCK TIMING DIAGRAM pak eats Aa ———-. Vou {eeeneneneceeeens Se SES i, TTL interface (continued) All outputs, D1 to D11 (data and status) are open-drain buffers. The output etlhade Wad sides oie ERIK TDS(on) of 250 Q and can supply in excess of 5 mA to Vsg. An economical output interface compa shown below. Any output, e.g. digit clock, that is required to drive a TTL clock input should be Haat es pssst baci such as the SN7414N integrated circuit. The Schmitt trigger is required because the fal pHi Pp is of the order of 150 nanoseconds and is not directly compatible with edge-triggered TTL inputs. INPUT INTERFACE OUTPUT INTERFACE Vv 4.7kQ f vss e Vss SN7405A OR OTHER | is 3 ‘ . SN7404N 2 OPENCOLLECTORTTLS $ $ se 680 2 ~ [>> o— KP 2 - 3.9kN Re 2 > KO = v, ° < {>e- KO ite GG SN7414N 9 g i z +> KN TMS 0117 2 5.6 k2 ry VeG mechanical data The TMS 0117 NC is mounted in a 28-pin plastic dual-in-line package, designed for insertion in mounting-hole rows on 0.600-inch centers. — Clock input 1 C] || 2 Enable input KP 2 a il 27 Serial data input 8 Vss substrate supply KQ Digit output 1 3 a ] 26 Decimal point input KN Digit output 2 4 il 25 ~—- Master reset KO Digit output 3 5 [] [| 24 Digit clock output sp Digit output 4 6 [] | 23 _ Display dipstick output SH Digit output 5 : 7 C] il 22 Error output ~$G Digit output 6 8 a a 21 Sign output Status SF Digit output 7 9 i a 20 Busy/ready output SE Digit output 8 10 a ] 19 | Numeric output 29 (LSB) SD Digit output 9 11 a al 18 Numeric output 21 sc Digit output 10 12 ia r] 17. = Numeric output 22 SB Digit output 11 13 [ | 16 Numeric output 23 (MSB) SA’ Vop drain supply 14 il 15 Vag gate supply NOTES: 1. Digit outputs 01, D3, 05, D7 and D10 are used to serialize input data. 2. Digit outputs D1 — D10 are used as digit enable for numeric display. 3, Status outputs are valid during D11 time. 4. K input and S output notation per TMS 0100 NC specifications. i 5. Display dipstick SH indicates the number of digits displayed in the output register by being at logic High for the relevant portion of the digit cycle, It acts as a zero suppress latch. my Copyright © 1971 by Texas Instruments Limited. All Rights Reserved. This publication, or parts thereof, may not be reproduced in any form without permission of the publisher, Texas Instruments Limited, Texas Instruments reserves the right to make changes at any time in order to improve design and supply the best product possible, Information contained in this publication is believed to be accurate and reliable. H , fesponsibility is assumed neither for its use nor for any infringement of patents or rights of others which may result from its use. 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