Reference / Paper · 1982
Sharp PC-1500 Technical Reference Manual
Sharp's technical reference for the PC-1500: the LH5801 processor, machine code and the system.
Reference / Paper · 1982
Sharp's technical reference for the PC-1500: the LH5801 processor, machine code and the system.
SHARP ‘pocxer computes PC-1500 TECHNICAL REFERENCE MANUAL se eeeeee se eneeeee se aeeeee se eeueee Seeeeee | se eeeeee ee eeuuee eB eeeeee SHARP CORPORATION Do not sale this PDF ! All and more about Sharp PC-1500 at http://(www.PC-1500.info Do not sale this PDF !!! All and more about Sharp PC-1500 at http://www.PC-1500. info FOREWORD Since the release of the PC-1500 on market, we have had great number of questions from users regarding the machine language of the PC-1500. To meet with such demand from ardent users, we are now sending this text for study of the machine language of the Sharp’s original design LH5801 Microprocessor and L.H581]1 Peripheral Control LSI in concern with the PC-1500 system. Because the text is edited on the basis of user questions, it may not support quality as a guidebook. In such an event, you are suggested to make reference to microprocessor guidebooks published on market, in addition to this text. Your opinions and questions are welcome through our products distributor. NOTE: Machine language program, which controls hardware directly, gives you more various functions than BASIC programs. However, you should check your machine language program enough to make no error before executing it because single wrong key operation may upset the program or occasionally make the machine break down. Sharp Corporation assumes no liability Or responsibility of any kind arising from the use of programs or program materials or any part thereof. SPECIAL NOTICE TO PC-1500A CUSTOMERS Because the PC-15Q0A provides more RAM than the PC-1500. some of the descriptions of the CHIP SELECT SIGNAL. MEMORY MAP, and 40- PIN CONNECTOR (for memory modules) require modifications to suit the PC-1S00A, A summary of the differences between the PC-1500A and the PC1500 is given in the addendum on the page 161. lake notice of these differences when using machine language. Do not sale this PDF !!! All and more about Sharp PC-1500 at http:/Awww.PC-1500. info CONTENTS 0 RE 2 III ene eee on ACE Eg ES ARERR E OEE ATS Sas A PU RIRD IM OFAWUS Oh RUNS T A OIESR 1 2; LHSSO1: Micronracennet 5i5iissas is ea REE TS 5 2-1. Outline Of LHSGOT ... ccc c cere cctercetcnecececcccererererererrererercceensey 6 BG: WVRSE NE SUUCUAD: ca 5cccisc.oce cessnr eens eessneetenger esas pase he ee ery eT eeNgs SOEs 7 BE: Bink Gaga scssa caiaces caresses nteanadswers heresies ieebarens 7 BAD, letaral Ogee i VER ee Fae ae 8 SPB; “SlOtS NOS co ccscorvaseascs se eievssa eo apmeseraene se wereKeeeeeees wanes tC 22-6, CPU: pin desertion xis cscics sc ciiscenenemncen ea eae aw eee OSS OEMs 9 DS PUNE ES SNS eed NR a Pa SOLED ORO RE CLAS GSW eT eS 14 Ce Oo ee en ee oe ee 14 DeBee, WUMOTUETS <6 6055 ceage ene swereaNerers sss eee ee tes 17 BeBe, RRS a is Cea REARS TERE Re 20 2-3-4. CPU system sequence : 21 Ba BE MED ec ousienet pawn yds siveniod Nata ht-ep kita acon a ae Ra wees PEA Rees 22 S-B WAIT HOO isinicic ss cic siren snasisccicsnscxacuswasswesweeese ch veseteeees ess 23 2-4; LHSOSS imetruntlang assess sass tok sii dha a tis 24 2-4-1. Outline - 22... eee eee ee eee eee e eee e peewee re eeeeyeeeeeeee 24 2-4-2. Add, subtract, and logical instructions ..........-.......-.- SOTTO Tir 25 2-4-3. Compare and bit test ..... is ibn acd SAGA OES VaR AR SR Te IO WW bik beRal es Sues 31 2-4-4. Transfer and search instructions .,... REDEN Sette VEG POTEAU ERMC ab RRS Jukes OS 2-4-5. Block transfer and search instructions ,..... 6... cece ee eee eee ene ees 38 ZehsG: - Rotate vrd shit Inslruclone sicacacxcasasiresacesxes ead vw ad eies ee yeas es 39 a-Aefi CPU control instructoneaiiiicarveivii ccna ress aes a aie 42 oT a Le ae ee ee ee ers 45 RRS, <SiCoestiene Hw MWS WU CTIOIG saci 5 cinco: pees ceeswacn s0 5 Ha es RENN ONS BWHE 49 BAe 30; atures: ne lraMee ioeiss aiisin sin ss Sl aicak ke Raia Re Hawai dae RASTER 53 BB CE USE ose cicas Secs eae ae wed ene cek eae eseseccslsseedsnibwhtaseyeacboavseleas 54 2-6. Electrical characteristics and timings .............-.-------- +22 ccc ceeneneneeeeeene 63 9: LOSC1G/ENSEt1: OC part Conner rics ccic ee ee a 67 OE CARE 5 ovina eaiewene-n en svarins ane c-nsecesawepneeeerennnssrerenenctipevecieabsnseeee 68 9-2: FURIOUS es nsec crcennee rep gticciceey arene eV esee ber Kec ae en ee oun hile esielpleseiznies 68 PS TERETE: BEI Rema 555 ae FA Hi ak GR GS NDE LEA WAGER RUR Dh awe Cee ERNE Saiatee 70 BBsT, “BSG iMG rai ss CU eae ee eee hie seat ece outa ewes een euawaeee (yews 8eO 3-3-2. Internal registers 70 353-3, “Pin description «5 oso ss scvwie ce cccsceis eectaee 73 Soh FNS FE EAE RRS TE TUNES RS 74 BET, COMMA cas cenisnseae cathe cetnavess \eust secs sindenqasseteonsennerses sia 74 BAZ, “WE CONWOL 0:60: osascssigus seas ones crane seemecegegeayeseiseewsaseigeences 75 SAR, Geral late Meso isccrenaccciesccncunneeseeeeee aaa ela 76 DA, BHOOOE sa a oui occ cass cicis Ses waemarelebcs balaspaesneeawedndaclnedee teeedewae uewan 77 iets SONIA INNIR 5 secre aeik a Sie in pine a AW Ale CIE A OLDEN E959 MATRACTIEREMR OREIER ERS nceeneea eat aneraspie Meera 78 3-5-1. 1/O port controller input/output circuits 78 22. Pad tapout end QuuGnwe sis. 65a AERA S 79 3-5-3. Electrical characteristics ..... 0... 0000. oe eee ene nee 79 Do not sale this PDF !!! All and more about Sharp PC-1500 at http://www.PC-1500. info 4. PC-1500 hardware description ...- 2.2.2.6. ccc etree tenes teen ene 85 4-1. PC-1500 system configuration ........... 6. ce ese e eka neces ener ee neenneeseeeeseneees 86 Att. Outlinesisae ainsi cesi sais ea ee ee ees 86 Ha052; BIOCK GIAGIAIN S06 oS 5 ee SENS a TCG eS a Nae I 87 * 4-1-3. Power supplies (PC-1500, CE-150, CE-158, CE-159) ...... 22... ee cece eens 87 4:25 PC21500 cecasenc ames wierRMM eee ae tales mmteuateT Eee Hel STERN W Ake ee 89 BO, Clan aie 89 4-2-2. Block diagram. .......--.ereeeccnrererc cent et ae ee bansentecberecseacversoes 90 4-2-3. Chip select circult).....5 00... ccnseennces ne nneein eae cnswe ce seeee ee ne tenes eens 91 4-2-4. PC-1500 system memory map .... 2... ee eee eee eee 94 4-3. Connector signals/LSI signals ....... 2.2.26. 6 eect e eee teen eens 102 4-3-1, 40-pin connector .........-.- 2 eee cece cece teen tenet een tees at ener eetete 102 4-3-2; GBO-DIN: CONNECIOR once xasioniec cw sasseyewewarN Meade a Nias Dea SRE 103 4-3-3; LHS801 Microprocessor. i... 5 SS EE Re 104 BORE AIO BG) cere ncnagenserneneunace.s nema gremmnenea.cig noes amd hea mise geded Mia eae Rae 105 4-4, Key matrix and key code chart ........ 00.6.6 c ccc eee eee eee sentences 109 5. PC 1EOO: SOT ware 5 65k re BES Pa aaa eS 111 5-1. BASIC command related PC-1500 machine language ........-.-.-..... 6 eee nnnnes 112 SeIst. (NEW 5 sacacoacen a mictass ruin cosas po emg cayenne ea meme iCne 112 Safe D STATUS cee cae ae mea RA 112 BAAS SPEBK nae cope ececeess sce d bea hie VEveng LOSE d ea Rne re Nana DUET Gost he ones 113 oy BY 0) | ee ee ee ee ToT Teen Meret rte 113 5-1-5, CALL iccsececeecuns 5 ae SY Ga RNa OER TRAIAN MaRS ee Beare 114 561367 CSAVEM o06 capes as cenaiedaenc Gudea oieen dating howameesGuaegee cea belmiaaaG 114 Se Det LOW sip cresttaag hogs rickesa atu e ner a art Mo Eon Ur aie er ere ema o.e FSR Oe egies puanaie 114 5-2: Internal: code: Chart:.c5< 5.005: ss -aacevisiein cc NUDES NAAR SAL a ead ae Wa Sater eerie nee TTY 115 5-3. Expression of variable and program ............. eee ees eee eee eee enters 116 5-3-1. Expression of decimal number ............0 0 cece eee cece e erect eee ee enee 116 5-3-2. Expression of binary number. .... 2.2.2.6... ccc tee eee eee eee 116 5-3-3. Expression of character string..... 2.2.00... ccc c cece cece net e eee e nent en eees 116 §-3-4; Structure:of variable mame ie 5G aie hs I 117 ES Cet ET ROL A Cri cL Renee eee eee Tee nT Pa eT eS OR 117 5-8-6. Structure of reserve area... 0. ccc cece eee ee re ens ent ere nees eae ee beeen ee 118 5-4. System subroutines «0. 0.0.6 eee ea de eae e dee ee ese eae ada tae 120 Sedel, ‘Character tanctons:... 02-020 -usjpre cess eens seer eseesne apap gases dag ked 122 5-4-2, Arithmetic subroutines «0: 0:6:9:¢:sec.ce pee wiectew ne baie oe aaieate dl qele wee e ae are resinee 127 54-3; Compares ss SEA ASE EER GAN a CARAT OTS Wis AE Rae SE 128 SARA, SORE. okies cscna eae Coie Ss a webia e cibae Pare ba Oe Swe eee a ea pee Fae a 129 BAe ADSM BY cesta gases: acesen carer miacein ences herecearesarene er lece wimetn one wee ON er ee pe T Ke 131 S46: Pritt siccc sass newepss ace eam semana aie leale wea sao ee aM eee ERA IGs 135 BaAa7, “Caseotte tape see ese iS ei Pe We esis 138 5-4-8. Caution for system subroutine Call .......-.-.-. 52. e cece eee eee eee eee 141 6. Machine language programming examples ..........000 0c cece eee eee eee eee tes 143 6-1. Binary to hexadecimal conversion ......... 6.26.6 ccc ccc eee etn eee eee ees 144 G=2. Display INVEPSION 2.0.00 noire cane gnee eee ste sean Ne R Meee E Teens ne mene es 145 6-3. Single display: dot lelt-stlif i053 cess tas sacs eccraniwens owe Naime eR TeE 146 6-4. Single display dot right ahlft 1. <5 ONE DENTE 147 6-5. Conversion of USING format expressed numerical data into character string........ 148 6-6. Power off that does not activate the printer upon power on .........--------+ ee eee 148 Do not sale this PDF !!! All and more about Sharp PC-1500 at http:/Awww.PC-1500.info [REFERENCE] 1. Determining printing character size and direction... ......0000 00006 ccc cee eens 150 2. Restoration of array and two-character variable............ 202.20. 200202000 e eee eee eee 150 3. Knowing the use Of CE-150... 0... cece eee rer en err e ee reneseeeererssserererrresrarss 150 ANS 2 ee Te 151 Ss CHOUE CRG TAIN acsisce sce sees renerg ease ERR AROS TERR Cea S SSN calle ENR Oa atale aoe bite eeRSeTS 153 BES PE eTOCs SBE DRS ASE 154 be ae | | A ne nC on en eae 155 on, Cote ae Uaiaaara tiered eneRrewer Raa ew GnTaR Ns we me nw se RUA TEES 156 SA CES SETAE NRRL ESR 156 5-5. CE-155........... SO RG OT Oe RR On ne Coe cen 157 Re ae acs: sinnp wens ase nie-seie NoMa ater Som aan wie ww fa anton So adem Aas AEH asODS Wa RLA dei gta pemLOr OLDE RUbSBINLESETSLelaT ese 158 ey Oy | 3 Rapa ee ented Part TPIS ER ERO DOR SIC MIE NT NTT PST ae NOU Dar EER aR 159 [ADDENDUM] Differences between the PC-1500A and the PC-1500..... 2... 2.2.6... ee eee ees 161 Do not sale this PDF !!! All and more about Sharp PC-1500 at http://www.PC-1500. info Machine Language Do not sale this PDF !!! All and more about Sharp PC-1500 at http:/Awww.PC-1500. info 1. Machine language There are many program languages for each purpose, PC-1500, for example, is designed to carry out both BASIC and machine language. BASIC is easy to use, however, execution speed is slow. On the other hand, machine language is difficult to understand but execution speed is fast. Usually, machine language program would be written with the assemble language, which consists of mnemonic codes, and then the assemble language will be translated into machine language. [EXAMPLE] DISPLAY REVERSE PROGRAM I. Prepare the program with assemble language consisting of mnemonic codes. LDI LDI DEC LDA EAI STA LOP CPI BCS RIN spiced { prepare for assignment of the first display buffer address. UH advance the address U take data in the accumulator FFH take the complement U return data into memory 06H UHJ7H | make the loop OEH return to BASIC 2. Translate the above program into machine language. The assembler translates the assemble language into the machine language automatically according to the list. However, a short program can be translated manually. (hand assemble) The above program can be translated as follows; 68 78 6A 4D FD 62 25° BD FF 2E 88 06 6C 77 93 OE 9A Do not sale this PDF !!! All and more about Sharp PC-1500 at http://www.PC-1500. info 3. After the completion of the machine language program, write it in PC-1500 by using POKE instruction. And execute the program together with BASIC by CALL instruction. Execute the following program. You can run the BASIC program with (2) @ and the machine language program with C#) B) . Display reverse in machine language program is faster than that of BASIC. You would know how functional the machine language program is. EX. Write the following program after executing NEW &4100 (=) . 10 WAN WAIT O 20 PRINT" sharp pocket computer 30 FOR A=0 TO 155 40 GCURSOR A 50 GPRINT 255-POINT A © NEXT A 70 GOTO 30 8 END 100 "BY WAIT O 110 PRINT “sharo pocket computer" 1200 POKE &40C5-&68°&78>&6A+&4D> &FO+&62+&25'&SBD- &FF+&2E*'S88>h06 130 POKE &4001°+&6C'&77°&93+&0E*&SA 4g CALL &40C5 190 WAIT 20:PRINT: GOTO 140 16 END This manual is divided into three major sections; description of LSI (pp. 5~84: LH5801 Microprocessor & LH5810, LHS81L 1) O port controller), PC-1500 hardware description (pp. 85~ 109), and PC-1500 software description (pp. 11 I~ 141), If you want to know about PC-1500 system first, read from p. 86. Do not sale this PDF !!! All and more about Sharp PC-1500 at http://www.PC-1500.info Do not sale this PDF !!! All and more about Sharp PC-1500 at http://www.PC-1500. info LH5801 Microprocessor Do not sale this PDF !!! All and more about Sharp PC-1500 at http:/Awww.PC-1500.info 2-1. Outline of LH5801 The LH5801 Microprocessor is a CMOS static 8-bit microprocessor that features low power dissipation performance inherent to CMOS LSI and large capacity data processing. Not only that, it cnables to to configure a variety of systems with a few additional chips because such as the LCD backplate signal generator, input port. external latch clock, and timer are built in the LH5801. Features of the LH5801 @ $-bit parallel data processing @ Direct accessing of 128K bytes @ Use of a 6-byte general purpose register. in addition to the accumulator, allows to comprise three pairs of 2-byte date pointers. @ 9-bit timer capability © Three kinds of interrupts ® Non-maskable interrupt ® Maskable interrupt © Timer interrupt @) 82 instruction set @ WAIT function (memory access control possible) @ Clock Pd for input port (8-bit) and external latch (@) Memory backup function (BF1, BFO) LCD backplate signal control @) External crystal connection for clock generation @ Reducing program steps by means of 28-kind single step vector subroutine jump Do not sale this PDF !!! All and more about Sharp PC-1500 at http://www.PC-1500. info 2-2. Internal Structure 2-2-1. Block diagram Fig. 1-1 Block diagram of LHS801 10h XLO | XLI @OS WaT HA NMI MI HIN Osc@ator ; Interrupt ore | sontfol H counter . cep = Hs? ne backplate} | Riba J power VM ures A Timer supp ae “g sera controt VDIS vGG—* voc fle ™ oA | Buffer | { ] Internal bus Insteucton decoder Data bus: pu | pv | ose ps & CPU control control OPF BAK BRQ RESET OO RW MEOMETBFO BF DO~D7 INO~IN7 PU Py ISP Fig. 1-2 Internal register & flipflops PH SH XH YH UH aT PL SL XL YL UL A ™ * PB: Program counter S: Stack pointer . Xreg) Data pointer, *\Yreg |: oF af Ureg! general purpose register z A: Accumulator ; TM: Timer "pu ee 8 0 0/0/H_V Z1E/C) T: Status reqister }: General purpose flipflep PY DISP: LCD on/off contro! Do not sale this PDF !!! ** C: Carry and borrow (byte to byte) -- |E: interrupt enable + 2: Zero V: Overtlow ~~ He Carry (digit to digit} All and more about Sharp PC-1500 at http://(www.PC-1500.info 2-2-2. Internal registers Symbol Name Bit size Description P Program counter 16 Indicates the address next to the address the CPU is now in execution It will be incremented by “1° when the next instruction is fetched. $s Stack 16 Indicates the stack address — pointer A Accumulator 8 Used for retention of operational result or for data ; transfer with the external memory. XL 8 XL, XH. YL.YHLUL, UH comprise independent B- Xreg XH | @ | bit registers Also, used as 16-bit data pointers, Xreg. Yreg, and YL | 8 Ureg. when used in a pair. Yreg Data register I YH 8 UL & Ureg UH & ™ Timer counter 9 When "0" is set to the TM, it stops the counter action, When anything other than “0” is set, it puts the counter into action. When the TM turns full of “1” with the interrupt enable signal IE on. L_ CPU executes an interrup! processing PU } 1 General purpose flip-flop ee PV 1 nina 4 = —— DISP | 1 LCD on/off control. T | Status register 8 Low order 5 bits represent one of five status of | Operational result 2-2-3. Status flags Status lags, C, V. H, Z, IE are contained in the 8-bit status register. In general, flags other than LE change their state after the execution of arithmetical instruction. Status register T= 0 0 0 HV ZIEC! @ Carry flag C Carry flag C is set when there is a carry from the MSB and reset when there is no carry. For SUBTRACT, the flag is set when there is no borrow or reset when there is. @® Half carry flag H Half carry flag H is set when there is a carry from the bit position “3” (digit-to-digit carry) and reset when there is no carry. Q) Zero flag Z Zero flag Z is set when the operational result is zero and reset when not. @® Overflow flag V Overflow flag V is set or reset depending on the operational result of "C6 C7"; where, the carry from the bit position 6 of a single byte data is assumed to be C6 and the carry trom the bit position 7 to be C7. Single byte data B7 B6 BS B4 B3 B2 B1 BO Do not sale this PDF !!! All and more about Sharp PC-1500 at http://www.PC-1500.info 2-2-4. CPU pin description wOTONnN re © SBBSBS55n5SE82SS88R8858 Ze etaetedeceeaeteoeaetodcat ae cece aeactet 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 403 R/w 158 38| D7 Po 59 37| D6 Py |60 36] DS PU {61 35} D4 OS 162 34} D3 XLO 163 33) D2 XL | 64 32! DI “WAIT 165 31] DO IN? 166 30| MEO “Ke le LH5801 2 Mew IN5 68 (TOP VIEW) 28) OD IN4 169 27) HO IN3- | 70 26] HI IN2 | 71 25] H2 INI | 72 24) 3 INO 73 23) H4 Nc 74 22] H5 nc 175 21) H6 NC 176 20) H7 123.456 7 8 9 101112131415 16171819 rs a SoU Vvouxodgs n = ny WSEESESSLSESs2FslF 28 @ XLO, XL1 These are external crystal connection pins. X1.0 is the input pin and XLI is the output pin. Clock frequency is divided by two inside the CPU, When the 2.6MH+z crystal is connected, the CPU operates under |.3MH~z of internal machine cycle. @ ADO~AD15 Address bus, Outputs from these pins are 3-state (three output states of high, low and high impedance) and go high impedance with BRQ (Bus ReQuest). Basically, 64K bytes of memory area is supported for direct accessing, but it is made possible to access even 128K area of memory area when MEO and ME1 are used. @ DO~D7 Bidirectional data bus which is used to write or data to/from the external memory. @ MEO, ME1 Memory enable signals. As memory area of 64K bytes is accessed by MEQ and another 64K bytes by MEL, it permits direct access of memory area of 128K bytes in total. Since MEO is used for instruction fetch and stack operation, accessing by means of the program counter P and stack pointer S is limited to a maximum of 64K bytes. As for data accessing, both memory areas covered by MEO and ME1 can be controlled by a CPU instruction. Do not sale this PDF !!! 10 All and more about Sharp PC-1500 at http:/Awww.PC-1500.info ® as Through this line can be supplied the clock to an external system since the clock in the same phase as the CPU internal basic clock is on this line. Connection of the 2.6MH7z crystal oscillator to XLO and XL1 will supply the clock of 1.3MHz. © R/W Memory write signal, A low on this line causes the CPU to send data on the data bus. @ OD Output disable signal. A high on this line causes the CPU to prohibit data output to the external device. It is used in writing data to the memory. t . D0~-D7 MEMORY DATA! CPU DATA , ' ' ' ' ' Memory read cycle Memory write cycle @ RESET CPU reset input. High state of this signal resets the CPU and the contents of the address FFFEH ts set to the register PH and the contents of the address FFFFH to the register PL, When it turns from high to low level, it starts program execution from the address of the program counter. @ NMI Non-maskable interrupt input. High state of this signal causes interrupt to the CPU, to which the CPU unconditionally responds and starts the interrupt processing routine of which high order byte address is represented by the address FFFCH and low order byte address by FFFDH, Do not sale this PDF !!! All and more about Sharp PC-1500 at http://www.PC-1500. info @ Mi Maskable interrupt input. When the interrupt enable flag IE is active, a high on the pin MI requests interrupt, to which the CPU starts to execute the interrupt processing routine whose high order byte address is represented by the address FFF8H and low order byte address by FFF9H- How instruction execution address is determined against the reset and interrupt input External memory Address. EQ00H ——————= ———.. Start address by RESET input aa EI7IH —_| |_-—_____, Start address Be acas by MI input oe E22BH Lp Start address by NMI input Prag fo Nee E22CH — = ————.,, Start address by timer interrupt ESB EO (Si. SEES FFFBH E1H | 9 ma |! A E2H | 8 2cn |! c E2H " D ee E £OH \ FFFFH | 00H! "1 Do not sale this PDF !!! 12 All and more about Sharp PC-1500 at http://www.PC-1500.info @ BRQ Bus request signal. @ BAK Bus request ackowledge signal. When BRQ goes high, the CPU issues a high level of signal on BAK in response to it. The CPU keeps address bus (ADO~ ADIS5), data bus (D0~D7), MEO, MEI, R/ W, and OD high impedance when BAK is in high level. @ OPF Operation code fetch signal which is sent out when CPU fetches operation code (instruction code). OPF is issued only when operation code is fetched and will not be issued in fetching address data, immediate data, and second byte of the two-step instruction. os J \SVSVS\ i ‘ ‘ Last Operation code i cycle ’ fetch ' @ INO~IN7 Input port through which the CPU receives 8-bit data into the accumulator. As internal pullup resistor is used, the CPU assumes it to be high level when not connected, @ Po External latch clock. With high level of this clock, the contents of the accumulator is sent on the data bus, Addition of [C will comprise an output port. REFERENCE: ATP instruction. @® PU, PV These are CPU internal flipMlop outputs. PU and PV are furnished with set and reset instructions, Do not sale this PDF !!! All and more about Sharp PC-1500 at http://www.PC-1500.info @ WAIT CPU wait signal. A high on this line stops the clock @ so that the CPU halts its operation. As soon as WAIT turns low, the CPU resumes the operation. me F NSN [ \ walt a X. Fiipflop | ere WA NOTE. WAss the fliptiop dedicated to WAIT, by which the WAIT input is received at the falling edge of the clock OS. Because the CPU operating clock @ stops when WA is high, it makes the CPU stopped. consequently. @ HO~H7 LCD backplate signal output. As the liquid crystal display (LCD) is driven by backplate signals and segment signals, the CPU controls the backplate signals, @) VA, VB, VM, VDIS LCD backplate power supply inputs. @ HIN Input signal to the counter from which the LCD backplate signals HO~H?7 are generated. Normally, connected to pin HA of the CPU. @ HA CPU internal divider output pin. It is used for the basic clock that drives the LCD that connected with HIN and the segment signal generating LSI. @ DISP LCD on off control signal output which can be set or reset by means of instruction. @ BFO, BFI BE flipop output (BFO) and input (BFI). The BF flipflop is reset by the OFF instruction from the CPU, and will be set when the input BFI is turned to high level. BFO is in low level when the BF flipflop is set and in high level when reset. As VGG is power supply to the BF Nipflop. the contents of the flipflop are retained as long as VGG is in supply. Normally, it is used for memory backup system, Do not sale this PDF !!! 13 All and more about Sharp PC-1500 at http:/Awww.PC-1500.info 2-3. Functions 14 2-3-1. Timer The timer is a 9-bit polynominal counter. The counter value can be set by the AMO or AML instruction of the CPU. Shown in “POLINOMINAL COUNTER” is the list of hexadecimal data of counter with decimal count number. The timer operates continuously at all times. When the counter value reaches | FFH. it issues interrupt request to the CPU. If TE (Interrupt Enable) flag is active at that point, the CPU jumps to the timer interrupt processing routine whose high order byte address is represented by the contents of the address FFFAH and low order byte address by the contents of the address FFFBH. The timer has to be set to 0O0H when it is not used, Since it counts in synchronization with the clock ®F, cach one cycle of #F increments the counter one step. Oscillator | V/2 | | Divider oF When the 4MHz crystal oscillator is in connection, the timer is incremented at cach 32usec, because @F is 31,25k Hz. Do not sale this PDF !!! All and more about Sharp PC-1500 at http://www.PC-1500. info “POLINOMINAL COUNTER” COUNT DATA OF COUNT DATA OF COUNT DATA OF COUNT DATA OF COUNT DATA OF NUMBER COUNTER NUMBER COUNTER NUMBER COUNTER NUMBER COUNTER NUMBER COUNTER 511 510 SSSRESKRSSSSSSRSSRRSRS 478 477 476 475 aia 473 472 47 470 468 467 466 465 464 463 462 461 460 IFF OFF OvF O3F OF OOF 107 183 1¢c1 1E0 OFO 178 18C 1DE EF 157 OFB 070 O3E VF V4? 1A3 10) OE8 074 13A 19D OCE 067 133 04c 013 104 082 041 120 148 OA4 129 194 1CA OES 172 1B9 ope 16E 459 458 457 456 431 427 426 425 424 423 422 421 420 419 418 417 416 415 414 413 412 4il 410 408 087 058 02D 116 188 1C5 1E2 OFT 078 13¢ 19E 1CF 1E7 1F3 org o7c 13E 19F OCF 167 183 0b9 06C 036 1B 08D 146 OA3 151 12A O4A 2 189 1c4 OE2 071 038 Ne 18E oc7 163 181 008 16C 086 183 OAD 156 SSSSPSSSRESRSSZssssesseRS $84 381 SSSSSIRSRKR Ress 1AB 105 OEA ZSRSSSISSSRER=SSRS=ERE SRRESBESSEEL = g REERBSERS 88 110 188 0c4 062 031 O18 10¢ 121 190 1c8 0E4 072 139 ogc 14e SSSERSRRRER 345 333 332 331 321 319 318 317 316 315 314 313 312 311 310 309 308 307 306 305 304 Do not sale this PDF !!! QA? 153 OAS 154 TAA 005 OBA 035 OIA 100 186 0c3 161 180 108 1EC 178 OBD OSE 12F 197 0cB 165 1B2 1b9 OEC 076 138 03D O4E 027 113 144 OA2 051 028 014 10A 142 OAI 150 1A8 16A 12D 196 1cB BRIIBRSSES 293 8 i 291 88 287 284 283 282 281 280 279 278 277 276 275 274 273 272 271 RIFRSIRSSRSIBBS 255 254 253 252 15 1F2 1F9 OFC WE 1BF ODF O6F 137 098 04D 126 093 049 124 092 149 1A4 002 169 1B4 1DA 1ED 1F6 1FB OFD O7E 13F OsF O4F 127 193 164 082 159 OAC 12B 195 OCA 132 199 888 019 838 101 15 All and more about Sharp PC-1500 at http:/Awww.PC-1500.info COUNT DATAOF COUNT DATAOF| COUNT DATAOF| COUNT DATAOF) COUNT DATA OF NUMBER COUNTER NUMBER COUNTER NUMBER COUNTER NUMBER COUNTER NUMBER COUNTER 251 180 199 O9A 1A? 141 95 OOE 43 oc 250 oco | 198 14D 146 1A0 94 007 42 1OE 249 060 197 146 145 ODO 93 103 4 087 248 030 196 0b3 144 168 92 181 40 143 247 8 195 069 143 OB4 31 1c0 39 VAI 246 sc «194 134 (142 15A 90 EO 38 100 245 Océ 193 19A 41 1AD 89 070 7 1E8 244 063 192 1cD | 140 106 88 138 36 OF4 243 131 191 1e6 | 139 TER 87 Isc % 17A 242 038 190 OFS 138 15 86 ICE 4 18D 241 14C 189 073 137 OFA 85 OE7 33 ODE 240 OAG 188 osc (136 170 84 173 32 16F 239 053 187 We = 135 OBE 83 oB9 3i 187 238 029 186 WF 134 1SF 82 5c 30 008 237 114 185 1c7_ 133 OAF 81 12E 29 06D 236 18A 184 1€3 132 157 80 037 28 136 235 och 183 1F1 131 OAB 79 048 27 198 234 162 182 ore 130 155 78 125 26 ocd 233 081 181 7c 123 OAA 77 192 25 166 232 058 180 1BE | 128 055 76 ic 24 0B3 231 Vee | 179 WOF | 127 02A 75 1e4 23 059 230 096 178 OEF | 126 015 74 OF2 22 o2c 229 4B | 177 77 | (125 0A 73 179 21 O16 228 TAS 176 OBB 124 005 72 oBc 20 108 227 102-175 OSD | 123 102 n 15E 19 185 226 1E9 | (174 O2E | 122 081 70 TAF 18 1C2 225 1F4 173 017, | (12) 140 69 107 7 O€1 224 IFA 172 008 | 120 AO 68 OEB 16 170 223 WO 171 105 | «119 050 67 175 15 188 222 OFE 170 182 8 128 66 OBA 14 1DC 221 17F 169 oct | 17 094 65 15D 13 TEE 220 OBF 168 160 6 14A 64 OAE 12 Or? 219 O5F 167 060 11S OAS 63 057 WW 078 218 02F 166 58 | 114 152 62 028 10 03D 217 7 165 1ac 13 1A9 61 5 9 Ole 216 ose 164 006 | 112 104 60 8A 8 10F 215 145 163 168 mW 1EA 59 045 7 187 214 1A2 162 185 110 OFS 58 122 6 1¢3 213 0D1 161 ODA 109 O7A 57 091 5 161 212 160 160 | 108 130 56 048 4 1FO 211 034 159 1B6 107 OSE 55 024 3 1F8 210 IIA 158 108 106 14F 34 012 2 IFC 209 18D 157 OED 105 1A7 53 109 1 FE 208 1c6 «156 176 104 103 52 184 0 1FF 207 0&3 «155 188 103 £9 51 oc2 206 171 154 opD = 102 174 50 061 205 obs 153 o6e = s101 IBA 49 130 204 C152 037——«100 10D 48 198 203 0 Se O18 99 OEE 47 1¢C 202 Ob? 150 000 98 077 46 OE6 201 O6B «149 106 97 038 45 073 200 135 148 083 96 01D 44 039 16 Do not sale this PDF !!! All and more about Sharp PC-1500 at http://www.PC-1500.info 2-3-2. Interrupts There are following three kinds of interrupt for the LHS801 CPU. @ Non-maskable interrupt When NML is turned from low to high level, it sets the flipflop [RO active, upon which time interrupt is requested to the CPU, so that the CPU starts executing the interrupt processing after completion of current instruction execution, Since the non-maskable interrupt is given with the highest priority order, the interrupt will be acknowledged at once, regardless of its internal state. IRO will be reset in a course of the interrupt process, As the NIM input is sampled by the clock @H, it will become 250k Hz when the 4M Hz erystal oscillator is connected. CPU internal XLO = Oscillator] % Divider tb-— fH Xu ere eS ee a A} a \ Synchronizing pulse if j 77 Reset IRO Inte Instruction execute partie am 6 Interrupt processing —— = When NML is turned high, the CPU creates synchronizing pulse at the rising edge of the clock ®H, which sets IRO active. HIRO is active when the CPU acknowledged the interrupt after completion of execution, it goes into the interrupt routine and IROis reset in a course of the interrupt processing. 17 Do not sale this PDF !!! All and more about Sharp PC-1500 at http://www.PC-1500.info Non-maskable interrupt processing sequence ESESR If S=1005H before going into the interrupt aon process, the contents of T and P are ( Piva ama CT Ong ) stacked, and it becomes S=1002H after the processing. Y TS Value of S) —> 1002H ios after mterrupt st 1003H PH O-lE 0-+ IRD 1004H PL PL-(S Vale of S > 10054 1 $-1I—S before mterrupt - PHS $-1-$ (FFFCH)-*PH (FFFOHK)—-PL L~ J Ld @ Maskable interrupt When MI is turned from low to high level, it sets the flipflop IR2 active. If the interrupt enable IE is active at this point, interrupt is requested to the CPU, so that the CPU starts executing the interrupt processing after completion of current instruction execution. IR2 will be reset in a course of the interrupt process. When interrupt request is issued while IE is inactive. the interrupt will be ignored even though IR2 is set. MI input is sampled in the same manner as in the case of NMI Maskable interrupt processing sequence Sis O-siE --iR2 PLS) So i-s PHS. $ Pes FRREM) <P FROM PL I Do not sale this PDF !!! All and more about Sharp PC-1500 at http://www.PC-1500. info © Timer interrupt When interrupt is requested from the timer. it sets the flipflop IRI active. If the interrupt enable IE is active at this point. the CPU starts executing the interrupt processing after completion of current instruction execution, and IRI will be reset in a course of the interrupt process. When interrupt is requested while TF is inactive, the interrupt will be ignored even though IRE is set. Timer interrupt processing sequence Pelor foative ten festracton fescuton fetch | Le) S ies reels: a tS FFF AM ort FFF D oo ae Return to main routine The RTI instruction is used for returning from the interrupt processing routine to the main routine. Because the contents of the T register and the program counter are stored in the stack at the beginning of the interrupt processing routine. the contents of the T register in the stack returns by the RTI instruction. Since the interrupt enable flag IE is contained in the T register, the contents of IF immediately before the interrupt returns by the RTI instruction. To disable maskable or mer interrupt by the main routine after returning from the interrupt processing routine, the bit in the stack corresponding to the flag 1E must be reset, Priority order of interrupts (1) Non-maskable interrupt responds to the interrupt request whatever the CPU internal state may be. prove Also, it responds in the first priority - one pererrroy oa iig even during execution of interrupt | oon routine by other interrupt. Lee Do not sale this PDF !!! "° All and more about Sharp PC-1500 at http://www.PC-1500. info 2-3-4. CPU system sequence Reset procerning + v a Non-maskable eeueee Maatiabi tas mietupt wterupy wiettupt peacessng | processing rowtne PrleP a Instruction acc ubon ¥ yv ¥ ¥ Do not sale this PDF !!! 21 22 All and more about Sharp PC-1500 at http://www.PC-1500.info 2-3-5. BF flipflop The CPU has two supplies of power; VCC and VGG. As the BF flipflop is driven by WGG, the state of the BF flipflop is retained as long as VGG is in supply. even if VCC supply is out. The BF flipflop is set when the BFI input is turned from low to high level and reset when the OFF instruction is issued from the CPU. Low state of signal is on the BF flipflop output BFO when the Mipflop is active and high state of signal when inactive. mrcctr ee == ao a 4 o oO || |_J ee 1 BE fiptop : m4 ss Q CPY LOGIC we R Q /}——_o aro 1 1 SNDO— = ' eee SEER Tiles Ca cal 0 Sab ede el Foc sFaee ge en ee gts 4 o BF It is possible to comprise a memory backup system using this BF flipflop. Do not sale this PDF !!! All and more about Sharp PC-1500 at http:/Awww.PC-1500.info 2-3-6. WAIT function (interfacing with the slow access time memory) Because the CPU access time is very fast, the CPU must be held with the wait signal in order to access a slow access time memory. Basically, the wait signal is created by the externally provided counter, but the 1 O part controller with the programmable wait time control feature (LHS8511) is used for this purpose. For more details of this function, refer to the section discussing the | O port controller. Shown in the next page is the connection of the CPU with the 10 port controller. CFU Re —_ 003 |___R// W—_—>1 MEO MEI K— po~ D7» K—— WAIT 1/0 port controller p> DMEO -——> OME! MEO > wait condition, | MEI wait wo wi ADQ~ADID condition} Do not sale this PDF !!! 23 All and more about Sharp PC-1500 at http://www.PC-1500. info 2-4. LH5801 instructions 2-4-1. Outline 24 This section deals with function of each instruction. ¢ ADC Instruction name | Functional description | ®Format ADC RL Operand ®Operation A+ [operand] +C — A — Symbol ‘_$ymbol — Symbol (EX) ( Example ] Symbols used in discussing operand, function, and operation A: Contents of the accumulator (8 bits) XL: Contents of the low order 8 bits of Xreg VL: Contents of the low order 8 bits of Yreg UL: Contents of the low order & bits of Ureg (RL. represents either of XL. YL. or UL.) XH: Contents of the high order & bits of Xreg YH: Contents of the high order & bits of Yreg UH: Contents of the high order & bits of Ureg (RH represents either of NH. YH. or UHL.) Xreg: Contents of the X register (16 bits) Yreg: Contents of the Y register (16 bits} Ureg: = Contents of the U register (16 bits) (Rreg represents either of Xreg. Yreg. or Ureg.) Rr Contents of the program counter (16 bits) Bi Contents of low order 8 bits of the program counter PH: Contents of high order 8 bits of the program counter Ss: Contents of the stack pointer (16 bits) Sk: Contents of low order & bits of the stack pointer SH: Contents of high order 8 bits of the stack pointer (Rreg): Contents of the memory represented by Rreg (accessed with MEO) #Rreg) Contents of the memory represented by Rreg (accessed with MEI) (ah): Contents of the memory represented by 16 bits of ab (accessed by MEO): where a represents high order & bits of the address and / low order 8 bits Do not sale this PDF !!! All and more about Sharp PC-1500 at http:/Awww.PC-1500.info #(ab); Contents of the memory represented by 16 bits of ab (accessed by MEI); where a represents high order & bits of the address and 6 low order 8 bits i: 8-bit immediate data A l6-bit immediate data of which high order 8 bits are represented by j and low order 8 bits by / G Carry flag IE; Interrupt enable flag Z Zero flag V; Overflow fag H: Hall carry flag = Data flow direction A AND V OR Exclusive OR + ADD = SUBTRACT 2-4-2. Add, subtract, and logical instructions @) ADC (ADd with Carry) Either the contents of the internal register or external memory are 8-bit added with the accumulator including carry, and its result is stored in the accumulator. C,H. Z. and V may change. ¢ Format © Operation ADC RL. ADC RH ADC (Rreg) A+ [operand] +C — A ADC #(Rreg) ADC (ab) ADC #{ab) (EX) ADC XL Value of the XL register is added to the accumulator, providing “C=0". A= 000 0 0 0 1 0 Execute A 0011 0 = C=0, H=0, 2=0.,, V=0 XL= 0011004141 25 Do not sale this PDF !!! 26 All and more about Sharp PC-1500 at http://www.PC-1500. info @ ADI (ADd Immediate) ‘To either the accumulator or the external memory is added the immediate data, In the case of ADI to the accumulator, carry is included in the operation. C,H, Z. and V may change. Format @ Operation ADI AJ Pay Ss it OY ADI (Rreg)i {operand] + / ~ [operand] ADI #(Rreg)i ADI (ah) ADI #(ah)i (EX) ADI (Xreg), 20H 20H is added to the memory represented by X register. Xreg=4FOOH Execute Contents — , Contents _ are 188 tO 8 8 of foo LO_! @ 1 0 0 | 0 C=0 , H=0, Z=0, V=0 @ DCA (DeCimal Add) Decimal addition is carried out between the external memory and the accumulator including carry, and its result is stored in the accumulator, C,H, Z, and V may change. Format © Operation DCA (Rreg) I) A+ 66H — A DCA #(Rreg) 2) A+ [operand] + C —- A (C,H, Z. and V may change.) 3) A+DA—A Where. DA is used for compensation of decimal number which is dependent on the value of flags C and H in regard to Item 2). c H DA 0 0 SAH i] 1 AQH ] 0 FAH 1 1 OOH (EX) DCA (Yreg) Decimal addition is carried out between the memory represented by the Y register and the accumulator. Y reg = 4700H Contents After execution of DCA c es Decimal addition of 4700H c H A 35H 27H 0 0 1 62H 354 27+0-—62 35H 27H 1 0 1 63H 35+27+1-—63 35H 67H 0 ] 1 02H 35467 + 0=102 35H 67H 1 1 1 03H 35 167+ 1=103 Do not sale this PDF !!! All and more about Sharp PC-1500 at http://(www.PC-1500.info @ ADR (ADd Rreg) Contents of the accumulator are added to the R register. C,H. Z. and V may change. Format © Operation ADR Rreg 1) RL+A— RL (C,H, Z, and VY may change.) 2) RH +C— RH (EX) ADR Xreg Contents of the accumulator are added to X register. A=(1100001 1] x=/0 1001011 ~ , Execute — XL=/1 000100 0\)-+xXH#= 00001011 C=1, H=0, Z=0, V= xH- 00001010 Pie SI @® SBC (SuBtract with Carry) The contents of the accumulator are subtracted by the internal register or external memory including C, and its result is stored in the accumulator. This operation may also be expressed in the following manner. Complement of the internal register or external memory is obtained first, addition is carried out including carry, then its result is stored in the accumulator. C,H, Z, and Y may change. Format © Operation SBC RIL. A [operand] -C ~ A SBC RH (C,H, Z, and V may change.) SBC (Rreg) or, SBC #(Rreg) A+ [operand] + C - A SBC (ab) (C, H, Z. and V may change.) SBC #(ab) (EX) SBC XL Contents of XL register are subtracted from the accumulator. a= [0011100 0) x=|0 0100001) c=0 A= (00111 0 0 O} gute ——— A=(0 0010111 XL= 1 10 1zvit oO} =1 , H=1 , Z=0:, V=0 c=1 27 Do not sale this PDF !!! 28 All and more about Sharp PC-1500 at http://www.PC-1500. info © SBI (SuBtract Immediate) The contents of the accumulator are subtracted by the immediate data including C. C. H. Z, and V may change. © Format © Operation SBI AJ A-i-C-A (C,H. Z. and V may change.) or, At+i+C—A (C,H. Z. and V may change.) (EX) SBI A, 07H A='0