Schematic · 1980
Sharp's service manual for the PC-1211 pocket computer (Radio Shack's TRS-80 Pocket Computer) and the CE-121 cassette interface: specifications, block diagram, RAM maps, display and power circuits, LSI signal descriptions, disassembly, cassette format, check program, circuit diagrams and parts lists.
SHARP - SERVICE MANUAL w ¢ € (~ ; = | | | MODEL PC-1211, CE-121 | | CONTENTS | [SOR Gad enters sree Se ee ere ee eee ee 2 | PSB lOCK Un gIaN =a s see pS oe SS ee 4 | 32 ES Usignallesch DUOU saa oa ee oe ee 12 | AAD OU SERVICED reese ss geese Se Se esses a 6 a ow ae SI ee ei 17 | 5 Cassttle-OperatiOn =~... ace = Se ee ee eS ee 18 GC RECKSp iO Stan are arrest wee eevee ewe Se 25 | 7 GUChIia aM eae ee ae es he 26 | 8: PC 12 partslist @guide= 94 Gee ee 30 OGRE leal ts St Gap IG eat agente et Sa ee 34 | SHARP CORPORATION 1. SPECIFICATIONS CA/BREAK x h < > = = | Fe Ton} vm HoAonomee eo : Ss + 8 % ¥ 7 5 5 = = TMM OoOoO eo oo & & we fa) a ft) f= ; = Ss oe ee ee resenvaowe xevs) [0] (+) (Exe) FE) (©) 1-1. Display @ Display tube: LF8017JE @ Display method: 5 x 7 dot matrix liquid crystal @ Display capacity: 24 coulumns (alphanumerics and symbols) 1-2. Basic functions ©@ Computational capacity: 12 digits of mantissa and 2 digits of exponent. © Computational method: According to mathematical formula (with priority consideration and judge function) © Capacities: Program memory; 1424 steps, max (PC1211) Daia memory; Fixed memory 26 memories Flexible memory (commonly usable with the program memory) 178 memories, max (PC1211) Reserve program; 18 kinds, 48 steps, max Input buffer; 80 steps e Buffers: Data buffer; 8 stages Functional buffer; 16 stages (but 15 stages for parenthesis) Subroutine buffer; 4 stages “FOR NEXT” stagement buffer: 4 stages 1-3. Arithmetic functions Add (+), Subtract (—), Multiply (+), Divide (/), Power raising (A) Trigonometric functions: SIN (sine), COS (cosine), TAN (tangent) Inverse trigonometric functions: ASN (sine! ), ACS (cosine~'), ATN (tangent™' ) Logarithmic functions: LOG (common logarithm), LN (natural logarithm [In] ) - Exponential functions: EXP (exponential) Angular transformations: DMS (decimal notation to sexagesimal notation), DEG (sexagesimal notation to decimal notation) Square root extraction: Signum function. SGN Absolute value: ABS (| X 1) Interization: INT Execution of arithmetic operation is commanded by the ENTER key. wo —— ale) en) oa. On 1-4. Editorial functions Cursor shift: P (right), <q(left) Insertion: INS Deletion: DEL Line control: + (down), t (up) 1-5. Programming language BASIC (Beginner’s All purpose Symbolic Instruction Code) 1-6. Power source Battery: Four MR44 (mercury batteries) Battery life: 300 hours Power consumption: 0.011W Automatic power shut off: About 6 minutes 1-7. Others Data protection: Program memory, data memory, reserve program memory Peripheral unit: Audio cassette unit (recording/reading of the program memory, data memory and reserve program memory) Physical dimensions: 175(W) x 70(D) x 44(H) mm Vw vw 0/1 NOILdO TVNOIS OLOWAY| LAD} V1vd| ) ) ‘ON.LNOD| NOI LdO| TVYNOIS ONIGVOT LD! S ONIGXOOSN WO} dA > BIN ada | dS1d. = waMOd ees aA = as WA = VA wx oN 91m | 490 lL & pg NO Sr eya UX om” vs STS" FIS PpResd gts [ Ee #Old~1o1d ey sis S2T8V9S | == 1 army 2889S Meas ma CADE unad = 49s I nado r —{9s ae qsa~ Ue [|| ega~eral] era PAIS Na 8 x= Va ale see Lit bez icles IM~ TIM def Pd I =: Be tae r ie exd!aM | ory ev! S a3 U 8Y~IV 2 WV4 £ d ZS $ Fd |e) AAAAD Se] =||° ata 1 Plo ea ed Y : Hl WoV 4 H {EURORD a Siae API oe nest seg aig °F a diy derdsia @x (Gree OS) LH~H a 7, £ x OFS~IS a O21 AWD WVYDVIC MOOT" *c rr om ) ) System configuration (see the system block diagram) System of this unit consists of the following components: 1) CPUI (SC43157)x 1 2) CPU II (SC43178) x 1 3) 4K-bit RAM (TC5514P x 3) 4) Display chip (SC43125 x 3, with built-in RAM) 5) 2AND gate (TC4011UBP x 1) 6) 2AND 20R (TC4019BP x 1) 7) Inverter (TC4069BP x 1) 8) Quard Analog Switch Multiplexer (TC4066BP) 9) LCD (24-digit FEM dot LCD) 10) Key 11) Crystal (CSB2560) 2-1. CPU |, CPU II These CPUs are provided with internal ROM, and each of CPUs shares the following assignments: CPU I Key input routine Acknowledgement of the remaining program One instruction to one program step incorporation Interpreter: Program execute statement Cassette control statement Command statement Printer control Execution of manual operation { Power shut off control | Clock stop control | @ The CPU I functions to read key-in data or read the instruction to be executed from the RAM, and decides what is to be done for the control of arithmetical operation (i.e. control of arithmetic sequence, memorizing of arithmetical data, and its readout), or interprete the syntax of the BASIC instruction for deciding what is to be executed, or determines and prepares the information to be displayed, but the CPU I does not perform any execution by itself. It only arranges the data and information in proper sequence and acts to provide instruction code to the CPU II via the buffer. On the other hand, the CPU I! constantly receives execution instructions from the CPU I via the transfer buffer and executes operation against each of instructions or sometimes performs to exchange data depending on the situation. Although it shares major part of execution in term of execution, it performs some kinds of auxiliary CPU when looked in the CPU I Display processing routine Input buffer Computational result Error Arithmetic routine Character generator Cassette routine Print routine Buzzer Recognition of printer [ Power off | Clock stop view that it does not perform any decision by itself. Ex: Actions of CPU I and CPU II at the time of key data entry. ‘Acknawledge- ment of the operational Entry of the key-in data into the input buffer Instruction to CPU II (display) Read in CPU I Notifying the completion of operation to CPU I Reception of the instruc- tion from CPU I Decoding of the instruc- tion Display CPU I In the case of manual operation of the pocket computer, the instruction code (key code) is written into the RAM in the display chip (input buffer) after information is put through the keyboard and converted into the instruction code by the CPU I, then this instruction code (display, at this case) is transfered to the CPU II via the transfer buffer. As the CPU II receives this instruction, the CPU II then decodes this instruction (display, at this case) and executes display processing. Upon the completion of this processing, it is then notified to the CPU I, then the CPU I confirms the comple- tion of the task by the CPU II before terminating their jobs. ne — ( ( o™ 2-2.RAM A certaifi number of C-MOS RAM (1 ~ 3 chips, 4K bits each) and another RAM incorporated inside the display chip are used in this pocket computer, having varieties of configurations as described below: om © Map of 4K-bit RAM 1536 Bytes 001 Reserve program 048 ng etion on to ] oo id Am e) II he le- Program -_ or flexible memory _— Que ee ese 1472 Fixed memories (W ~ Z) Fane Although RAM area is mainly shared by the program, data -~ Subroutine | FOR NEXT and reserve program memories, it is also used for the sub- stack ee eDe is routine stack, FOR NEXT statement stack and fixed cian memories (W, X, Y, Z). -~ @ Map of the RAM incorporated in the display chip There are three 1K-bit RAMs (128 bytes each) incorporated in each of display chips (SC43125), having the following configurations: DISPLAY CHIP 1 DISPLAY CHIP 2 DISPLAY CHIP 3 000 8-digit display buffer 8-digit display buffer 8-digit display buffer 040 Transfer buffer 048 Fixed memories Fixed memories 80 step input buffer (A~K, 11 memories) (L~V, 11 memories) 128 @ 8-digit display buffer 40 bytes of 8-digit display buffer is used as a display data buffer during displaying and also used as a buffer memory for arithmetical result during the arithmetical operation. e@ Fixed memory The total memory of 176 bytes from the display chip 2 and 3 is used as a fixed memories, A~V (22 memories). 4bit 1 memory le 16 bits >| e Transfer buffer 8 bytes (1 memory equivalent) of the display chip 1 is used as a transfer buffer which is used in the transaction of instruction between the CPU I and the CPU II. @ Input buffer Remaining 80 bytes (10 memories equivalent) of the display chip 1 is used for the input buffer, which is used in the following functions: 1. Any information entered through the keyboard is stored once in this buffer, thus allowing up to 80 steps. 2. The display contents is stored by the CPU I and the CPU II makes selection out of this data. 3. When an arithmetical instruction is entered, its procedure is stored in this buffer by the CPU I and the CPU II performs operation according to this procedure. 4. When program or reserve program is to be recorded or read out during the execution of the cassette control instruction, action takes place through this input buffer. ct ( a) 2-3. Display The contents of display indicated by the CPU I is received by the CPU II via the input buffer and makes converted into respective character codes, then they are carried over to the display buffer in the display chip through the address data bus. @ Designation of the display data The following structure is observed in the display buffer in the display chip. There are 8 x 40=320 bits (40 bytes) of area in the display buffer in the Counter/ 5 is HAT decoder display chip. Ex: Displaying numerical figure “4” ‘ 1 A8 A7 A6 A4 H8H7 H6H5 H4H3 H2 H1 x 001) 1 00 0Fss1 H1 x 0 0 1{ 0 1 0 0; »s2 inl fara ee HB H5 > S16 H6 ee og = “ DOsgsooo * OOmOs8o00 ¢ OOBOO8O ‘ BEGGS OOB@OO000 ) ) Q r>Ss17 H7 i es ei a {- ae cae r> S18 001 Display buffer | ee b> s32 Gelaectats thee tetris In ai laeeote st Pee 1 r> S 34 0 1 0 \ F 12 wal fea Pr s40 Address oF iupiedftepoef> iholedae lam DI04 DI02 DI04 D102 A5=1 A5=0 Fig 2-3-1 The numerica figure ‘4’’, to be displayed by the CPU II, is converted into the relevant character code and carried through on the address data bus. First of all, the segment S1 is selected with the address A8~A1 “00000000” to store the data DIO4~DI01 “1000” in the display buffer (see Fig. 2-3-1). To store second half 4 bits of the data, only A5 in the address in turned “1” to make the address “00010000” to store data “0001”. In the same manner, the address “00000001” is selected for storing the first half 4-bit data “0100” for he segment S2 and the second half 4-bit data “0001” is stored with the address “00010001”. ice een epeeeieenees Se kl re y $1 VT Sy pe Depleted ee VB $2 Fig 2-3-2 HA: Clock frequency for the counter. This signal is counted and decoded to perform synchroni- zation with the comman signal, HI1~H7, generated from the CPU II. DSIP: With high level of this signal, processing of display operation is indicated (RAM data designated by H1~H8 is sent out on S1~S40). The data stored in the display buffer is carried through S1~S40 (Fig. 2-3-2) to be fed to the LCD. (To indicate “4” on the display, H4 and HS are engaged for $1, H3 and HS for S2, etc., all the same throughout S6~S40.) 10 " ( lice’ ¢ 2-4. Power source —W —® GND 5) be TY rd Pa) at 22 ia any =. as ee A “gs af _ g ee! 28s { Sap MOS FET ce g¥ 38 8 kh a a cfg OVDISP Relation between temperture and VDISP Voc Yop cPUn Ps o° 20° 40° +c Pe © The liquid crystal reference voltage VDISP is generated in the above circuitry in order to avoid occurrence of such unpleasant phenomena as blurred character or contrast variation that might degrade display performance, which is caused by a slight voltage variation in the liquid crystal reference voltage VDISP, since the 5 x 7 dot matrix liquid crystal is used in the display of this pocket computer. A) VDD is generated in the CPU II on the basis of VGG. - B) The gate voltage of MOS FET is controlled by the 250KQ pot to regurate the voltage for VDISP. Furthermore, the voltage of VDISP is changed by the thermistor to meet with temperature varia- tion, so as to maintain proper display performance. C) Line between the reference voltage VDISP and GND is divided by resistor to make out VA, VM and VB. y VDISP: Low side voltage of common signals (H1~H7) for LCD. ae a VA: High side voltage for segment signals (S1 ~ S40) VM: Intermediate voltage of the common and segment signals ala VB: Low side voltage of segment signals. _ NOTE: VA, VM and VB become pulses in an amplitude of several volts owing to influence oD. caused from the LSI. ime © Adjustments of reference voltage VDISP The VDISP had been precisely adjusted to become —3.74V at an 30° Eye position ambient temperature of 20°C and —4.29V at O°C. In case there is a need of readjusting the voltage after servicing the LCD or exchanging some of power source components, be sure to look on the LCD from Cl 30° of angle from the vertical line while adjusting the pot. VDISP ae a, 11 3. LSI SIGNAL DESCRIPTIONS 3-1. SC43157 (CPU 1) Pin No. | Signal name | In/Out Description 1 F4a Out Chip Enable signal (RAM3 select signal) 2 F3a Out Chip Enable signal (RAM2 select signal) 3 F2a Out Chip Enable signal (RAMI select signal) 4 Fla Out Chip Enable signal (Display chip 1 select signal, for input buffer and transfer buffer usage) During display: Low i a aa ; oa During read-in: turns momentarily high pe 6 Voc In Source voltage (““—”’ voltage of battery) 7 Voc In 8 Xin In Basic clock (pulse signal in 256KHz) 9 TEST1 Z 10 TEST2 Connected with GND 11 RESET In All reset switch input Normally high but turns low when the all reset switch is depressed. 12 R/Wa Out RAM Data Read/Write signal Dung display Thigh’ ogejioy spassie: adi mevwied ont C Depression of the key causes it momentary low/ 13 DIO1 In/Out Data Bus (for address designation of the input buffer and 14 DIO2 In/Out transfer buffer in RAM and display chip 1). 15 DIO3 In/Out During display: High SAS a 16 DIO3 In/Out During read-in: Low LAA 17 B8a Out Address Bus (for address designation of the input buffer and 18 BJa Out transfer buffer in RAM and display chip 1). 19 B6a Out Ee, Se 20 BSa Out During display: tage Mementary generation 21 B4a Out 22 B3a Out During read-in: TU. 23 B2a Out 24 Bla Out 30 GND In Source voltage (OV) 40 Sl6a Out Busy signal to the CPU II (High during the execution in the CPU DD During display: Low During read-in: turns momentarily high 12 C-£ ¢ ’ ro ow j Pin No. | Signal name] In/Out Description 41 Sn Out Key Strobe signal, RAM Address signal 42 Si Out Key Strobe signal, RAM Address signal 43 S13 Out Key Strobe signal 44 $12 Out 45 S11 Out During display: High 46 S10 Out Depression of the key causes it momentary low 47 s9 Out 48 S8 Out 49 87 Out 50 S6 Out 51 SS Out 52 S4 Out 53 $3 Out 54 S2 Out 55 Kil In Key input signal 56 Ki2 In 57 Ki3 In During display: Low 58 Ki4 In Depression of the key causes it momentary high 59 S16b In Busy signal of the CPU II (high during the execution of the (KiS) CPU II) During display: Low J Depression of the key causes it momentary high 3-2. SC43178 (CPU Il) Pin No. | Signal name] In/Out Description 1 F4 Out Buzzer signal When the buzzer is off: Low —>{0.25ms— When the buzzer is on: 2 F3 Out Chip Enable signal (Display chip 3 select signal) a F2 Out Chip Enable signal (Display chip 2 select signal) 4 Fl Out Chip Enable signal (Display chip 1 select signal) During:display: Low tgp} ae do During read-in: Turns mementarily high 2 eee 5 VDD Out For liquid crystal drive voltage preparation (VDD = VGG) 6 VGG In Source voltage (““—’” voltage of the battery) if VGG In 8 Xin In Basic clock (Pulse signal in 256KHz) li RESET In All reset switch input 13 Pin No. | Signal name] In/Out Description 12 R/W Out RAM Data Read/Write signal During display: High During read-in: Turns momentarily low——*- - - - - - - 13 DIO4 In/Out Data Bus (for data transaction between RAM and display chip) 14 DIO3 In/Out During display: High ¥5 DIO2 In/Out During read-in: Turns low-___\ \ \ \ \ \ \ 16 DI01 In/Out 17 B8b Out Address Bus (for address designation of the display chip) 18 B7b Out During display: Bl b=high, B2B=low, B3b=low, B4b=low, 19 Béb Out BSb=high, B6b=high, B7b=low, B8b=low 20 BSb Out During read-in: Turns momentarily high 21 B4b Out 22 B3b OG tend |e tee a ye 2 eee 23 B2b Out 24 Blb Out 25) HA Out Display signal (Common signal counting pulse) a Fs Being generated during displaying ssoismsks 26 DISP Out Display command signal During display: High During execution: Low 27 VM In LCD display voltage (Intermediate voltage of the segment signal) 28 VA In LCD display voltage (High side voltage of the segment signal) 29 GND In Supply voltage (OV) 30 H4 Out LCD common signals (backplate) cpl H7 Out a2 H3 Out és) H6 Out 34 H2 Out 35 HS Out 36 H1 Out 37 VDISP In LCD display voltage (Low side voltage of the common signal) 38 VB In LCD display voltage (Low side voltage of the segment signal) 39 S16 Out Busy signal to the CPU I (High during the execution in the CPU II) During display: Low f Depression of key causes it momentarily high’ 40 S15 Out Record signal to the cassette tape and print data. 41 S14 Out Remote signal to the MT. 14 ( ¢ € 1 a) Pin No. |Signalname] In/Out Description 42 $13 Out Busy signal to the printer. 43 $12 Out Expansion signal Er During display: Low is Depression of the CA (ON) key causes an instant pulse generation. 49 S6 Out For DEF symbol display (engaged: low, not engaged: high) 54 Sl Out For symbol display (SHIFT, DGE, RAD, GRAD, RESERVE, PRO, RUN) Same waveform as the segment signal. 5) Kil In CPU I Busy signal (High during the execution in CPU I) (S16a) 56 Ki2 In Expansion signal To be connected to $12 (CPU II) for PC-1211. By) Ki3 In Printer Busy signal Low when the priner is not operated. 58 Ki4 In Printer connection identifying signal. Low when the printer is not connected. 59 iS In Cassette reproduct signal. 60 Ki6 In ON key input signal 16 see fia IR} TC4011 UBP ( Quad 2-input positive NAND gate ) VoD 14 1 ce) 1 i) ll 10 9 ala TC4069 P (HEX inverter ) val =) Gi ) [t iY LJ 7 GND C 4s 43 Jt 5 6 TC4019BP ( Quad AND-OR select gate ) 140 Lue 6 O— 70 (o—— 16 TC4066BP ( Quad bilateral switch ) 4— 1 Nour OUT AN i—— 10 ( ( 4. ABOUT SERVICING Screw bats © Disassembly procedure Screnla) g 1) Remove the 2 screws (a) and 2 screws (b). 2) Separate the upper cabinet CS from the lower cabinet from the screw side, as they are latched together at three points, A, B, and C. e Repairing procedure 1) As the back of the arithmetic WE — —— printed board comes into A isi ae kaa ¢ sight after the removal of the f lower cabinet, the arithmetic Lach Fig 4-1 printed board can be checked from the back side. 2) Replacement of the CPU I] is possible. 3) If the key printed board is to be checked, the arithmetic printed board has to be bent in right angle after removing the screws (d) and (e). Inspection of the CPU I is possible if the buzzer is removed after removing the screw (c). 4) The key printed board can be dismounted from the upper cabinet when the 9 screws (f) and 2 screws (g) are removed. But, care must be exercised in dismounting the printed board, as key tops may come falling down one after another. e Replacement of the LSI 1) It will be much convenient if the LSI use soldering pencil (UKOG-0078CSZZ) is used for replacing the LSI. 2) Be sure to remove the key printed board from the upper cabinet first, if the LSI on the key printed board is to be removed. If the LSI was removed with the key printed board being fitted on the upper cabinet, there is a possibility of deforming the key rubber by the heat of the soldering pencil. 3) Be sure to cut the legs of IC, if IC was removed. @ Measuring current consumption Power source voltage. 4.72V Current consumption: After depress the ON key: Under 850uA After depress the OFF key: Under 12uA B Som ist Screw () Fig 4-2 17 5. CASSETTE OPERATION 5-1. Recording Recording method 80 steps Contents of program or reserve program Recording format of program or reserve program eee Eo] peal Fe ea i Be Fs ei eae 9 }1] 9 [1/3 Data memory recording format 1 = Check sun code (after every 8 steps or one data memory.) = 8 steps of program or reserve program = End code of recording. 4= This gap, composed of all “1”, is inserted at each step the recording exceeds 80 steps, during which teime the next 80 steps of data to be input is prepared in the input buffer. 5= All “1” is recorded for a period of about 6 seconds in order to avoid non-recordable area located at the top of the tape and is also used for the cueing of the recording head. = With this program or reserve program name is indicated. = File name = Data memory is indicated with this code. = Area for one data memory. Recording method Data “0” and “1” are identified by changing the frequency of the recording signal (F4”’). a eld oe Ld ee DATA “1” LIAL RLS LIA eee ke 1bit al 18 Ce ¢-€ Recording signal (F4’’) generation circuit Pease Seance 9— F4"— To CE121 cassette modulation circuit he) HA as $15 $15 OM — Pecorsing sina UU UUUU UU LLL Ue (F4") Signal waveform at the time of recording When recording signal “1” is to be recorded, S15 is turned low level and the signal F4 (clock pulse of = 4KHz) is output during that period. When recording signal “0” is to be recorded, $15 - is turned high level and the F4 output is inhibited during that period, at which duration the . reverse signal of HA (clock pulse of ~ 2KHz) is carried on the recording signal. Then, this signal is supplied to the MIC terminal of the tape recorder via the modulation circuit of the CE121. ring area 5-2. Reproduction te) Output signal from the EAR PHONE jack of the tape recorder is amplified and shaped in the Schmitt circuit, to be input to the CPU II through the Ki5 terminal of the CPU II. a ett ete KI5 cpull VW SS Sicnnenedpeaatint Sci Siocussaiat tes enlaaa Schmitt circuit Amplifier circuit & a 19 5-3. Remote control we The CE121 will control the REMOTE terminal in automatic manner against the record, playback and check commands. 0.047PF = 470Ko Kk | @ | operation and two circuits are contained in the same chip. “A” outputs a pulse which is dependable on the time constant of CR at the falling edge of the input signal, and “‘B” outputs a pulse which is dependable on the time constant of CR at the rising edge of the input signal. The relay operates ON and OFF according to the current flow to the coil, and it is activated when “A” is active and deactivated when “‘B”’ is active. p—VW 100 i 2 Ale Ain abe . 2SA733 NR-5711 —----4 MT 560KN 5 = Sa & : tT REMOTO O- VW Bin QA YW ' i (S14) aL TC4528BP 33.0. ; : r ' I r 0.0472 470Ko. 1 st i Vos O- 100 : oo L 8 14 I 4 i} S) 12),. ' © 3 z Alain QB ug + 2SA733 I - B 2 43 r | GND O— “pin TE 4W L------ eS i BL TesseeBP Ee | y | The TC 4528P is a mono-stable multivibrator which can perform trigger operation and reset | | egies of the cassette operation sé Termination of the cassette operation g Sut | fe me a a No x Activation of the relay — (cassette to start running) | 1 an a nes ) Deactivation of the-relay y + (cassette to stop running) 2 20 —— ™ 5-4. Testing the CE121 “® 1. Writing test data to PC-1211 First of all, test data must be entered to PC1211 for checking CE121. No. Read in Display Remarks 1 ~ > RESERVE | Make the RESERVE symbol indicated on the display after 2 | NEW NEW _ RESERVE 3 > RESERVE 4 |[SHFT] z Ze RESERVE 5 | p.#[SHFT]VAY A(204) | Z:P.#¥AV; A(204) RESERVE 6 Z: PRINT #VAY; A(204) RESERVE 7 x jee RESERVE 8 | 1#(SHFT]VAY 5A(76) | X: 1 #¥AV; A(204)_ RESERVE 9 | [ENTER X: INPUT #¥AY; A(204) RESERVE 10 eas RESERVE 11 | A(76) : A(204) RESERVE 12 : A(204) 13 > DEF 14 > RUN 15 SPC] =100 A(204)=100_ RUN 16 RUN 100 The test data have to be written into PC-1211 in the above manner. 2. Checking CE121 Assumes that the step 1 has already been executed. No. Read in Display Remarks — S| OF Connect the CE121 with the tape recorder. Connect the PC1211 with the CE121. 4 > RUN the Make sure that the symbol RUN is on the display. Otherwise, let the symbol RUN be displayed using key. (ail No. Read in Display Remarks ) a RUN Make sureof the tape recording location. 6 ee RUN Depress the [REC] and [PLAY] buttons. Then, the cassette will come to halt. fi PRINT #¥AY; A(204)_ RUN RUN The cassette starts to run generating sound. 9 P RUN The cassette comes to stop quitting sound generation. 10 2 RUN Depress the (PLAY) buiton. But, the cassette is still at halt. 11 o RUN Return the cassette tape until the beginning of the recording. 12 ||SHFT} X INPUT #¥AY; A(204)_RUN 13 | ENTER} RUN The cassette starts to run generating reproducing sound. 14 = RUN The cassette comes to stop quitting sound generation. 15 | |SHFT] [SPC A(204)_ RUN 16 |[ENTER RUN 100. 17 RUN 100. Push the [STOP] button. 18 19 Disconnect PC1211 from CE121. 20 Disconaect CE121 from the cassette recorder unit. I. It requires inspection if one of following conditions is recognized. 22 1. When the cassette starts to run at Step 6. 2. When the cassette fails to run or no sound is heard at Step 8. 3. When the cassette does not stop at Step 9. 4. When reproducing sound is not heard at Step 13. . Repeat the procedure in the following case. 1. When “5... ” is displayed at Step 13, repeat operation from Step 10. If the same indica- tion is still on the display, repeat the procedure from Step 5 after entering ““A(204)=100”. If the same indication is to remain on the display even after this, it requires detailed inspection. 2. When “100.” is not displayed at Step 16, repeat operation from Step 10. If the specific indication does not appear on the display, repeat the procedure from Step 5 after entering “A(204)=100”. If the specific indication is not to appear on the display even after this, it requires detailed inspection. NOTE: @ When next CE121 check is to be performed in executing secondary test, be sure to enter “A(204)=100”. @ Repeat once again from the “1. Writing test data to PC1211”, if the contents of PC1211 happens to change. ™ 5-5. About repairing of CE121 “~ Program 10 me Om O 1 ) CaPaRe Nr, oa ¥ DY; A (201) 0 tobe A SUSE 1 The CE121 is in proper operation if the following procedures are ended successfully. Read in Display Plug Tape recorder EAR PHOE MIC REM OTE PLAY REC STOP Remarks ( [OFF] ) Connect PC1211 with CE121. ee RUN Determine the location of the tape to be recorded. > RUN Make sure that the cassette tape does not run. CS. |SHIFT]|VA CS VAL RUN ENTER RUN The cassette tape starts to run and the recording sound is heard. The sound is inter- rupted and the cassette tape comes to halt with “>” indicated on the display. = RUN Return the tape to the beginning of the recording. Ea RUN CLO.? [SHFT|YA CLO.2¥A_ RUN 10 IENTER RUN O}O}O O}O/O O}O/]O O} O;O The display con- tents comes to dis- appear from the display and the cassette tape starts to run generating the reproducing sound. 11 Sound generation is interrupted and the cassette tape comes to halt with “>” indicated on the display. 12 RUN 13 23 [Cautions] 1. Check the machine with the check procedure provided separately, if the cassette tape happens to keep running at Step 3, the cassette tape fails to run at Step S, or the cassette tape fails to stop at Step 6. 2. Check the recording circuit of the CE121 if no recording sound is audible at Step 5. 3. In case no reproducing sound is audible at Step 10, proceed to playback another recorded tape to check if reproducing sound is audible with that tape. If reproducing sound is not audible with that tape, proceed to check the reproducing circuit of the CE121 as it may be not functioning properly. If the reproducing sound is audible with the second tape, check the recording circuit of the CE121 as no proper recording may not have been carried out. No. Read in Display Remarks 1 | RUN RUN_ RUN | No need of running the tape recorder. 2 — RUN | Recording sound is audible. 3 RUN | Recording sound goes out and “10.” is displayed on the display for a period of about 1 second. 4 west RUN Foster cottons) eee | | } L | | In In n In —* recording recording’ in display "ecording Indisplay recording in display #6 pin of TC4528 and ‘ #5 terminal of the relay { | Unies aul | | fl mia Activation of the relay (cassette tape to start running) in display #10 pin of TC4528 and #3 terminal of the relay > Imsec, min fl [ ] Deactivation of the relay (cassette tape to stop) Cassette operation ON/OFF control must be properly executed when the above signals are observed during the execution of program. 24 | | j [otal tg ta tetas Dols hehaiae 6. CHECK PROGF ifels 1 2 8 4 5 6 7 Zs 9 0 ll 2 13 14 5 8 a7 8 9 20 1 | + | 3) rs 6 al a z = | (a]| fa o M fa) 5 ]] = |e © | |i z + =a) (6 ]] | ml & | lw) [by Q)) 4 a | co é GI] N] [a Zz < I | {e4 | a 5) ‘es ea || Tl) =] w Falta a =|" a (3) Bl 2 | [fa . (2) < ee} | [ox Ie ie fai] | Jon lie oO |} 99 | oy SINE ay \ ie} Fo ba <e]] ml} @]1M]) o O}|n a} | ed z = a} o| ala * e a a eal ale a 3s a a| &| co] co 2 = ern “HECK PROGRAM DISPLAY SYMBOL Cassete ni fiz [18)14 [15 ]a6 [27 [18 ]20 [20] 21] 22 [2s [24 Sart] eG] RAD [crap] DEF [RUN] PRO|fep | -"™ PLAY| REC [STOP ttt tt tt ttt ttt Dake 4 4 4 4 4 4 4 ie) ° pope pt t—+—+—+4 aU A a eh lene fe) fe) PoE EE Et tt feos irs Ses mre ° 2 Kv Ko) | 0 ° fi Sas eee +++ +—++++ + KO) | Oo {e} ee S KO) | O re) tH eee re [e) ie) a 5 fe) 9 Pe ay Sri emm emia es wlamesyeet afte ie (o} ‘) ttt te Fea i rei A we S 2 4 4 Si a 4 4 4 4 ° ° et Set | 4 4 4 4 4 1 4 4 4 4 4 Mm 4 (Oo) © ° : La be (©) (e} (e) pt oS ee eee ee ES 2 2 pe ea, {ej {eo} bob bo t—}—+—+—} + Ee. Caer is ore © ie} en re re to) to) 2 S225 Gaeta ee ' —~- bop | 4 4 4 1 4 4 4 4 Seentairiel 4 4 p++ ‘ +++ , ies tear area ess: t—++—+4 foo soy Pi ly ' re A ; tt tt Salta aa? pel ple ae er eee roe ; iar Pa: eae sa t—}-—+—+—} ++ ++ eo et et + AR Serie 4 i t+ + +—+ — aan sl ner tt} t+ + + + ttt ttt tt , ees a ened i ttt + tt tt ee ee eee rial a= | pot +—+—}—+ 4+ ++ Pt SS SS ee { = poo ey ' $—+-+-+-+ +++ + f — ——— = ptt +++ aa = 4 a ttt ho { +++ itd po +—+—+++ ts : bhi dl tri SnD a 4 4 1 4 1 4 4 4 ' | ' a 25 7. CIRCUIT DIAGRAM PARTS 7-1. Operation Circuit Diagram é Ae F FE Gamk 32 R Se eke a . CECE+ E ce : + oe W1259CCZZ ) Kié 32Fla T LRWa Fea F3a 1 | Optiony1/O connect signal 7 | 1 3 iki kislh L 1 4 8 4 2 10 t xis} 4 2 7 | Option, 1/0 BUSY signal 1 GND TC4011UBP 47Ko ' ' = ae gen DS1588L1 1 1c 4019 P(2) 1 ] 1 DS 1588 L 1x2 -B8a—t]—7a ‘as Bubzer Lt} 1 fen 1+ @ : ; oo g Dt Tah l es 2 rr ie H L--45 Reka} BLES oe 2 AL ) Kis fH y= posi cit + ey) a | y e/L0v) P-DI+ t z a Loadii 100Ka| 10000 PF 1 1 ! signal SIfKilK K KK K F FVpp oe 1 H 1 ae gugg 42822 ac} 25 WV. 1 —se 45 6 + *Béa—+ 7 Vas ! 1 Yoo —-s3 J ' T I 1 ss xinpel 1gka 1 mh = fier 0 a He Catia LO sé test2 SS 1 i | Control 7s" RESET] .-) iH | ' se RAN Boa Les 1 —s9 DIO4 6 | sis-[}- si SC43178 piostee ! tot 1 su pIo2z ' ! \ S12 (Bottom View) DIOL} > i] eel «sis Bab! paral ey mal Qn Ve 4019 Pa) | : 1 5 laa 1 ' S15 ie $15 Béb Baa “ 1A4 1 VB ieee iat! Lag ad a7 Dvavws Habe } ' LY Bi + fe | REMOTO P 7" ! te | Signal 4 pBaa Le tas tes nat LL 1 ! 1 | 1 L \ : Loe J h 1 T I + | I ! = “Bla ; ! =n a F TH jaz i} ~ § 10Ka 1 Wd CMT 1 Recording | TC4011UBP itt 1 ‘ gna lf 1 1 1 1 1 + 1 1 i ' +Bla —T 3 WAR aT 5 ) }H— exp F ! 101 1 1 5oWV 1 1 100Ka S ! ' r | 1, 1 Voc if 1 1 4 1 | Saree SUB-PWB D Q F Vee HHHHHH Vas DH, DDD Voor Ss DF 4 ‘s Tr hese te FRee de i : 1234 a ce : g GL__PR 7 i HA S16b 26 RAM PARTS & SIGNALS POSITION Ps * TC 4069P 12 10 8 aaa Vu St BP, Dt ry DS 158811 “Tre 4019 P(2) se’ BP {As ! 3 se! = q Vorsp Vpisef TC4066P ! 1M | 1 ‘ ° 470K 220 Kn. | (RAM) AZ L_ TC55l4Px3 eh Tk Jes 1 1 150K —F4a! GND Thermistor GND Sa Be Lt) Veo" Nees —— ev [AT GNDF— \ JAG AS AS Si jA4 Sn HA Diol IA2 (1) pioz JAS DIOs IF2a’ D104 Voc RAW’ 100Ka = PWB : a F AAAAAAA ASSn RWb Xin TES 4S LT eas - ; . ) PR $16L UW9'L (Aaqsrm4ay 1) Ad00001 AMOL so amo yO e4 oly {aga veg v9q Ved 2d 4 IvIS GA WH 20d qd wy sv SH SECT A IIL tie wo Md Ady OL ‘aM d uonesedg “2-2 MATA WOLLOG +t zc 24 vig veg 4H 8 bY BeA vOld ACKRt Sid. YA “Bh vsg ULg OMYy WX 024 Vb4 WIG US 1. §Md AWy OL WWE ee Geet” 2 % \ ns fw M4AIA dOL veg vod Vg vzd €4 IIS GA WH 2010 Wd 1G 9! VEY Oly 139Fy ey SY €H 2H IH d UWS (Aaqsimaayt) DXOSL 7-3. Key Circuit Litt tt ul f a Ps | sal > — a os sa} > — s ) SC43157 Brat» aoe cPuU1 as 0 £7 1 o es 28 ev ee Mele ccc s_ Say pie SC 43125 $C 43125 sss DISPLAY CHIP(3) 3 - . DISPLAY CHIP) 1 sg2ee,8 4826.6. <823Ssf ese Ee ose i saz] ois acca oo gooo9 ono ooo 0 Ba og og Sop0, Q o § 86 88 2&8 ‘a Gooo, 9° “ooo “oood 8 8 oon ae, eG oo. a8 op 88 98 8 oe Wee on og yy = ooo”) 88 ooo” Boe” ao” odo oooga oO PERSE +e d ggoos oo8 8 aoooo 8a oogo0 ooood oooo0a fy voo00 8B EI 88000 tt | gonno goon oon g 9 op ono g 4o g 85 08 q a a Boo ©0000 O00 FF 8 3 Bie 8 oo @ ooo PARyet (ig ti te bisa we | at og oe a oe og 8 Bo 8 8°38 g 8 3 8 85 8 8 ao 8 8% 8 BOB Boooa 8 ooo” «8 «68 obo “bo 8 “o Boon 8 8 go00, oo0 oo900 9 ogo 99 9G Oo oO oooOg a5 oo OH GB 8B 88 88 8 | a8 Bo 8 ohoeed, Boegesdion gia a goon” “ooo, 49 8 8 Oo Gog oO ‘0 o 86: 8 8 5 Bo 888 oo @ oo Beeeedees 8 ool 8 oe bo od io 8 oa B °5 Sono” 8 “ooo” 8 8° GE 8 8 8 Goooo oo ooo9o a goo a6 oo 68 3 o oo a a 88 38 a 88 38 a8 88 ‘08 o "5 o 8 gooog o0 a" 83 oo oop aa = «Ba oo “o a Boood a a [geeeevesveurenseeeoses GESGeseGEsSeSOGOeGeGeee eo oe S10 SUB-PWB 1 ‘J10 (Vea) ee J12(GND) J13 (HA) J14.(S16 0UT) chee | (BSA) OL GMd-SNs DOUUUO ULES | 6090688 Ve Bdsm ‘ad Ae» “p-z 7-5. CE-121 Circuit Diagram DS1588L1x2 1Ma ye ’ Ww i 2SA738 RECORD input d.ooa7xRSOWY 1a 12 WV 4 a AAA | | 470 Ko ane (F4") + wska [YO 10Ko = 0.01uF Tw 2700 : 100Ka vit ——, rose 22Ka CMT LOAD output O- «<P <b WL (KIB) DS1588L1 TC4069P 50WV 0.047 4F 470 Ka 100Ka h—w Ss iz Ty t 2SA733 mb Sp aR Q a DS1588L1 awa | — 1 REMOTE Q- we ! T4528 | 24" ($14) 560Ka y ES 4 ! 7 DS1588L1 50WV H 0.0474F 470Ka ' h—w—_+ ' Veco O 100Ka © we 16WV 15] 14 = / bal 2SA733 104F a 8k; K | Bo OBZ a Gnd O- 17 T4528 a BP 13] 30 = AAX3 — | ' 1Moa ' 2SA738 I t i. 0.014F 25C458KS t 470KNS 25 wv singe i © 1 1 00K iN MA —VW 22Ka 100Ka Wt EAR 91 us 12'S 0.047 “E/50WVajen BONE “SP V ' Ww 2SC458KS : ! 1Mo ! H A 2 ¥ 2SA738 > 40 © REMOTE % 3 SA733 YAW 330 (901g) SLOWSY Meise 1 is hed 8. PC-1211 PARTS LIST & GUIDE NEW NO. PARTS CODE DESCRIPTION NEW K | RARK® [PRICE RANK NO. PART 1 | LX-BZ1102CCzz | Screw n1|clas TMANE! 2 | LX-BZ1032CCZZ | Screw oe Aes SPAKCE 3 | HDECA1705CCZZ Bottom cabinet NGF lanes leant TiNSE2 4 | PZETL1323CCZZ | Insulator sheet n/|c]flas LPLTPI 5 | PTPEH|O62CCZZ | Tap for chassis GC 1 AA | | TLABZI 6 | LCHSS1078CCZZ | Chassis Nac! sane | | RR-DZI 7 | GFTAAI231CCZZ | Lid N Do aos RR—-DZI 8 | XBPSD20P09000 | Screw Cal Ar RR—DZ! 9 | RALMB!006CGzZz | Buzzer BIAH RVR—ME 10 | LX-BZ1060CCZZ | Screw x9 Cc LAA VCEAAL 11 | XTPSD20P05000 | Screw CrP Age VCKYPL 12 | QONTMIO36CCZZ |All reset switch co ASB VHDDS| 13 | PCUSS1081CCZZ | Cushion a VHH154 14) QONW—1135CCZZ | Flexible wire (22pin) n | Blac VHiSC4 15 | QONCWI259CCOi | Connector (Qpin) N B AH VHiSC4 16 | PGUMS1 190CCZZ | Rubber connector G A F VHiSC4 17 | VVLLF8017JE—! | LCD Nol Bal BoA VHiTC4 18 | PTPEH!033CCZZ | Tape for LCD ae | ASA VHiTC4 | 19 | LANGK1290CCZZ | Angle for LCD c [aD VHiTC4 20 | PFiLW1230CCZZ | Filter c [AH VHiTC4 21 | HDECAI527CCZZ | Display mask Cc A Cc | | VHiTcE 22 | PFiLWI228CCZZ | Display filter Cc. hee VRC—MT 23 | PGUMM1I254CCZZ | Key rubber B AK VRD-S7 24 | MSPRC1O98CCZZ | Earth spring Ch IgA aA VRD-S1 25 | JKNBZ1515CCO4 | Key top (18key) n | coc lar VRD-ST 26 | UKNBZ1515CCOS5 |Keytop (17key) Ne Lle> eAeee VRD-ST | 27 | UKNBZ1516CCO2 |Keytop (SHIFT) X20pcs Nn] clAE VRD-ST | 28 | UKNBZ1566CCOI |Keytop (ENTER) X1Opes N lc? Faia VRD—ST 29 | UKNBZ1492CCO2 |Keytop (Numeral) N |G | AVE | | vRD—s1 30 | UKNBZI567CCO!I |Keytop (CL) X20pcs n/|clAaAe VS2SC4 31 | QTANZ1287CCZZ [Battery terminal (+, —) c laB VS2SJ4 32 | QTANZI292CCZZ | Battery terminal (+) c | AB 7 lee -sz 33 | QTANZ1250CCZZ | Battery terminal (—) Cc A B RCRSP| 34 | XUSSD20P04000 | Screw co lA Al VCKYPL 35 | LANGT1336CCZZ | Angle for bottom cabinet n | colflaB VCTYPL 36 | CCABB2299CCO2 |Top cabinet n|olaAs | Re=sz1 37 | GFTAA1232CCZzZ | Lid for connector ni bdlaAasB | vRD=s) 38 | QONW—1137CCZZ | Flexible wire N B fe 8; VCKYPL | 39 QTANZ1293CCZZ | Battery terminal (+, —) N ie) AB | | UBAGZI211CCzz | Hard case Nn | Dflam DK iT—! SPAKA5108CGZZ | Packing cushion Nl Dy Abe TiNSE3137CCZZ | Instruction book (U.S.A) N | D Ana PO—1211-) Po—1211-2 32 NO. PARTS CODE DESCRIPTION NEW MARK PARTS RANK ] PRICE Rana TMANE 10!10CCZZ Program library D > SPAKCS5O 1 2CCZZ Packing case TiNSE2826CC2ZZ Basic text LPLTP!I1O70CCZZ Tenplate Poa ae 4 TLABZ1I295CCZZ Name lavel RR—DZ1!1O006CCZZ Resistor 1/8W 143Kohm +2% RR—DZ!1007CCZZ Resistor 1/8W 12.7Kohm +2% RR—DZ 1! 008CCZZ Resistor 1/8W 21.0Kohm +2% RVR—MBS5 | 0OQCZZ Valiable resistor 250Kohm VCEAAU!IAWIO07Q Capacitor 14F 50V VCKYPUIHB221K Capacitor 220PF 50V VHDDS1588Li—! Diode DS1588L1 VHH1I54KD—-5/—1 Thermistor 150Kohm VHiSC43125/-I L.S.i (Display chip) VHi-S€43157/—| ERS ina (CRUZ). VHiSC43178/-1 LE'Ssi-(CPU=TI) VHiTC401 1UBPI (2G) VHiTC4019P/-1 pes; VHi TC4066P/—1 ad. VHi TC4069P/—| on VHiTC5514P/-| L.S.i (RAM) VRC—MT 2BG165J Resistor 1/8W 1.6Mohm +5% VRD—-ST2BYIOIJ Resistor 1/8W 1000hm +5% VRD-ST 2BY223J Resistor 1/8W 22Kohm +5% VRD-ST2BY 103J Resistor 1/8W 10Kohm +5% VRD—-ST2BY 104J Resistor 1/8W 100Kohm +5% VRD—-ST2BY105J Resistor 1/8W 1Mohm +5% VRD—ST2BY472J Resistor 1/8W 4.7Kohm +5% VRD—-ST2BY474J Resistor 1/8W 470Kohm +5% VS2SC458KS/-—| Transistor 2SC458KS VS2SJ40—///-| MOS FET 2SJ40 RC—SZ1005CCZZ Capacitor 0.1nF 10V RCRSP1024CCZZ Crystal VCKYPUIHBIOIK Capacitor 100PF 50V VCTYPUIEX103M Capacitor 10000PF 25V RC—SZ1007CCZZ Capacitor 1uF 10V VRD—-ST2BY224J Resistor 1/8W 220Kohm +5% VCKYPU!HBIO2K Capacitor 1000PF 50V OQ/O!lOlA/O/O/Ol/O/DIDlOD/QD/D/O/O/O O/Dl/WBliD/D/D\/D/WM/ Di Di D/O/O;/O),0/0/0O/0/0;0/0 PPL Sl| S| S/S S/S [S| S| S| Sele S/S S| SPl/Ol S| S/S |S|/O/O/ S| YF|/ S| S| S| E/ S| S| >| Sr/ >| >| yo Bef BB a | SS | | | a | | 2 i bo ce De ela DKiT—!1001CCZZ SUB-PWB Kit PC—1211—22] 33 SS a. 9. CE-121 PARTS LIST & GUIDE use z =) PARTS CODE DESCRIPTION NEW MARK PARTS RANK PRICE. RANK GCABA2315CCZZ Bottom cabinet is) A LX—BZ1038CCZZ Screw GLEGGIO!2CCZZ Rubber foot ue GFTABI235CCZZ Battery lid XTBSD20PO6000 Screw QPLGJ1008CCZZ Plug *f QCNCMI260CCO! Connector (9pin) @elN| ola} e/wlr|— XTBSD20PO5000 Screw o LANGT 1 334CCZZ Angle °o QTANZ1266CC2ZZ Battery terminal QTANZ1072CC2ZZ Battery terminal i) HDECA!684CC2ZZ Dec. panel A ve w HDECA!685CC2ZZ Dec. panel B = GCABB2316CC2ZZ Top cabinet ve SPAKA5097CCZZ Packing case SPAKCS5111CCZZ Packing case SPAKAS109CCZZ Packing cushion Yar OF oe ae ae VCEAAU!ICWIO6Q Capacitor 10“F 16V | VCQYKUIHM472K Capacitor 0.0047uF 50V VCQYKU 1 HM473K Capacitor 0.047uF 50V ve VCTYPUIEX1O3M Capacitor 0.01uF 25V VCTYPUINXIO4M Capacitor 0.1“F 12V VHDDS!1588Li-—! Diode DS1588L1 VHiNR5711//-1 Relay NR5711 VHi TC4069P/—| 1. C. TC4069P VHiTC4528BP—| |.C. TC4528BP ue VRD—ST2BY 103J Resistor 1/8W 10Kohm +5% VRD—-ST2BY 104J Resistor 1/8W 100Kohm +5% wu @ VRD—-ST2BY 105J Resistor 1/8W 1Mohm +5% VRD—-ST2BY183J Resistor 1/8W 18Kohm +5% VRD—-ST2BY223J Resistor 1/8W 22Kohm +5% VRD-ST2BY271J Resistor 1/8W 2700hm +5% VRD—-ST2BY474J Resistor 1/8W 470Kohm +5% VRD—-ST2BY564J Resistor 1/8W 560Kohm +5% VRD—-ST2EY330J Resistor 1/4W 33ohm +5% VS2SA733—/7—| Transistor 2SA733 VS2SC458KS/-| Transistor 2SC458KS DID OD/O/O/O/O/O/O/O/O/D/MD| DI Dl/O/B/O/O/OJ/O/GD/V/V/ V/V O/O/O;/O/D/o)/O;0;0O;0 PIPL P| S/S LSS S/S SS S/S S/S S| S| S| S/S [S| S/ S/S Sl Sl Sl P| SiS Slo yr S| >> loans} | PL S| S/S |S Sl S| yrl| Vi T) SDD O|/D/D\/D|M/OlO|O/D/O|/ P| P/O/ S| O\o;/ plo; p/P] oO wu © uv @ 34 2 13 ” @ " @ 35 SHARP CORPORATION Industrial Instruments Grou