Datasheet · 1974
Mostek Integrated Circuit Guide (1974)
Mostek's 1974 catalogue of MOS integrated circuits, including its MK50xx calculator chips, descendants of the MK6010 made for Busicom.
Datasheet · 1974
Mostek's 1974 catalogue of MOS integrated circuits, including its MK50xx calculator chips, descendants of the MK6010 made for Busicom.
CONTENTS Com pa ny lnformaf Functional/Nume Standard p ~on rical Index . roducts ReadRegisters. Shift Onl M ........ .... : Rand y emories . . ........ 5 . om Acee ss Memo·.. . . . . . · · · · ·. 17!. M1croprocessors ries · · · · · · · · . 45 c1a Spe · I Product ··· ............... ·7 Con s. · ·... · 7 p sumer Products · · · · · · · · · · · .. 81 roducts to b e Announced ......... . · · · · · . 93 ......... 13 "'0~;'" e.. \(. ~ \( "10qbf' ~ \l'l oM- THE COMPANY Since formation in 1969, MOSTEK has grown dramatically in product development, geographic scope and technological capability. Sales have advanced from $1 million in 1970 to an excess of $40 million in 1973. Geographic expansion has been just as rapid. Sales representation is virtually worldwide and manufacturing plants are now operating in Carrollton, Texas; Worcester, Massachusetts; and Penang, Malaysia. A complete MOSTEK circuit design facility is located in Stuttgart, West Germany. Engineering strengths have been particularly important to this growth pattern. The superior engineering design capabilities at MOSTEK have regularly increased the state-of-the-art of the entire industry. MOSTEK "firsts" include ... Y' First production of low threshold PMOS by ion- implantation FACILITIES "1" First single-chip calculator MOSTEK's continued growth is evidenced by the Y' First production of MOS/LSI having both recent addition of 40,000 square feet to the Dallas enhancement and depletion transistors on the facility and the purchase of a 273,000 square toot plant same chip in Lowell, Massachusetts. This will bring MOSTEK's total facilities to approximately 449,000 square feet. Y' First TIL compatible 1024-bit RAM Dallas area MOSTEK 136,000 Y' First single 5-volt supply PMOS Worcester 8,000 Y' First MOS/LSI circuit combining N-channel, GMBH Stuttgart, West Germany 5,000 silicon-gate and ion-implanted depletion Penang, Malaysia 27,000 load processes Lowell, Massachusetts 273,000 Y' First 4096-bit Random Access Memory 449,000 MANUFACTURING PROCESSING TECHNOLOGY OPERATIONS PLANNING, PURCHASING AND With the incorporation in 1969 of ion-implantation into INVENTORY CONTROL To organize MOSTEK's standard PMOS processing, MOSTEK pioneered a explosive product output, a complex system of technique enabling the us.e of both depletion and computerized information has been developed for enhancement transistors on the same device. This planning and control purposes. These systems include a technique gave improved performance and allowed long-range Iinear programming model for forecasting process optimization for lowering device costs. MOSTEK manufacturing capacity constraints in relation to has recently expanded its production processing anticipated sales; a complex system of scheduling capabilities to offer ion-implanted N-channel MOS and production and inventory control reports; and product CMOS devices having improved electrical character- yield and costing reports. This information is routed to istics over non-implanted versions. company locations in Worcester, Massachusetts; MOSTEK currently operates two separate wafer Penang, Malaysia; and three subcontract offshore fabrication facilities devoted to high volume production assembly facilities as well as all sales offices. of MOS devices. The original facility located in Worcester, Massachusetts has approximately 8,000 MANUFACTURING ENGINEERING square feet primarily utilized for processing two-inch The two major operations within MOSTEK and three-inch silicon slices. The second facility, manufacturing engineering are test equipment located at MOSTEK headquarters in Carrollton, has engineering and product engineering. Both efforts begin approximately 28,000 square feet primarily utilized for early in the product design state and continue processing of three-inch slices. An additional 63,000 throughout the product Iife. At MOSTEK, new product square feet is being prepared for occupancy in 1975 in designs are quickly evaluated using a sophisticated Lowell, Massachusetts as a third process area. computer system including Fairchild 500 and 600 units At MOSTEK's Worcester facility, more than one million and an STS Venture II. In addition, MOSTEK developed wafer implants have been performed, making this facility unique parametric measuring and timing units to the world's largest supplier of ion-implanted MOS wafers. complement the computer evaluation network. All photomask shipments are sampled by Quality In order to offer the most thorough testing of MOS/LSI Control for geometry control, etch accuracy and physical circuits, MOSTEK designed and built the "Bluebird" damage. Each set of newly shipped masks is checked series of IC testers. MOSTEK now operates eleven of for proper registration. MOSTEK has found that well- these sophisticated systems, testing 100% of all defined and tightly controlled mask specifications have units shipped. a high impact on circuit yield. 2 Each assembly piece part shipment (packages, gold Uses include: wire, preforms, lids, etc.) is checked for physical (1) Real time process control for the wafer fabrication dimensions, plating thickness, bondability, tensile areas strength, wetabi Iity and hermetic seal before release to (2) Design and prototype analysis of new products the manufacturing department. (3) Wafer processing research and development WORKMANSHIP QUALITY CONTROL (4) Wafer/lot analysis MOSTEK's wafer processing is performed in class (5) Failure analysis 100 environments having humidity and temperature QUALITY ASSURANCE control. These operations are performed by highly skilled MOSTEK places unusual emphasis on product quality manufacturing personnel and are continuously evidenced by the ratio of manufacturing to QC personnel monitored by quality control operators to insure con- of 10:1. The common industry ratio is 20-30:1. And at formance to all specifications. MOSTEK 30% of the QC staff are high technology Each die receives a manufacturing 100% visual professionals. inspection and a QC Lot Acceptance prior to its submission to the Assembly process. The assembled unit is then subjected to another manufacturing 100% INCOMING MATERIAL QUALITY CONTROL inspection and a QC Lot Acceptance immediately prior Polished si Iicon wafers are purchased under to the sealing (encapsulation) process. MOS is a surface specifications including wafer thickness, resistivity, oriented technology and most defects can be detected diameter, crystal orientation and dislocation distribution. by well-trained assembly and QC operators. Each shipment is sampled by Quality Control prior to Each completed device receives an electrical test by release to production. the manufacturing department; additionally all material Electronic grade chemicals are used exclusively. is submitted to sample electrical testing by Quality Proprietary solutions, such as oxide and metal etch Assurance personnel. All lots rejected are solutions, are checked with respect to etch rate and rescreened 100%. discoloration prior to release to the manufacturing line. The MOSTEK Qua Iity Department uses one of the most powerful analytical tools available today. This instrument, the Scanning Electron Microscope (SEM), allows an order of magnitude improvement in resolving power over standard light microscope equipment. 3 Functional Numerical Index Shift Registers Consumer MK 1002P Dual 128-Bit Static ............ 6 MK 5020 Series MOS Calculator Series .......... 94 MK 1002L Dual 128-Bit Static ............ 10 MK 5020AN 8-Dig it, Six-Function Calculator MK 1OO?P Quad 80- Bit Dynamic ......... 12 v) .............. (+, -, x, ...,._, %, 96 Read Only Memories MK 5021 CN 10-Digit, Six-Function Calculator MK 2000P Series 2240-Bit Column-Out Character v) .............. (+, -, x, ...,._, %, 98 Generator ..................... 18 MK 5022AN 8-Digit, Five-Function with Memory MK 2300P Series 2240- Bit Column-Out Character v) ............. (+, -, x, ...,._, %, 1oo Generator ..................... 23 MK 50203N 8-Digit, Six-Function Calculator MK2302P ASCII Encoded Generator ...... 23 v) ............. (+, -, x, ...,._, %, 102 MK 2400P Series 2560-Bit ROM ................. 29 MK 50280N Series 8-Digit Calculator Series ....... 105 MK 2408P 2560-Bit Row-Out Character MK 50281 N 8-Digit, Five-Function with Memory Generator ..................... 34 (+,-, X,-7-, %,) ............... 107 MK 2500P Series 4096-Bit ROM ................. 36 MK50282N 8-Digit, Five-Function Calculator MK2503P ASC ll~EBCDIC Code (+,-, X,-7-, %,) ............... 108 Converter ..................... 40 MK 50283N 8-Digit, Six-Function Calculator MK 2600P Series 4096 Bit ROM ................. 36 v) ............. (+, -, x, ...,._, %, 109 MK 2601 P ASCII ~EBCDIC Code MK 50040F CMOS Oscillator/Divider ....... 111 Converter ..................... 40 MK 50250N Series 4- or 6-Digit Alarm Clock ....... 114 MK28000P 16384-Bit ROM ................ 41 MK 50265N Clock Radio .................. 118 Random Access Memories MK 5017P Series MOS Clock Circuit ............ 122 MK 4006P-6 1024x1 Dynamic RAM .......... 46 MK 5017 AAP Alarm Clock .................. 123 MK 4008P-6 1024x1 Dynamic RAM .......... 46 MK5017ANP Clock Radio Clock ............ 125 MK 4008P-9 1024x1 Dynamic RAM .......... 52 MK 5017BBP Calendar Clock ............... 127 MK 4008P-9 Application Notes .............. 54 MK 50240P Series Top Octave Tone Generator .... 131 MK 4007P 256x1 Static RAM .............. 58 Products to be Announced MK4007P-4 256x1 Static RAM .............. 62 MK 50010 4-Digit, 12-Hour Liquid MK4096P 4096-Bit RAM .................. 63 Crystal Watch ................ 136 MK4102P 1024x1 Bit RAM ................ 70 MK 50011 4-Digit, 24-Hour Liquid MK 4102P-1 1024x1 Bit RAM ................ 70 Crystal Watch ................ 136 MK 4102P-6 1024x1 Bit RAM ................ 73 MK50012 3112Digit,12-HourLiquid Microprocessors Crystal Watch ................ 136 MK5065P 8-Bit Microprocessor ........... 78 MK 50100 ROM 12-Digit Calculator Set ......... 137 Special Products MK 50075 RALU 12-Digit Calculator Set. ........ 137 MK5002P 4-Digit Counter Latch Decoder ... 82 MK 5030 CMOS 12-Hour LED Watch ..... 138 MK5005P 4-Digit Counter Latch Decoder ... 82 MK 5031 CMOS 24-Hour LED Watch ..... 138 MK5007P 4-Digit Counter Latch Decoder ... 82 MK4096-6P 4096-Bit RAM-200 ns MK5009P Counter Time Base ............. 87 Access Time ................. 139 MK50070N CMOS Oscillator and Divider .... 91 MK5085 Telephone Tone Generator ..... 139 MK 50395 6-Digit Up-Down Counter ...... 140 4 5 MK 1002 P MK 1002 N DUAL 128-BIT MOS Static Shift Register moSTEK FEATURES: D Ion-implanted for full TTL/DTL compatibility - no interface circuitry required D Single-phase, TTL/DTL compatible clocks D Dual 128-bit static shift registers - 256 bits total D Dual sections have independent clocks D Recirculate logic built in D DC to 1 MHz clock rates D Low power dissipation -130 mW D 16-pin dual-in-line package FUNCTIONAL DIAGRAM APPLICATIONS D Delay lines D Buffer data storage D Recycling test data sequencer D Digital filtering DESCRIPTION The MK 1002 is a P-channel with internal pull-up resistors MOS static shift register utiliz- to V55 (+5V) for use when driv- ing low threshold-voltage proc- ing from TTL. These resistors essing and ion-implantation to can be disabled when driving achieve full TTL/DTL compat- from circuitry with larger out- ibility. Each of the two inde- put-voltage swings, such as pendent 128 bit sections has DTL. Enabling of pull-up re- a built-in clock generator to sistors is accomplished by OPERATING NOTES generate three internal clock connecting the appropriate phases from a single-phase terminal to V66 ; disabling by TTL-level external input. In connecting to V55 . The Recir- addition, each section has culate inputs are not provided DATA input logic for loading or re- with pull-up resistors since Re R;n D;n ENTERED ci rcul ati ng data within the they are generally driven from 1 x 1 1 register. (See Functional Dia- MOS. 1 x 0 0 gram.) The positive-logic Boolean expression for this Shifting data into the register 0 1 x 1 is accomplished while the 0 0 x action is: 0 Clock input is low. Output data appears following the positive- "1" = V55 = +5V OUT (delayed 128 bits) = (Re) (D;n) + (Re) (R;n) going Clock edge. Data in each "O" = V00 = Grd register can be held indefi- X = No Effect The Data, Recirculate Control, nitely by maintaining the Clock Output Logic: See Description. and Clock inputs are provided input high. 6 ABSOLUTE MAXIMUM RATINGS Supply Voltage, V00 • • . • • • · · . V55 - 10.0 V Supply Voltage, V66 • . . • • • . V55 - 20.0 V Voltage at any Input or Output . . . V55 + 0.3 V to V55 - 10.0 V Operating Free-air Temperature Range . . . 0°C to + 75°C Storage Temperature Range . . . . . . . . -55°C to + 150°C RECOMMENDED OPERATING CONDITIONS PARAMETER MIN TYP MAX UNITS COMMENTS f5 Vss Supply Voltage 4.75 5.0 5.25 v V00 = 0 V i!; VGG Supply VoltagePJ -12.6 -12.0 -11.4 v a. Input Voltage, Logic 012 1 v = = a. !5 VIL VIH Input Voltage, Logic 1 Vss-1 0 5.0 Vss-4 Vss v f Clock Repetition Rate DC 1 MHz t91p Clock Pulse Width 0.35 10 p.S t¢d Clock Pulse Delay 0.4 p.S See "Siz t91, Clock Pulse Risetime .010 0.2 p.S Timing ...= j:: t911 tdld Clock Pulse Falltime Data Leadtime 50 .010 0.2 p.S Diagram a. ns !5 tdlg Data Lagtime 200 ns trld Recirculate Control Leadtime 100 ns t119 Recirculate Control Lagtime 300 ns ELECTRICAL CHARACTERISTICS (V55 =+5 ±0.25V, V66 = -12 ±0.6V, V00 = OV, TA= 0°C to +75°C, using test circuit shown, unless otherwise noted.) PARAMETER MIN TYP 3 MAX UNITS CONDITIONS lss Power Supply Current, V55 14 25 mA f¢ = 1 MHz 15 Inputs & Outputs open ~ a. IGG Power Supply Current, V66 5 10 mA Ci Input Capacitance, any Input 3 10 pF V1 = V55, f = 1 MHz TA= 25°C Ill Input Current, Logic 0: Resistors Disabled 2 -40 µA V1 = V55 -5V = = a. !5 Resistors Enabledz -0.3 -1.6 mA V1 = +0.4V ---I llH Input Current, Logic 1, Any Input 40 µA VRA, VR 8, VR¢ = V55 V, = Vss llR(on) Input Current at Recirculate lnputsz -40 µA VRA, VRB, VA¢ = vGG V1 = V55 - 5V = ...= a. VoL Output Voltage, Logic O (3) 0.4 v IL= -1.6 mA = 0 VoH Output Voltage, Logic 1 (3) Vss - 1 v IL= +100 µA toLH Output Delay, Low to High (3) 450 ns See Timing u :ii ail 'toHL Output Delay, High to Low (3) 450 ns Diagram and cC z u ,... :c Test IQ tvoR Output Voltage Rise Time (3) 100 150 ns Circuit tvoF Output Voltage Fall Time (3) 100 150 ns NOTES: 1. Other supply voltages are permissible providing that supply and input voltages are adjusted to maintain the same potential relative to Vss, e.g., Vss = OV, Voo = -5 ± 0.25V, VGG = -17 ± 0.85V. 2. MOS pull-up resistors to + 5V are provided internally. These MOS resistors are enabled by connecting VRA, VRB and VR¢ to VGG, and disabled by connect-, ing VRA, VRa and VR¢ to Vss. Pull-up resistors not provided at recirculate inputs. 3. At TA= 25°C. 7 TIMING CLOCK Din Re vss 90%- - - - - - - - - - - 10%---------- - toLH LOGIC "1" OUTPUT 50% - - - - - - - - - - and Rin LOGIC "O" - - - - " "1 . e- ,, ,, c e- "'c:·- (; o 0 E ~ o«> w cu·- ~~ -=-- g:c c .=:= - i5 a:: :g £ o: c cnE cu:_ e -·e~ 'S .?:- :,-0"'ca: The timing diagram applies to either section of the dual shift register. The test conditions for these wave- forms are illustrated below. A logic "1" is defined as +s V and a logic "O" is defined as OV As long as Ac is at a "1 '', Rin is disabled and Din is enabled. The data that is present at Din while the clock is at "O" is shifted in and will be stored as the clock goes to a "1" This data must have been present id1d time prior to the clock "1" edge. The data must also remain in that same state for td1 9 time after that edge. These times are necessary to insure proper data storage in the first register-cell. On the clock "1" edge, data is shifted through the register causing bit 127 to be shifted to position 128. This cell's output is buffered and appears at the output in the same logic polarity that appeared at the input 128 clocks prior. This data appears within tpd time of the clock "1" edge. Rin may be hardwired to the data output. When Re is at a "O", Hn is enabled and Din is disabled. Therefore, the output data will appear at the input of the first cell. When Rin is tied to the data output, the output delay will insure td1 9 and td1d times. Re "O" time must lead the clock "1" edge by tr1d time and must lag that edge by t,1 9 time to insure proper data storage when recirculate storage is desired. TEST CIRCUIT GRD Vss r-- - -- --- Vss VDD VGG 2.9K 1% R1N OUT word I pattern D1N MKI002P ..J.. VR Re CLK circuit I - 20pF -12v VDD under test _ _ _ _ _J I 0 :* Voo clock pulse Inverters are 74 series TTL * Includes scope and test jig capacitance 8 APPLICATIONS This shows the MK 1002 P connected to operate as a single, 256-bit, static shift register Pull-up Recirculate 128-bit STATIC resistors are enabled at Control SHIFT REGISTER TTL driven inputs and dis- A abled at MOS or DTL driven inputs. Any simi- lar TTL/DTL device may be used in place of the Dato Input inverters shown 128-bit STATIC Data SHIFT REGISTER Output Clock Vss Input Inverters ore 74- series TTL II 10 • 5V GRD -12v -12v PACKAGE 16-pin plastic dual-in-line PACKAGE 16-pin ceramic dual-in-line PIN CONNECTIONS TOP VIEW 16 PIN CDIP VRs 16 VRA Dins 2 15 Din A Rina 3 14 RinA Res 4 13 Re A Outs 5 12 Out A Voo 6 II VGG Vss 7 10 VR¢ Clocks 8 9 ClockA TYPICAL PERFORMANCE 400 140 380 Vss= 5.0V 135 .,, ,..... Voo= O.OV 5 360 130 125 VGG=-12.0V '.§ 340 I.LI 0 ~ 120 I- 320 E :::> Vss = 5 .OV 0 a... 115 :=:::> 300 II 0 0 Voo = OV 280 105 260 VGG = -12.0V 100 95 0-·~1~--~-----..---..~-.-~~~-----. TA (oC) 0 10 20 30 40 50 60 70 80 TA (°C) 0 10 20 30 40 50 60 70 80 9 MK 1002 L DUAL 128 BIT MOS Static Shift Register moSTEK DESCRIPTION The MK 1002 is a P-channel MOS static shift register Shifting data into the register is accomplished while utilizing ion implant, low-threshold voltage processing the clock input is low. Output data appears following to achieve full TTL/DTL compatibility. Each of the two the positive-going clock edge. Data in each register can independent 128-bit sections has a built-in clock gen- be held indefinitely by maintaining the clock input high. erator to generate three internal clock phases from a single-phase TTL level external input. FUNCTIONAL DIAGRAM PIN CONNECTIONS v.. N.C. SHIFT REGISTER A DIN a SHIFT REGISTER OUT 8 B Vss ~s Voo TOP VIEW 3 7 4 N. C. = no connection vss vss voo VGG CLOCK TIMING PACKAGE !¢r CLOCK 2 128 2 tdlg Din LOGIC"1" OUTPUT 50% - - - - - - - - - - LOGIC "O" _ _ _ _ __,, BOTTOM 034 VtEW 028-Y;~~ ........_ ~ 026 .,,., .,, e- NOTES 0 ~ o"' - ,.. A ALL DIMENSIONS