Datasheet · c. 1969
Data sheets for Hitachi's HD3100-series PMOS chips used in the Friden EC-1114/1115, Casio 121-B and other Japanese Nixie calculators: shift registers, gates, flip-flops and the serial adder.
a y ! _ per} HITACHI] MOS INTEGRATED CIRCUIT HD3101 4 DESCRIPTIONS The HITACHI MOS (Metal Oxide Semiconductor) Integrated Circuit HD3101 is a dual 8 bits quasi-static shift register constructed on a silicon monolithic chip utilizing P-channel enhancement mode MOS transistors, belongs to HITACHI MOS IC HD3100 series especially designed for applications in an electronic desk calculator, And HD3101 is available in a dual in line type ceramic package (14 leads). The HD3101 functiuns as an 8 or 16 bits shift register, an 8 or 16 bits ring counter, and otirs. The features of HD3101 are as follows: ° Integrated zener clamp protects gates. ® Large: noise margin ssiccweiweiees a4. 04 Gy ae ve NM, = 1.0V, NMy = 2.0V ° Wide operating frequency range .......... DC to 100 kHz. ° Wide operating temperacure range ........ -20°C to +75°C. fe _ ye seems ot ae DIMENSLONAL OUTLINE PIN CONNECTLON SCHEMATIC DIAGRAM poe | : o ‘oo ME 4 Ht Up Yop q 33 aes c 84 OUT 2 ¢ a a | W4 cal | Y it ad 4H Lor - qi ALL. >b,2 © oe GND <7.62> a cpl ™ | cp2 ot ale 0.20~0 38 ontS° | unit : mm (top view) ABSOLUTE MAXIMUM RATINGS at 25°C ambient temperature ee ITEMS ~ a |symporg RATINGS UNITS ‘asi Mn sia [en Sl Be | Storage Temperature Tstg i -55 ~ 150 =€ (to be continued) “x, —200-— ELECTRICAL CHARACTERISTICS (-Vgg=24Vt10%, _~Vpp=lavt10oz, Ta=25°C) a eee 4 SYMBOLS [MIN | UNITS __ CONDITIONS Input | 0" Level | “Vin 5 9.05 |” . Xb meaggre _ Voltage {1 or “nm | | ; WM ee “Output [.0" Level | -Voy | 10 | V_| Ta=75°C,cpw=1. Ops, = 00 Voltage | 5 Level | -VoH. : ¥ fop=5kHz | Rp=50KQ | Clock "0" Level -Vep 19 ve Voltage ee Level, | eed Vv |. Ta=75°C, cpw=lys Min. Clock, Clock | fepimtn| 2 Hz{ cpwel. Ons , £cp2=5idH =75°C Frequency | Clock 2| fep2min| _—| kHz | cpw=1. Ope, ee ee Clock Pulse Width i _cpw p1.0 ps, | See Fi __ — | Clock Capacitance _ | Ccp | ; pF “f=1MHz, “Vep=0V ee | Input Resistance — Rin ' 10 MR | -Vin=26.49 ~~ on Input Capacitance — - | Cin i ~ 0 ‘pF -fe1MHz, Vin=O0V | | Outpat Capacitance al Cout | .0| pF | f=1MHz, VoutsWo Power Dissipation Pd 00; mW [ -Voc=-Vep=24V, Vp ls Propagation , q falling | tPHL 5! ps | -Vine0~12.6V,fcp=l0kHz, Delay Time tf. rising tpry | — | sf 2-0} ms | CL=20pF,Ri=%, See Fig.1-& 2 | Clock Pulse Delay cpd' | 1.0] | us | See ‘Fig. 2. NOTE : Cpl is controllable when cp2 : is given at from 5kHz to 100kMe repetition rate. Cp2 is uncontrollable and always must be given .at from 5kHz to 1OOkHz repetition rate. OUTPUT WAVE FORMS "% ‘¢ LI Pulse H Generato# Data Input nated. stu de [| cpl i 4 7 cp2 SRE senceecectcinapers , OUT ;- ~ -- pee i res : amen ee cf includes as eury ae = ay ay capacitance a probe and wittiigh. Fig. 1. Output Voltage es Propagation Delay Testing Circuit cp2 Output a aseaeeereennalin Genie ov =Ky VCPH jepa'2 be -18V —- cpd'l VepL oe F =4v-—Vcpy es Via -7V fp ey seem ORE, —— lens Rapper eer ea valu oV CPHL --— ' iin ——— -7V pecan OE, tPLH Fig. 2. Clock & Output Wave Forms | {to be continued) _! Amt TYPICAL TIMING CHART sr Wy af cpl controlled || f i Hoya foie y Uo | tit kh & # l U ! | . u TE _ | - | ners | L ‘ Sad aimmiiatel — SE 6) G —- t | . AMV i tw fep | | {- AMV --- Astable Multi Vibrator MMV --- Mono-stable Multi Vibrator BMV --- Bistable Multi Vibrator Fig. 4. os = ! rh pee aa ——— E fo cpl E --~ Emitter Follower E —o cp2 é E }+———o Data Pulse Clock Pulse Generator Block Diagram 2n% HITACHI MOS INTEGRATED CIRCUIT HD3103 DESCRIPTIONS The HITACHT MOS ( Metal Qxide Semiconductor ) Integrated Circuit HD3103 js a five MOS FETs constructed on a silicon monolithic chip utilizing P-channel enhancement mode MOS transistors, telongsto HITACHI MOS It HD3100 series especially designed for applications in an electronic desk calculator, And EE3103 is available in a dual in line type ceram.c package (16 leads). The HD3103 functions as a ‘ransfer gate, an inverter, exclucive OR circuits, and others. Tne features of HD3103 are as follows : ‘ Integrated zener clamp protects gates. Large nOiS€ MATGiIN .....sseseceeecceecssccsoeeoeNMy, = 10.0V, NMH = 1,5V Wide operating temperature Prange seeeeeeesseeens -20°C to +75°C PIMENSIONAL OLTLINE | PIN CONNECTION SCHEMATIC DIAGRAM 5.06maK. to cal 3 — a) h A % Si {1 | 1 § “fq 6b! a, [21H 415] c ¢ Gq &5 q BY £ q ~ q Pp L rT 4 Ro G yeas 2.8 min, © [5 i] 3 : G2 one hi) D4 G -* 0.20v0.38 S2 ca 0} 4 Onss® SUB fel ro] S4 (top view) ABSOLUTE MAXIMUM RATINGS at 25°C ambient temperature ITEMS SYMBOLS} RATINGS UNITS Terminal Voltage -VT -0.3~30 Vv Operating Temperature Topr |-20 ~ 75 = Storage Temperature Tate .}-55~150 i (to be continued) ‘ &® 75029 RD =265— BLECTRICAL CRARACTERISTICS (<Vp=24Vtl0%, Ta=25°C) ITEMS SYMBOLS | MIN.|TYP.| MAX, | UNITS CONDITIONS Input O Level | -VIL 9.0 V _|. Voltag@l Level | -ViH 3.5 V | Ta=75°C Output Level | -VoLa | 19 VIR =200K0, TacT> CoVinepeo¥ Voltage fl Level | =Vona 225 V | R =20KN,Ta=75°C ,-Vi Level | -Vopp | 15 V]R =200KN, Ta=75°C,- ~] Level | -VoHs 2.0 V[R =20KN, Ta=75°C ,-V 1 Level | -Vowa 1.0 V|R =20KN, Ta=75°C, -Vine=l5v nput Resistance n 10 Mp | -Vin=26.4V Input Draine | Cds 8.0 = =Vps=OV, f=1MHz Capaci- | Source | Css 8.0 pF | -Vss=OV, f=1MHz tanca Gate Cgs 8.0 pF | -Vgs=OV, f=1MHz Propagation|falling| t Lee us | -Vin=O~lo.oV,see Fig.l & 2. Delay Time [rising | tpLk 1.2 us |R =20K9,Cy=50pF VL HD3103 Ry, Pulse Pg tO [>0 ot 4 CRT Oscillo- Generatoy [ Vout it 7 l ie 4 *C), includes a stray capacitance of a probe and wirings. Fig. 1. Propagation Delay Testing Circuit. OUTPUT WAVE FORMS. _ = Oe VIH Input sous Tn, ormmenene, fA f "ry, nl oo aparece Essensa: hon ‘ A | Vou Output ee (i, Lee errno VOL f N | ‘DHL ‘PLA . Pig. 2. Definition of tpyy and tp.y a & 35024 ( (8) HITACHI MOS INTERGRATED CIRCUIT HD3104 DESCRIPTIONS The HITACHI MOS (Metal Qxide Semiconductor) Inte grated circuit HD3104 is a dual 4 input AND gate + two inverters constructed on a silicon monolithic chip utilizing P-channel enhancement mode MOS transistors, belongs to MOS IC HD3100 series especially designed for applications in an electronic desk calculator. And HD3104 is available in a dual is line type ceramic parkege (16 leads). The HD31(4 functions as a 4 input AN? gate (positive logic), inverters, a 4 input NAND gate (positive logic), and others. The features of HD3104 are as foilows : Intergrated zenerclamp protects ga‘es. Large noise margin .ssccceccccecececsccccee NM = 10.07, NMy = 2-0V he Wide operating temperative ...sseceeeeeeees -20°S to +75° * ,see--inverter part DIMENSIONAL OUTLINE PIN CONNECTION SCHEMATIC TIAGRAM 5.06 max. ps2 get a2e on ey =e UU 0.5 min. Cl 2.8 min. D1 yo Bn Eizigini@ > - a GND K2 unit : mm (top view) ABSOLUTE MAXIMUM RATINGS at 25°C ambient temperature. *Inverter part. ‘ ITEMS SYMBOLS | RATINGS UNITS grade NMy, NMy Terminal Voltage -Vr -0.3~ 30 Vv A |i0V | 1.5V Operating temperature Topr =-20~75 *¢ B 6v | 2.0V Storage Temperature Tate -55~150 c (to be continued) #45029 ( h) ELECTRICAL CHARACTERISTICS, (-VGG=24V210%, Ta=25°C, -VL=-VGG) ITEMS SYMBOLS| MIN. | TYP.| MAX.}|UNITS CONDITIONS ' Input QO Level | -VIL 9.0 Vv Voltage |1 Level | -VIH 4.0 Vo sjTa=75°C Output O Level | -VOLA | 19 VIR =200KQ,Ta=75°C,-Vin=9v Voltage [1 Level | -VOHA 2.0 | V. |[R =20KQ, Ta=75°C,-Vin=4V(gy) | ___ {0 Level | -vonB ]19(15 | Vv IR =200KH, Ta=t5°G,-Vi ne OVC4V) Input Resistance Rin 10 MQ {-Vin=26.4V Input gate Cinl 5.9 | pF Capacitancainverter [Cin 8.0 | pr |f=1MHz, -Vin=0V utput Capacitance | cout 8.0 | pF {f=iMiz, -Vout=0v |] PowerDissipation Pd 120... mW |-VGG=24V,-Vin=14V Propagation [falling + pH, | [1.5 | us [-Vin=0 ~12,6V,See Fig.1 & 2. Delay Time frising | + pry 2.0V] us [R =20KQ,C =50pF *,....The value wnich ig showr in pare:':eses is used at testing an inverter VL wsiod[. Lo gy [Pulse | Vin cea sf Vout CRT Oscillo- = Generator ed ee CL includes a stray capacitance of a probe and wirings. Fig. 1. Propagation Nelay Testing Circuit. OUTPUT WAVE FORMS. Input 7 1 me VIL OV — VOH Output -TV ain _— ‘PLE VOL oy \ ~ ~~ Vor Output _ a == Ty (inverter) \ VoL — ‘ > PLE tPHL Fig. 2.Definition of a tpyy, & a tppy *The following value is used at testing an inverter. grade | -V +*VoL YQ uM -Vin | min, -Vin max. 3.5V | 3.5V 19V QV 2,0V B 4.0V | 4.0V 15V OV 2.0V 35029 (42) —26— HITACHI MOS INTEGRATED CIRCUIT HD3106 DESCRIPTIONS The HITACHL MOS (Metal Oxide Semiconductor) Integrated Circuit HD3106 is a dual 2 input & a dual 3 input AND gate (positive logic) constructed on a silicon monolithic chip utilizing P-channel enhancement mode MOS transistors, belongs to HITACHI MOB EC HD3100 series especially designed for applications in an electronic desk calcyhator. And HD3106 is available in a dual in line type ceramic package (16 leads). . The HD3106 functions as a 2 input AND gate, 3 input AND gate, 2 or 3 input AND-OR gate, and others. ‘ The features of HD3106 are as follows: * Integrated zener clamp protects gates. ‘ © Large noise margin .....-.-- (oeqeewonee WR = 10.08, a 228 'V © Wide operating temperature range ....seeees -20°C to +75°C. — nn peeeeneeenmer ogee | DIMENSIONAL OUTLIME PIN CONNECTION SCHEMATIC DIAGRAM 01 tS) 04 2 5 Al [2h L Vac B [3] Ay ' cy [4] B, ) 42 O2 | 7r cup [8] unit :mm { (top view) i... Ele ABSOLUTE MAXIMUM RARINGS at 25°C ambient temperature ITEMS SYMBOLS RATINGS UNITS eS ee ememete ote enn nn eee er et ee mim |e a Terminal Voltage -Vr -0.3 ~ 30 V ee - st Henman eet — — —— i —— _— — Operating Temperature Topr | -20 ~~ 75 *¢ Storage Temperature | ‘Tstg | i sedied 150 *¢ (to be continuegy —207- “i g° 8 , be & LEC CTERIST (-Vgg=24Vt10%, Ta=25°C, -VL=-VGG) [LTEMS [sympots | tn. [TvP. | max. | UNITS] CONDITIONS wd Input i“o” Level. | VIL. | 9.0 es on ee 4 | Voltage gy Level -VIH Z _ oat _ Vv Ta=75°C Output ‘0 Level -VoL i | | V { RE=200K8, Tas 75°C, -Vin=9. ov | — Voltage il Level | -VOH | 7 2.0) __V_{Ri= 20KQ, Ta=75°C ,-Vin=4. OV li Input Resistance _, Rin jf 7 i. : i" MQ | -vin=26. \ si ; Input Capacitance =, Cin» { 5.0} pF |-Vin=0Vv, f=1MHz _ _Output Capacitance ; Cout | 8.0; pM... VOMeney ss Soe mail Power Dissipation ~ Pd. | 100; mW {-Vgge24V, -Vin=l4v_ Propagation , falling | tpyy | 4 Ad ps j|-Vin=0~12.6V,See Fig.1 & 2, Delay Time j risimg } CPLH t i. 1.5} ps | RL=20K2, CL=50pF c pics \ Pulse | Via “Tt 7 CRT Osei lid \Generator| om nee ~ | Scope TT | why ahr ry * Cy includes a stray capacitance of a probe and wirings. . Fig. 1. Propagation Delay Testing Circuit OUTPUT WAVE FORMS ~ Tv V a ees aa Output _ ~7V tPHL ua r * Pig. 2. Definition of a tpyy and @ tpyy HITACHI H DESCRIPTIONS The HITACHI MOS (Metal Oxide Semiconductor) Integrated Circuit HD3107 is a qued- ruple quasi-static delayed flip flop constructed on a silicon monolithic chip utilizing P-channel enhancement mode MOS tramsistors, belongs to HITACHI MOS IC HD3100 series especially designed for applications in an electronic desk calculator. And HD3107 is available in a dual in line type ceramic package (16 leads). ‘ . The HD3107 functions as a 4 bits static D flip flop, a 4 bits parallel in parallel” out static shift register, a 4 bits ring counter, and The features of HD3107 are as follows: e Integrated zener clamp protects gates. * Large noise margin ssseceseessrereereseeees My = 10,0V, Ny "20 V © Wide operating frequency range -esseeresers pC to 100 kHz. * Wide operating temperature ramge --+--+--+++- -20°C to +75°C. ‘ DIMENSIONAL OUTLINE PIN CONNECTION SCHEMATIG DIAGRAM Fe + ke.2.9 q . cpla [2| mn [3 Q1 [4] a [5 | m2 [| cp2a [7] 7 ata cup [8 t tg : F unit : mm ABSOLUTE MAXIMUM RATINGS ITEMS SYMBOLS RATINGS UNITS mnenryere Voltage oat Nip 0.3~ Ww Vv r | operating Temperatuee _Topr -20 ~ 75 “¢ Storage Temperature Tetg | -55 ~ 150 “ (to be continued) | _ > =" (-Vegr24vt10%, Ta™25°C, -Vi=-Vgg). se ti 3 _ ITEMS SYMBOLS -} tere 40 CONDETLOMS | SSS niet ae . Input ‘O"Level | -Vip 9.0 v 5 Voltage i "Level =i =. a) T Ta=75°C | Output foMLevel __- Vor iv | ni Vf R= 200KM! Tex 75°C, cpw=1. Ops Voltage "Level | -Von | ie a R= 20KQ| fopeSkHz, ; Clock a te -i9- v = | Voltage f'1"Level | -Vepy a 40 a Ta=75°C, cpwe ys i, Min. Clock | Clock 1 opdain nae: és "[fep 2 Skite. | cpm]. Ops a. Clock Pulse Width copy 1.0) ah oo See "i ee ee Clock Pulse Delay | epd_|1,0| | [ms [See Mig-2 0 | Clock Capacitance Sep [| | 8.0T pr | f=tltz, VepOv — | Input Resistance = -j_—s Ran 13 ot : | Input Capacitance i eee 5.0 Output Capacitance | cout | 6.0 Power 1_. Pal p ieee a 4 38. J Propagation | falling 1.5 | ps |, -VineO~ $8.60, fcp-10kHz, Delay Time rising | ¢puy i 2.0} ys |, Rpt 20KQ, Cre 20pF, opens £ q NOTE : Cpl and cp2 are both controllable, and when cpl iq controlled, cp2 amit be. given at from 5 kHz te 100kHz repetition rate, and when cp2 is contfelled, cpl must Be given at from 5 kHz te 100kHz repetition rate. ; NOTE : Pdl and Pd2 do not contain power dissipation which is consumed at exterea¥ load resistance (Ry). t i ~ Pulae | Vip a Generatdr} _ HD3107° it 7 = eft J * Cy includes a stray capecitapce ofa probe and wirings.. og Fig. 1. Output Voltage and Propagation Delay ohe Testing Circuit “he ; Be QUEPUT WAVE KORMS 7 [— = aan OV eS a oa oe. cpl i . 3 eS Paanuseneres Say P RFI macs r _ ~< Z ~~ cp2 = | Se ——=7V , _cpw2 « ep . a ee iy Vou Output —--7V <—_——- Fig. 2. Clock & Output Wave Forms a ae b es =—210—~ TYPICAL TIMING CHART *! = Tua m ner * | 1 ia cpl controlled i cp2 controlled woe | TY Output ~| | - 1 bit delay CLOCK PULSE GENERATOR BOLCK DIAGRAM Fig. 3. Fiming Chart E |}—~-O @l° } may +t ~~ epwi ; E --- Emitter Follower , MMV E t—o cp2 AMV --- Astable Multi pw Vibrator | t MMV --- Mono-stable Multi ; : i Vibrator ; Bue |B [0 Date Pulse» BMV --- Bistable Multi ~ aie ib ; ge Vibrator 4. Clock Pulee Generator Block Deagrem nae DESCRIPTIONS f The HITACHI MOS (Metal Oxide Semiconduetor) Integrated Circuit HD3209 fs 2 60 + 4 + 4 bits dynamic shift register with control gate constructed on a @1]4 wopolithic ,f chip utilizing P-channel enhaticement mode MOS trapeistors, belongs te gt Moe Ic ¢ HD3100 series especially designed for applications in an electronic desk calculator. And HD3109 is available in a duel in line type ceramic package (24 leads). The HD3109 functions‘ as @ 4 bits dynamic shift register, a 60 bits dynamic ehift register, a 64 bits or 68 bite dynamic shift register, ahd others. The features of HD3109 are aa follows: ‘ es % Integrated zener clamp protects gates. ' Large noise margin ....+-+sseeeererenes coewe os 1.0 V, a” 2.0 V Wide opetating frequency range «+++-++ereere Oi te 100 Wide operating temperature range «+.-++sseres ~20°¢ te +75°C DIMENSIONAL OUTLINE PIN CONNECTION 14 né “ NC ? READ [4 Tm60 [5 ] NC S . Ce NC 7} cpla Nc ‘wnit : om (top view) ‘ ITEMS S¥MBOLS Terminal Voltage as 7 0.3~ Operating Temperatute Topr ~20 ~ te] } .p.Srorage Temperate Tete ri 1$0 *¢ | a. * "Es t (xo be.continued) | a9 TYPICAL TIMING CHART eon. "Vda Input i y i | Output. 7 ee eee (y. ey L (060) 60 bit delay a Fig. 3. Timing Chart P DIAGRAM | | MV Rk F—° opt wh AMV P fcp a ; t . —— : E AMW --- Astable Muiti- snd S id se Vibrator : cpw2 MMV --- Mono-stable Multi- is _ Vibrator BMV E /}—0O Data Pulse BMV --- Bistable Muti-Vibrator ’ E --- Emitter Follower Fig. 4. Clock Pulse Generator Block Diagram vote le SCHEMATIC DIAGRAM _ 60 pat delayg t aes yt Input H ‘ | ' Output (Ingo) s+ whe o(%; 9) ‘RC oan | t l 7 gr aoa F —_ —° cp ~ | 4 bit "Te | - delay me . ‘ t ; B utpu il d { cy H Hy 7 (048) VpD as Aaa ihtonttmecmen ty am poe in a Sg a ile -_ cpla 4 bit delay A 6 a Out nput (Oga) = (Ing) Fig. 5. Schematic Circuit - a he 3 . + 3 a 4 ; - Testing Cireuit . ’ ; ; e cpl a pep’ ly -* , ep2 Out put _ camee an FY sirag oo, CPHL tPLH (-Vgg"24vt10%, -Vpp=14vtioz, fae25*cf - ,- | . i ITEMS SYMBOIS|MIN. | WP, MAX.[ UNITS] _CONDIFIONS ‘ Input ie Level -Vyy, | 9.04 = Loe {oy F ‘4 Fourput [0 Level “yu [aaah], ¥ |Mriegmbte7s"c,m2- Ope | |... Voltage ‘arent ~[ ROT ¥ | Rp=50KaQ) fcp=10KHe Clock "0" Level 4 26.4] V __ Voltage "4" Level - i | 4.0 v Ten35°C, cowsiene Min. Clock Frequency | | [10] betta Tren 75%c remem: aback Fulee Width | cpw | 208 a a See Fig.2, Clock Pulse Delay | pd’ j 1.0). | a|_ws__| See Sage Ras: 20a fInput Resistance | Rin | 10; } ya [-vine26.4V |input Capacitance | Cin beeen 4 5.0 | pF | felMiz, -VineOV 3 Output Capacitance | Cout | = -_s|_10 | ph | fe lMiiz, ~¥owteOV \Fower dissipation ee on eee ee Yeeeast, ster Ae fope1db Propagation T falling) tPHL | t-- nial, | we | “Win-O~ 12,6V, fep= ae Delay Time f rising | tpry | ; 1.5 | pe || Cy=20pF, Ry=00 See Pig. & 2. Ypp ec T Pulse | , |__¢ | crr oscillo Generator Vin HD3209. Cy pee fi Scope out ¢ -. | - ee er ee + i cp2 Cr includes @ stray enpackianee. : of a probe and wirings. Fig. 1. Qutput Voltage & Propagation Delay Fig. 2. Clock & Output Wave Form, i , anit HITACHI MOS INTEGRATED CIRCUIT HD3112 DESCRIPTIONS The HITACHI MOS (Metal Oxide Semicgnductor) Integrated Ciucuit HD3112 is an integrated sub-system on a silicon monolithic chip utilizing P-channel enhancement mode MOS transistors, belongs to HITACHI MOS IC HD3100 series especially designd for applications in an electronic desk calculator. And HD3112 is available in a dual-in-line type ceramic package (24 leads). The HD3112 includes about 100 gates and performs the function of series delayed ful] Adder/ Subtractor. The features of HD3112 are as follows: . ° Integrated zener clamp protects gates, ° Large noise margin.is...sseves SGA RNS wE NML#2V, NMH®2V oWide operating frequency range........... DC to 100KHz. e Wide operating temprature range......., -20°C to +75°C., PIN CONNECTION epl 1 a a cp2 2 Yog \24 Yop Delayed E BCD 2g tz Full i19 CR Xin | Adder F Gf Bn ob mar = Bt S/p ona iag! ad x | 7 (top view) UNIT | mm i *Pin 2,4,5,@must be open. | fi i _ a: ABSOLUTE. MAXIMUM RATINGS at 25°C anbient temperature: ITEMS SYMBOLS RATINGS UNITS a aes ale acaaleas “ he ‘ ee | Terminal — -Vr -0.3-~30 V pics ae Se ooo Operating ‘Temperature Topr -20-~ 75 | = Storage Temperature | Tstg ~55—~150| °C =216— (to he continued) INITIO SY Input | An ]BcD or Binary DATA | Bn ; BCD or Binary DATA ' Xini X-Register Input | Cp Carry or Borrow Fli | utput | Fy ; Sum or Difference X2 X-Register Output 2 X, X-Register Output 4 ' Xg .X-Register Output 8 ‘Cn BhCarry or Borrow S/D Sum or Difference a/s app /SUB control ‘BCD Binary/BCD control | tg Bit Time t4 clock pulse ‘clock pulse x-Register clock pu control t os ‘Power “tree [ ;Source Voc ! be i cones sr ceceaniit p-flop Reset H (Binary) — ! (BCD) | a/s_ BoD | Function __ ) 0 0 | Binary Addition 0) 1 | BCD Addition a 0 , Binary lse 1 1 (BCD Subtracto TIMING CHART _ EXAMPLE : 15+16 in BCD Format. cpl=cpx | il.) TUT TT epg et ETE TTT ae FP AAT Ind coe LLL LL LLL *: internaiiy generated. a TLE A TLL LI 4 SL LAL ALLL a/s (espe crys geese nee BCD a _ An nn ! (15) BCD m J UL (26) BCD FA ee 0 el Cn/Bn fq 7 sp UC (41) BCD NOTE: Cpl is controllable when c rate. Cp2 is uncontrollable repetition rate, OUTPUT WAVE FORMS cpl Fig.1. ELECTRICAL CH STICS (-Vog=24V410%, -Vpp=14Vt£10%, Ta=25°C) oo LTEMS SYMBOL@ MIN BA TYP | MAX. | UNITS CONDI TIONS Input evel =| ~VIL | 9.0 | i V___| Ta=75°C Voltage: Vin | 1 14.0 | V Output Vor [ii [_ ‘ V RL=100K7i}Ta=75°C, cpw=2.Gus, Voltage + 7Vou bere V RL= 30K‘. |f£cp=10KHz | Clock ; “Ve V9 “126.4 | V | a Voltage ae 0 | 4.0: | vi * | DAR 7S°C,, ‘cpwegus Min. Clock Frequency | Fcpmini ee KHz Ta=75°C, FepZST0KHz Clock Pulse Width | cpw [2.0 } — O” | as [See Frg.2 Clock Pulse Delay Tecpd' [1.0; {| 7 as See Fig.2 Clock Capacitance | Cep TRO PF) F#IMHz, =Vep=Ov | Input Resistance Rin Mg BL MoT Vine ZE SV | Input Capacitance Cin “Ay PF f= IMHz ,=-Vin=0V | Output Capacitance Cout | “t “ f10 PF | f<IMHzZ) at lt) rr | Power Dissipation ~ ~~ T Pa 7 120: mw epee Za, Vppa Ts, -Vegezay Propagation | Output tpHL | aa 0 4s - exceptCn/Bh tpLH : 6.0 [as Vin=0 ~12.6V, fcp=10KHz Delay Time | | tpHL ~ "T.0 Tas Cy=20PF, RL=100Ki, Cn/Bn j tpLit .0 | ais See Fig. 1&2 p2 is given at fro and always must be give m 10KHz to 1OOKHz repetition n at from 10KHz to 100KHz — CRT Oscillot te hig] Wa Scope _ iirc | 4 T cL | som 4 - - Cy, includes a stray capacitance of a probe and wirings. Output Voltage & Propagation Delay Testing Circuit. —p cpd'2 cp2 a Zach OV om = 1 8V cpd'l Vepl. ov a VepH -7V | ~18V -——--—-— VepL = OV Output tpHL ——_- VvOH ~—-7 oe VOL i tpLH Fig.2. Clock & Output Wave Forms (to be continued) = Ne ’ HITACHI MOS INTEGRATED CIRCUIT HD3115 DESCRIPTIONS The HITACHI MOS (Metal Oxide Semiconductgr) Integrated Circuit HD3115 ts‘a triple qdasi-static R-S-S flip flop. constructgg @n a silicon monolithic chip etiliz- ing P-channel enhancement mode MOS transistore% belongs to HITACHI MOS IC §B3100 series especially designed for applications in-an electronic desk caleulator. And HD3115 is available in a dual in line type ceramic package (16 leads). The HD3115 functions as a R-S-S flip flop, a cotnter, a memory, and others. The features of HD3115 are as follows: Integrated zener clamp protects gates. Large noise margin wveesseeeeevserseecceceeses NMp = 10.0V, MMy = 2.0 V Wide operating frequency range .-.eseeeseeees DC to 1O0kHz. Wide operating temperature range ........++++ -20°C to +75°C. oo 6 @ DIMENSIONAL OUTLINE PIN CONNECTION TRUTH TABLE ! ‘ cpl[1j) 46) R3 | z a ——— | Q3 | 2h 10 -R ) 115] Vgg | Sn Rn ft Ort | = >) Fr Q3 | 3/si_s}-114) $3 | | 9 | O | Q | 0 i 1 5 0 | @ [4 rye s2 | | 1 0 1 — OR Pe basing 5 Teg s sppeneeie ncaa een | [6h 07 RE) 1 f 1]. | ' a [7 ea S$ :—{10| S] dstecsreomrcilioas cal | | ed = Po cup [ 8, | Se Qnt1 = Sn + Ra-Qn i unit ; mm | (top view) ABSOLUTE MAXIMUM RATINGS at 25°C ambient temperature ITEMS SYMBOLS RATINGS UNITS Terminal Voltage -VT -0.3~ 30 V Ee seers 2 oo inn b= + Operating Temperature| Topr | ~2) e 75 éc_ ° Storage Temperature Tstg -55 ~ 150 c Sa oo eee -* = = (to be continued) G_ CHART" cpl lt mi | 2 1 aor = in | ai 1 ri q | Input S L ~ | Lo 7 = ‘aa i a ~ pl v _——-— | — : ss - ——— — -| a Output Q F bit SS | | a on * Output Q J 7 poe T — Fig. 3. Timing Chart CLOCK PULSE GENERATOR .BLOCK DIAGRAM ’ Le MMV E /--O cpl — i= | AMY i cpwl E --- Emitter Follower fep |. __4}-»-tJ MV E | ep2 ; "os 7 || + cpw2 ‘ | } j = os o any --- Astable multi ~~ a . ~o DPl (input ®) Vibrator seer: mails z MMV --- Mono-stable multi i = Vibrator SI BMV LU E L ~O ,DP2 (dnput BMV --- Bistable multi 4 | | r Vibrator Fig. 4. Clock Pulse Generator Block Diagram SCHEMATIC DIAGRAM Voc sd Vv O70 Q : ON tre S oS Q © GND R OF cpl Q- > cp2 Oo; - Fig. 5. Schematic Diagram -214 = ELECTRICAL CHARACTERISTICS (-Vgg=24Vt10%, Ta=25°C, ~ViL=-V6G) : a _ITEMS |SYMBOLS | _ MIN. . TYP.| 2p MAX. jane CONDITIONS Input “of ‘Level | -Van_ 79.0) — ot eosm Voltage “Level | -VIH | lhe Totes c Sil decal Scehlee Ma ms Snee oe errs i 2 sess pee Voltage - fl Level | -VoH iz 1 2.0, V_ [Rp= 20KQ fep=5kHz a Clock So’ Level | -Vepy | 19 | 126.4) Vv . Voltage 1" Level | Vera |} sj $0] [TASC epee Min. Clock {Clock 1 |fcplmin| |, 0 | Hz. |fcp2=SkHa] cpw=1.0us_ | _ Frequency _j Clock 2 | fcp2min | ed 0.4 He jfepde Ska Tas75°C | Clock Pulee Width | Gp 2 LO cd cee ara on | Glock Pulse Delay |. cpd'. [200 4. i . Clock Capacitance _ Cop of. he 13 | pF j,f=1MHz, =VepsOV | Input Resistance Rin 10° i | M2 -Vine26.4V { stance = LBM 5 bi cm mere ee wh eee sa Beaters | Input Capacitance ___|_ Cin = pees oe PP | faim, eat Bs ! | Output Capacitance Cout_ | sit 4 (8.0) pF | felMHz, OO Power Dissipations Pd fe j 100 mW is Vggr-Vep=24V, -Vin=14V(S=R) | Propagation “falling tpHy | . 2.0 ‘Ss ‘-VineQ~12.6V, fcp=10kHz, | Delay Time [rising | tppg i ji 2:0) BS |R,=20K2,, Cy =20pF, cpw= lps NOTE ; Cpl and cp2 ar given at from 5 kHz t e both controllable, and when cpl is controlled, cp2 must be o 100kHz repetition rate, and when cp2 is controlled, cpl must be given at from 5 kHz to 100kHz repetition rate. Vac z. . i = HD3115 i Vout CRI Oscillo- | L a” Scope ee $ cL i | = en oe! ee BY wtp “cp2- a a ony Cy includes a stray capacitance of a probe and wirings. Fig. 1, Output Voltage and Propagation Delay Testing Circuit QUTPUT WAVE FORMS epl | ; P on cpd'® - Se apemiccrts Cerne os bee a |} ss gy ' — Ve =| cpwl ecpd' PL {cp a | fs =e coe — = = =4V VepyH ene fie mS 7 ~7V - ann — 18V ere 1 BY vopL sissies —OV Vv OH mm. : — _. Sn, CPHL CPLH Fig. 2. Clock & Output Wave Forms (to be continued)