Reference / Paper
A 52-page theory of operation: the delay line time-multiplexed into 16 channels, the PLL clock locked to the line, the 1-2-4-2 serial arithmetic, programming, the display latch, zero blanking and thousands separators.
Sony 2500 Calculator Theory of Operation & Summary User Manual bhilpert / madrona.ca 2024 Oct Rendition: 2025-Jul-13 1 Table of Contents Introduction • Architectural Overview 3 4 Implementation of Logic 5 Timing 6 Channel Layer 8 Register Layer • Realign-Rotate Process 13 13 Digits • DX Digit • DY Digit • DN Digit • DM Digit • DF & DFp Digits 15 15 15 16 16 16 Counters • DPC - Decimal Point Counter • CJ - Utility Counter • CK - Utility Counter 17 17 18 18 Flags • µA Flag: SST, PBRD, PQPA • µB Flag: SNML, PNEG • µC Flag: PNEWN2, PPHE • µD Flag: RDD>0, PPH2 • µS Flag: SPARM, SSKIP • µY Flag: DY.W, PDPE • µØ Flag: INTØ, PQRDØ, RNDØ • RDNEG Flag 19 19 19 19 20 20 20 20 20 2 Procedure Layer • PM - Procedure State Machine • Main Loop • Zero-Blanking • Rounding • CLR-ALL & CLR-ENTRY • NML-ENTRY & PNEWN Flag • MEM-CLR & MEM-IN • MEM-OUT • REVERSE • QUEUE-OP • ADD/SUB • MULTIPLY • DIVIDE • SQUARE-ROOT 21 21 21 21 22 23 23 24 24 25 25 25 26 27 27 Supervisor Layer • SM - Supervisor State Machine • SPC - Program Counter • Execution & the EXEC Flag • AUTO Mode • LIST Mode • LEARN Mode • EDIT Mode • IDLE • DIGIT & the SNML Flag • MEM-SET & the SMSET Flag • JUMP & the SSKIP Flag • Non-Code Operations 31 31 31 32 33 33 34 35 35 36 36 36 37 Appendix 1 - Table of PM States 38 Appendix 2 - List of Operations 42 Appendix 3 - Summary User Manual • Registers • Keys • Switches • Indicator Lamps • Programming Notes • Program Example 1 • Program Example 2 • Program Example 3 • Program Example 4 • Program Example 4a 43 43 43 45 45 46 47 48 49 50 51 Introduction The Sony 2500 is a programmable desktop calculator from 1969. A schematic was produced from a reverse-engineering of a 2500 unit. A logic simulation was produced from the schematic. This commentary is intended as accompaniment to the reverse-engineered schematic, having been produced from analysis of the schematic and exercise of the simulation. Proviso: There remain areas and aspects of the design not covered in this commentary. Descriptions are not promised to be comprehensive, e.g. the Table of PM States may not specify all actions occurring in some state. [reference]: Text within square brackets is a reference to some page, figure or component: [15] page in this document [SCH.15] page in schematic document [SCX.3] page in schematic appendix document [E216.3] pin 3 of IC E216 in schematic 3 Architectural Overview The Sony 2500 is a bit-serial design using a single magnetostrictive acoustic delay line for number and user-program storage. Conceptually, the architecture can be construed into 4 layers: User / Keyboard Supervisor Layer Procedure Layer Register Layer Channel Layer • Channel Layer At the lowest level, the Channel Layer deals with the details of multiplexing the single delay-line into a set of 15 registers. Each register as presented to the Register Layer is an independant recycling bitstream of 64 bits each. • Register Layer The Register Layer interprets the bitstreams from the Channel Layer as 16 digits of 4 bits/digit. Some of the bitstreams are used for number storage and some for storage of user-entered programs. For numbers, this layer performs bit-level intra-register operations such as the serial addition of bits and digit normalisation. For program storage, this layer delivers an addressed instruction to the upper layers for execution as directed by the Supervisor Layer. A program instruction is a 4-bit function code stored in a register digit. • Procedure Layer The Procedure Layer sees the number registers as a sequence of digits. It performs the arithmetic functions and sequences actions such as moving operands and results between registers. The state machine PM controls procedure execution. • Supervisor Layer The Supervisor Layer deals with keyboard activity and execution of the user program. The state machine SM controls these actions. The Supervisor Layer accesses the Register layer for the user-program storage. 4 Electronic Implementation of Logic The logic of the 2500 is implemented with a small family of SSI integrated circuits produced by, and proprietary to, Sony. This family is referred to here as the 500 series [SCX.8]. There are 4 types of ICs from this family used in the 2500, though there are understood to be a small number of additional ICs in the family. The 504 flip-flop IC type is further divided into 3 subtypes of -30 -40 -50. This was likely a post-production grading for speed. The 500 series uses bipolar NPN transistors operating in current-sinking mode. Vcc is +4V. Logic 0 is low-impedance to GND, logic 1 is high-impedance to GND. • Inputs Inputs are frequently left unconnected. Such inputs are seen in logic terms as 1. • Outputs The gate outputs do not have load or pull-up resistors. The flip-flop outputs do have load resistors of ~ 1.1K. Multiple gate outputs may be connected together to form a wired-AND gate (negative-logic OR). • Flip-flops FF outputs transition on the 1-edge (positive) of the Ø input. The G (Gate) input controls whether the JK input state will update the outputs or not, when a 1-edge at the Ø input occurs. If G=1, normal JK operation takes place. If G=0 the outputs will not change, i.e. equivalent to J=0 & K=0. The flip-flops do not have asynchronous set or reset inputs. They can however, be asynchronously set and reset via collector triggerring by asserting 0 at an output, e.g. asserting 0 to the Q~ output sets the FF to Q=1. 5 Timing The system timing is tied tightly to the operation of the acoustic delay-line providing storage. The delay-line presents a requirement of precise data timing to maintain sychronism with any drift in latency. In other delay-line implementations this may be provided by a crystalcontrolled master clock. The 2500 takes an alternative approach. The master clock is an RC astable flip-flop functioning as the VCO in a phase-locked-loop arrangement with a phase comparator and the delay-line in the loop. This is discussed further in the Channel Layer section. For following commentary refer to the Timing Diagram [SCX.1]. • Master Clock The master clock is the astable flip-flop formed from QF13,18. QF19 is a local voltage regulator for the master clock. The output from this astable is buffered to produce the master clock signal ØS. The frequency of the astable can be adjusted by varying the QF13,18 base bias via Darlington pair QF16,17. This functions then, as the voltage-control input for the PLL VCO. • Channel Slicing ØS sets the raw bit rate for writing-to and reading-from the delay line. The delay line is time-division multiplexed into 16 channels. The channels are delineated in time by the ØS Counter (ØSC) and identified as ØS0::15. ØSC is a straightforward 16-stage 1-of-16 ring counter. • ØB Selected outputs from ØSC feed flip-flop [F408.9] to produce a signal ØB which has a cycle period equal to a full 16-state cycle of ØSC. The duty cycle of ØB is designed in conjunction with the register allocation of the delay line channels (see RS cycling). ØB is the register-level bit clock for the serial processing of numbers, with the 1-edge delineating these bits. At the register layer and above, all flip-flops are clocked by ØB. The G input to the FFs is then used - if necessary - to control the bit periods at which transitions occur. • Bits of Digits A digit is comprised of 4 bits. The bits of a digit are delineated in time by the ØB Counter (ØBC). ØBC is a 2-stage switch-tail ring counter. The bits of a digit are identified as ØB0,1,2,3 corresponding to bit weights 1,2,4,W, though not all need to be decoded from ØBC to actual signals. • Digits of Numbers A number is comprised of 16 digits. The digits are delineated by the ØD Counter (ØDC). ØDC is an SR16-type counter. By default it produces the full 16-state SR16 sequence. The ØDC state is decoded to signals ØD0::15 with ØD0 corresponding to digit 0 (LSD) of a number. ØDC provides a simple example of the use of the G inputs of the flipflops. The G inputs are fed by ØB3, resulting in the JK state updating the flip-flops on the 1-edge of ØB at the end of ØB3. The counter transitions thus occur at the end of digit periods. • Extended NC Assertion of PNCEXT (Number Cycle EXTend) extends the ØDC sequence to 17 states by inserting an additional digit period (ØDEXT) between digits ØD11 & ØD12. This is used when the digit registers DX,DY,DN are inserted into the register bit-loops during processing. 6 • Numbers A full 16- or 17-digit cycle of ØDC then, constitutes a number cycle. Signal ØEON (End of Number) is a pulse produced during the last bit of a number cycle (ØB3 of ØD15). • State Transitions State cycles for the execution state machines SM & PM are synonymous with number cycles. The G inputs of the SM & PM state-register flip-flops (SM.n,PM.n) are fed by ØEON, with ØB feeding the Ø input. SM & PM state transitions thus take place on the 1-edge of ØB at the end of ØB3 of ØD15. 7 Channel Layer The channel layer provides the storage for numbers and user programs. The channel layer is comprised of the acoustic delay line (ADL), its read and write amplifiers, the clock synchronisation circuitry, the flip-flops DLRCV, DLa, DLap, DLb, and a set of flipflops and gates for multiplexing and demultiplexing the delay line into bitstreams to present to the register layer. While the ADL provides the vast majority of the storage, the delay-line in full includes storage provided by some of the ancillary flip-flops [SCX.4]. • Physical The ADL is a magnetostrictive acoustic delay-line operated in the longitudinal mode. The wire forming the storage medium is ~ 362 cm long, looped into a coil of 10 turns. At each end is a transducer solenoid, one for write and one for read. • Channels As mentioned in the timing commentary, the delay-line is multiplexed into 16 channels. 15 of the channels become a register each. The remaining channel is injected with a fixed pattern to provide a sync signal to the phase comparator of the master clock PLL. The time period for a channel will be referred to as a slice and are identified as ØS0::15. • Storage Each channel provides 64 bits of storage. Interpreted as a register the 64 bits are 16 digits of 4 bits each. For 16 registers, the full delay-line loop needs to be 1024=16*64 bits [SCX.4]. Four of the 1024 bits are provided outside the ADL. DLa with DLap provide one bit of the four, DLc is one, the remaining two are the multiple flip-flops of the demultiplexed registers where a bit resides for 2 slice periods before being written back to the ADL. The ADL then, must store 1020 bits. • ADL bit injection Bits are injected into the ADL on the 0-edge of ØS. This is the middle of a channel-slice period when the state of channel-bits is stable in flip-flop storage. The 0-edge of ØS triggers the injection monostable flip-flop [QF21,27] to produce a pulse of ~ 500nS. This pulse is gated by the 1-state of a multiplexed channel-bit ADLINJ [F310.6] to drive current in the ADL write solenoid [QF30]. • ADL bit exit The degenerated pulses from the ADL read solenoid are first AC amplified [2 in ADL,QF2,4], then re-formed into binary pulses of again ~ 500nS [QF5,7], to appear as signal ADLRD. • ADL sync For a given latency in the ADL, the frequency of the master clock must be such that bits are injected into the delay line at a rate whereby 1020 bits will reside between the write and read solenoids. Channel 0 of the delay line is used to carry sync marker bits. These markers are injected regularly into the channel [F412.3] from the timing system, they are not recycled per se. Re-formed pulses from the ADL are gated with timing signals to extract the anticipated sync markers. The sync markers are fed to a phase comparator for comparison with a signal from the timing counters. Variations in time between the markers and the timing system signal adjusts a charge pump which maintains the 8 voltage level into the master-clock frequency-control input. • Charge pump F306.3, F306.5, Q14,15 and associated components form the charge pump. Capacitor CF24 is the charge storage. Resistors RF44,45,48 present a determined discharge rate for CF24. CF24 is charged by asserting 1 at either of the two control inputs driven by TNUPC and TNUPF (Tune UP Course & Fine). TNUPC=1 turns on QF14 to charge CF24 quickly through the low-R emitter resistor. TNUPF=1 turns on QF15 but the charge rate is slower due to the much higher R of RF48. The voltage on CF24 (TNV) feeds the frequency control input to the master clock. The high-gain Darlington-pair QF16,QF17 reduces the load on CF24 so the discharge rate will be in better accordance with the engineered rate set by RF44,45,48. • Achieving sync In normal operation, the phase comparison is made at slice-period resolution while updated at a per-digit rate. At power-on, the initial master-clock frequency will be some distance from the needed target, requiring a wider capture range to bring the frequency closer to target. The frequency must be resolved to the precision of a particular slice in the full number cycle. There are two phase comparators that resolve the synchronisation to different levels of precision: a coarse comparator (TNUPC) that will be used to bring sync into number-cycle precision, and a fine comparator (TNUPF) that will be used to then bring sync into channel-slice precision and maintain it there. In the following commentary, functioning of the TNUPF comparator during normal, post-initialisation operation will be described first, followed by the TNUPC comparator, and then the process of achieving sync during initialisation. Reference also the phase comparator timing diagrams [SCX.2]. • Fine tuning The TNUPF flip-flop [QF9,12] is triggered at a per-digit rate but its duty cycle will vary with the error of the master-clock from the ØS target frequency. The target is not a fixed frequency, rather it is dependant on the delay period of the ADL which may vary. During ØB3, TNUPF is set 1 at the beginning of ØS10 [F308.6] and cleared 0 by an extracted sync marker from the ADL [F308.5]. The lower the ØS frequency, the longer the TNUPF 1-period, thus a lower ØS frequency charges up CF24 more, raising the ØS frequency. The sync marker pulses are expected during ØS14 [F308.3]. The sync markers were injected during ØS2 of ØB0 [F412.3]. ØS14 of ØB3 is 4 slices earlier than this to compensate for the 4 bits of the delay line in flip-flops, outside the ADL. The sync markers are isolated further into the 2nd half of ØS [F308.11] – this is significant in the resolution precision of the loop operation. The loop response is slower than the per-digit update rate. In practice, 9 the ØS10-to-ØS14 charge period is not long enough to fully compensate for discharge. In observation of unit 620175, the ØS frequency slowly lowers over ~ 11 digit periods till the 2 nd half of the ØS14 period slips beyond the sync markers and the markers are in the 1 st half. TNUPF is then no longer cleared 0, instead continuing 1 through the digit period, this condition persisting for ~ 8 digit periods when the frequency is high enough to bring the 2nd half of ØS14 back to the markers. This correction cycle repeats with some jitter of ~ ±1 digit [SCX.2]. The net result is the ØS frequency is maintained such that the 0-edge of the re-formed read pulses from the ADL are synchronous with the 0edge of ØS. The ADL delay from injected pulse to re-formed pulse is: delay(ADL) = 1020 • period(ØS) – 500nS The 500nS being due to the injected pulse starting on the 0-edge of ØS whereas the re-formed pulse ends on the 0-edge of ØS. • Coarse tuning The coarse phase comparator TNUPC is formed from two flip-flops [F305]. F305.9=1 for the period of ØS11 to the end of ØS0 during EON. If a sync marker is received outside of this period, TNUPCp asserts 1 to enable fast charging of CF24 to bring up TNV and raise the frequency of ØS. Eventually the F305.9 1-period coincides with the sync marker and TNUPCp is cleared 0 to stop the fast charging. • Sync init process There are two RC power-on-reset circuits: those of CF4 & CF34, with CF34 being the longer. Initialisation proceeds in several stages [SCX.2]. Note TNRDY, TNUPCp and TNUPC are electrically the same signal. 0. Power up: CF34 is not charged; once power and basic circuit operation has stabilised, INIT=1. CF4 is not charged, so TNRDY=0, suppressing coarse tuning of CF24. Charge pump capacitor CF24 is not charged and the ØS frequency starts out being low. Sync markers are injected once every number cycle [F412.6,1]. 1. EON capture: As CF4 charges, TNRDY eventually asserts 1, enabling the coarse-tuning phase comparator [F305.3] to assert TNUPC=1 till the EON sub-pulse [F305.9] coincides with the sync markers. Once this is achieved, this phase comparator is essentially out-of-the-picture and the fine-tuning phase comparator takes over. 2. Channel capture: As INIT is still 1, sync marker gating into the fine-tuning phase comparator is enabled to select sync markers during ØS14 of only EON [F307.5,6]. The ØS frequency is now slowly raised further to pull ØS14 to coincide with the sync markers. 3. Normal operation: Once CF34 charges sufficiently, INIT goes 0, and the sync marker injection and gating switches to the perdigit rate of normal operation, as described previously. The 10 coarse-tuning phase comparator is also formally disabled [F305.2]. • Power-off When power is turned off, the charge in a 10µF capacitor charged to 100V is dumped in part into CF38 to turn on QF20. This discharges both CF24 and CF34 so a quick re-power-on is ensured to perform the full initialisation cycle. CF4 is discharged by a reverse diode to V+4. The 10µF@100V charge is also distributed to dump through the ADL delay-medium wire. This is curious but may have something to do with magnetising the wire to enhance or maintain the magnetostrictive characteristic. • ADL bit recovery The DLRCV flip-flop is the initial receiving flip-flop of read pulses from the ADL. DLRCV is not an additive bit in the delay loop though, rather, it overlaps in time with the last bit of the ADL. DLRCV is cleared 0 at the beginning of a slice period, the appropriate bit pulse from the ADL then has a window of (less than) one slice period to exit the ADL and set DLRCV=1 before the bit is clocked out of DLRCV to DLa. DLa is gated by DLRCV to toggle when DLRCV=1. DLap holds the prior state of DLa and the two feed an XOR gate [F303.3,6;F304.1]. The output of the XOR is 1 if DLa toggled. The net storage or delay is only one bit after DLRCV – DLap is not additive to the delay. It is not clear why this toggle-with-transition-detector was used to transform the 1s from DLRCV to a transition and then back to 1s – perhaps to avoid a differential feed from the capacitor-coupled DLRCV flip-flop. • Channel allocation The 16 channels of the delay line are allocated per the table following. The channel identification corresponds to the slice period during which bits of the associated register appear in flip-flop DLb – the last delay line stage prior to demultiplexing. Included are the DM and SPr values which will select the RS registers. Delay-Line Channel Allocation • Multiplexing Channel ØS Use 0 Sync 1 DM SPr Channel ØS Use DM SPr 8 RM7 RP5 0xD 0x0 RA 9 RM5 RP7 0xB 0x2 2 RD 10 RM6 RP6 0xC 0x4 3 RB 11 RP2 0x6 4 RM3 0x3 12 RP3 0x3 5 RM4 0x4 13 RP1 0x5 6 RM1 0x1 14 RP4 0x1 7 RM2 0x2 15 RT To present the channels as registers they are demultiplexed into the set 11 of flip-flops RD,A,B,T,S. The recovered channel bits are distributed into these flip-flops as they exit DLb. After two slice periods they are recycled back into the delay-line, e.g. note the two-slice difference between F405.11 and F412.10. The bits none-the-less persist in the demultiplex flip-flops for longer, through the 1-edge of ØB. This is the transition or processing edge at the register level, thus the bits in these flip-flops are simultaneously available for inter-operation at the register level, such as summing two of them. • RT logic differs The logic for multiplexing RT differs from the other registers [F404.4,F408.4]. [F404.4] is loaded at the same time as DLb. [F408.4] is collector-set by level from RTw rather than by edge. It is not clear why this was done, perhaps to avoid a clocked transition for RT channel-bits which would otherwise occur on the transition edge for register-bits, or due to the logic being too slow for the half-slice preparation period before the bit is written to the ADL. • RS registers 11 channels are allocated to the 7 user memories (RMn) and user program storage (RPn). Collectively, they are referred to as the RS registers. These registers share the bitstream RS. Only one of these registers can be accessed at a time. The selection is determined by the ØSn signal fed to [E314.2]. The bit stream of the currently selected RS register appears as signal RS. • RS cycling Normally, all the RS registers - including that selected - loop internally in the channel layer through flip-flops RSc & RSd [F407.9,F407.4]. These two flip-flops provide the 2 bits of storage to complete the data-loop length of these registers. A gate in this path is enabled to pass data during the 0 period of ØB [F410.12]. The duty cycle of ØB has been chosen such that it is 0 for the write-periods of the RS register channels and 1 for the write-period of the others [F408.7,8], thus the others are prohibited from cycling via this path. • RS write To write to an RS register it must be selected, the desired bit stream fed to RSw, and RSwENB asserted 1. RSwENB=1 enables flip-flops [F409.9,F409.4]. These flip-flops delay the selected slice phase 2 slice-periods. For the delayed slice phase, the normal RS recycle path is disabled [F410.11] and a data bit from RSw enabled for injection to the ADL [F410.10]. 12 Register Layer The objective of the register layer is to provide to the procedure layer an interface that deals with multi-digit decimal numbers. The task of the register layer then, is to perform the operations internal to registers: arithmetic operations at the bit level, digit normalisation, digit shifting, transferring register contents between registers, etc. The channel layer provides 15 64-bit registers to the register layer. Four registers - RD,A,B,T - are presented as individual bit-streams. The remaining 11, referred to as the RS registers, share a bit-stream as RS. • Register RD RD is the displayed number, be it an operand being entered or a result. • Register RA RA is an operand and results register. • Register RB Between operations RB contains a prior operand; during operations RB is used as an internal temporary. • Register RT With tally mode enabled, the tally sum accumulates in RT. • Registers RS 4 of the RS registers are dedicated to M1,2,3,4; 4 are dedicated to program storage; and 3 may be either memory or program storage. Long programs will abrogate M5,6,7 in descending order. • Digit encoding The 4-bit digits of a number use a 1242 bit-weight decimal encoding, not standard BCD [SCX.7]. The 2nd '2' bit will be referred to as the 'W' bit to distinguish them. As with BCD encoding, the binary sum of two 1242 digits requires correction (normalisation) to the 1242 encoding. This is performed in DX. • Negative numbers For registers RA,B,T,Mn, the stored value is a signed number in 9'scomplement format. The 16th digit (ØD15) will be 9 for negative and 0 for positive. Using 9's-complement format results in there being both a positive zero and a negative zero, this is consequential for user programming (see JUMP instruction). For RD, the stored value remains as a positive magnitude but with flag RDNEG indicating the sign (negative=1). When needed for arithmetic, the RD bitstream is inverted or not, in accordance with the sign, by an XNOR gate [C414.5,C413.5,6] to become bitstream RDCOMP. Realign-Rotate Process The register layer is not entirely free of constraints from the channel layer. The bits presented to the register layer are not consistent over the entire ØB period. However, they are guaranteed to be aligned and stable across the 1-edge of ØB when the register layer bit transitions occur. • Conundrum As mentioned in the channel layer commentary, an operation involving two registers can be performed at the 1-edge of ØB where the register bits are mutually stable. 13 In storing the result of such an inter-operation however, a problem arises. The current register-bit period has now ended, so injecting a result value into the register channel will place it in a subsequent bit period where it will be out of alignment with the other registers. • Realignment Resolving this involves a process: • The bit-loop for up to 3 registers is extended from 16 to 17 digits by inserting a digit register (DX,DY,DN) into their path. • The number cycle is extended to 17 digits by assertion of PNCEXT. PNCEXT is a subset of the states of PM. • Now, during a number cycle, for the extended registers, bits are written to the delay line after the additional digit delay of DX,DY,DN. At the end of the number cycle all is well for these registers: though they were written into a later absolute location in the delay line, due to the extended number cycle the digit timing periods were also delayed, so the data and the timing remain in alignment. • Unfortunately, the registers which were not extended are now out of alignment with the extended registers and the timing: they have effectively been rotated down one digit. The solution to this is to keep doing it: the register and number cycle extension is maintained for enough number cycles to total 16, at the completion of which the out-of-alignment registers will have rotated into alignment with the extended registers. The extensions can now be removed. • Tracking with CK The extended number cycles are tracked by counter CK. Before PM is released to execute a procedure, CK is sent home during S1 [B307.5]. During the procedure execution, for each extended number cycle, CK is incremented [B206.9]. Before a PM procedure ends, state P03 or P04 is entered. This state loops until CK returns to home [D316.10], to complete 16 extended cycles. • Realign example An example of this is the MEM-IN procedure [SCX.5]. In P02, RD is added to RS. RS is extended with DX, RD is extended with DN and the number cycle extended, for one number cycle through P02. After P02, P03 is executed in a loop for 15 number cycles with the extensions continued. 14 Digits There are six 4-bit shift registers used for intermediate storage of digits. 'Digit' here is 4-bits, but not just digits of a number. Functions are also encoded and stored in 4-bit digits. The digits are DX, DY, DN, DM, DF & DFp. DX, DY & DN may be inserted in number-register bit-loops for extension to 17 digits but they additionally provide facilities distinct to each. DX Digit DX is the arithmetic adder, and is an extension digit, usually for RA. It has two bit-stream inputs for the operands, a bit-stream sum output and a carry output. DX adds the two input bitstreams and performs sum correction for the 124W encoding. • Adder The adder is formed by the gates between the A.W, B.W and X.4 flipflops. The operand half-adder (XOR) is formed from [B215.6,B216.3, B212.5]. The carry half-adder is [213.6,212.6,wired-NORN]. • Normalisation In processing the operand bitstreams, the adder performs a binary addition of two 124W-format digits from the DXa and DXb inputs. The sum however, is not in 124W format, so must be corrected - normalised to 124W. The scheme for doing this normalisation is to wait till the end of the digit period when the lower 3 bits of the binary sum have been formed and stored in the DX flip-flops (the sum W bit has not yet been formed due to the adder being located between the 3rd and 4th bits). In the next bitperiod (ØB0), this state is assessed by combinatorial logic and appropriate corrections applied to the bits of the digit on the shift at the end of ØB0. [B112.1,B212.11,B214.11]. DY Digit DY can increment a digit, and is an extension digit, usually for RB. The increment facility is used in multiplication for reducing the multiplier digits, and in division and square-root for building quotient digits. • Increment The flip-flop [C103.4] functions as a carry flag. Incrementing the digit value in DY starts with setting this carry flag for the first bit of the digit [C205.9,11]. The carry is added to the bitstream in the XOR formed with [C203.3,5,etc.]. The carry persists until the operand bit from the bitstream is 0, at which point the carry is cleared [C103.6]. • Normalisation As the DY data value is 124W encoded, normalisation of the sum as in DX is also required here. However, because the sum is following a known sequence - to wit, that of incrementing - a simplified normalisation scheme can be employed: the only situation where normalisation is necessary is when 4 is incremented to 5 - the 0b0101 sum must be corrected to 0b1011. This correction is accomplished by suppressing the bit shift of the 3 lower bits of DY for the first bit of the subsequent digit period [C202.3]. 1 goes out for the 1-bit, while the 0b101 4,2,1 bit sequence is effectively 15 shifted up 1 bit to the W,4,2 positions. The net result is 0b1011 is shifted out as the sum. DN Digit DN holds an entered numeral, and is an extension digit, usually for RD. It may be loaded in parallel from the keyboard or serially from program storage. DM Digit DM stores a 124W-format decimal numeral received either from the keyboard or program store to indicate the currently-selected memory register. DF & DFp Digits • DF DF holds a code for the function being performed. Like DN, It may be loaded in parallel from the keyboard or serially from program storage. • DFp DFp contains the function code of the most recent prior function executed. • Function Codes Function codes are a 4-bit hex value [SCX.7]. 16 Counters SR16-Type Counters There are five 4-bit counters in the system: ØDC Timing Digit Counter DPC Decimal Point Counter CJ Multi-use utility counter CK Multi-use utility counter SPd Program Counter - digit portion All these counters are formed as a shift register ring with feedback which - unmodified produces a full 16-state sequence as shown in the table below. These will be referred to as SR16-type counters. The values in the table derive from bit weights 8,4,2,1 applied first-tolast to the shift register flip-flops. The table shows the count arbitrarily starting with value 0. SR16-type Counter Sequence Count: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Value: 0 8 4 A 5 2 9 C 6 B D E F 7 3 1 Note these are not common switch-tail ring counters. The point of using the SR16 design was presumably that it is synchronous, provides full state-utilisation of the flip-flops, but requires far less state logic than a 4-bit synchronous binary counter. • Home state None of these counters have an explicit reset input. Instead, for those necessary, they are gated to clock to some home value and then stopped. This home state may be deemed to be the beginning of the count cycle. The home value is not the same for all the counters - the reason for the lack of consistency being unapparent. DPC - Decimal Point Counter DPC maintains the user-selected position of the decimal point in the display. • Sequence The SR16 sequence is modified to 15 states: [31084A529C6BDE7] 0xF is absent from the sequence. • Home state When DPC=3 the output DP is asserted, activating the DP cathodes of the Nixies. • Operation DPC is continuously active, incrementing at each digit transition except ØD15 [B206.3]. As a 15-state counter it thus maintains synchronism with the 16-digit number-cycle. For example, if DPC=3 during ØD5, the DP of the 5th LSD Nixie is illuminated. As the Nixies are right-side DP, there are then 4 fractional digits in the display. • Initial At power-on, DPC is set to value 6 at the beginning of number cycles 17 (ØB0 of ØD0) by the pulses of INITP. This determines the initial startup position of the DP and corresponds to 4 fractional digits. • DP shift down To shift the selected DP position down, DPC will receive an extra increment during a count loop. In subsequent loop cycles then, DPC=3 will occur one digit earlier. The additional increment is performed at ØD15 [B205.3]. • DP shift up To shift the selected DP position up, one increment of DPC will be inhibited during a count loop. Subsequently, DPC=3 will occur one digit later. The increment at ØD0 is inhibited [B306.3]. • Thousands marks With thousands input DPCTH=1, DP=1 when DPC=8,5,C,D as well as when DPC=3. • Units digit An additional output, UNITØD, asserts when DPC=7, which is one digit period prior to DPC=3. This marks the digit period when the units digit is being processed (is output from the register bit-streams). CJ - Utility Counter Multi-use utility counter. • Sequence CJ follows the full SR16 count sequence. [31084A529C6BDEF7] • Home state In states PM=0bx0xx0, CJ is set to 3: CJ is incremented till stopped by CJ=3 [B301.6]. • Serial load With SM.1=1, CJ is serially loaded from RPF [B403.10]. The counter feedback is suppressed during the load. • Uses Number-entry, zero-blanking, CHECK mode function display, procedure loop counter. CK - Utility Counter Multi-use utility counter. • Sequence CK follows the full SR16 count sequence: [F731084A529C6BDE] • Home state During S1, CK is set to 0xF. B209.6=1 when CK≠0xF. With SM.1=1 and B209.6=1, CK is incremented on each digit [B208.6]. When CK=0xF, B209.6 is set 0, disabling the incrementing. • Output DPCTH DPCTH=1 when CK=0xE or CK=0xF. • Uses Thousands marks, register realign-rotate. 18 Flags There are a dozen flip-flops in the design serving as binary flags. A number of these flags are as individuals shared for multiple uses where the uses do not overlap in time. These flags are given a base name of µa along with additional names descriptive of the specific uses. For flags with a single use, most are not mentioned in this section, rather being described in context in an according section. µA Flag: SST, PBRD, PQPA • SST Supervisor Start. See EXEC Flag [32]. • PBRD Blank Rounding Digits. See Zero-Blanking [21]. • PQPA Square-root Pair-Aligned. See SQUARE-ROOT [27]. µB Flag: SNML, PNEG • SNML See DIGIT [36]. • PNEG During arithmetic procedures PNEG tracks the sign of the result. It is manipulated by the following: • Operand sign capture: During P0A, RA is assessed and PNEG set 1 if RA is negative [D208.5], as indicated by the MSB. • Result sign capture: During P06, RA is assessed for negative [D205.5,6]. See ADD/SUBTRACT [25]. • Result sign tracking: During P16, PNEG is toggled if RD is negative [D115.6]. µC Flag: PNEWN2, PPHE • PNEWN2 Operand Management. For an operation which produces a semantically new number, this flag carries indication over the idle period to then set PNEWN. PNEWN2 is cleared 0 in P17 at completion of an arithmetic operation [D110.7,9]. PNEWN2 is set 1 at the end of P0A during a recall operation (MEM-OUT, KTREAD, REVERSE) [D109.8,D108.11]. PNEWN2 is set 1 during intermediate binary arithmetic operations (not completed by the '=' key) [D109.3]. At the beginning of P0A, if PNEWN2=1 then PNEWN is set 1 [D111.6,D108.1], that is, PNEWN picks up the PNEWN2=1 status from the previous procedure. • PPHE Phase End. See SQUARE-ROOT [27]. 19 µD Flag: RDD>0, PPH2 • RDD>0 RD Digit is greater than 0. Set 1 at the end of a digit period if the digit which has just exited RD is not 0. An illuminated zero (0b1000) is recognised as 0. • PPH2 Phase 2. See SQUARE-ROOT [27]. µS Flag: SPARM, SSKIP • SPARM Program Parameter. When in LEARN Mode, SPARM=1 indicates a STOP instruction for parameter entry needs to be entered in the program store. See LEARN Mode [34]. • SSKIP Skip Instructions. During program execution (AUTO Mode), SSKIP=1 indicates instructions are to be skipped, as opposed to performed (SSKIP=0). See JUMP [36]. µY Flag: DY.W, PDPE DY is not needed during number entry, allowing the W-bit flip-flop of DY to be employed in secondary service as a flag: • PDPE Decimal Point Entered. Indicates the DP key has been pressed and numeral entry is now in the fractional digits. See NML-ENTRY [23]. µØ Flag: INTØ, PQRDØ, (RNDØ) This flag will assert for some portion of a number cycle. What portion is dependant on the PM procedure. • INTØ During P09,P08 & P18, asserts 1 for the integral digit periods. • PQRDØ Asserts 1 during the digit periods of the radicand in RB [B205.10]. See SQUARE-ROOT [27]. • RNDØ During P14, RNDØ asserts 1 for the digit periods from the rounding digit and up. See Rounding [22]. RDNEG Flag RDNEG is a sign flag for RD. RDNEG=1 indicates RD is to be treated as a negative number, even though it is not in complement form. • CS key Pressing the CS key toggles RDNEG [D405.7,D207.8]. • Copy from PNEG During P13 and P17, RDNEG is copied from the state of PNEG [D408.6,D405.5]. • Subtract Subtraction operations toggle RDNEG [D104.5]. 20 Procedure Layer PM - Procedure State Machine The Procedure State Machine sequences procedure execution. The current state is stored in binary in a register of 5 flip-flops. 25 of the 32 possible states are used. State values are presented as Pxx where xx is a 2-digit hex value. The decoding of PM states from binary is heavily optimised for necessity, with the consequence of being frequently obscuring of intention. For example, at some point in a procedure the algorithmic intention of a single state may be decoded by only 3 bits, leaving 2 bits of freedom and 4 possible states, but is acceptable because other algorithmic circumstance excludes 3 of the 4 states from occurring at this point or are unused states. State transition logic determines which state-register bits are to be cleared or set to get from the current state to a target state, though to note, the toggle facility of the JK flop-flops is used at times. For all commentary on PM, see the Table of PM States [38] and the PM State Graph [SCX.6]. Main Loop The various procedures are situated in a main execution loop. P09 is a wait state for PM when inactive PM loops in P09. PM is kicked out of P09-wait under 3 circumstances: - at the end of S1. As SM leaves S1 to head to S0, it kicks PM to either P08 [E408.6], or P0A [E408.6,E408.3]. - by assertion of KSCS (DP-Shift or Change-Sign). PM heads to P00 [D416.7,D209.2]. - by assertion of KCA or KCE (Clear operations). PM heads to P00 [D416.9,D209.1]. P0A unblanks RD so it is ready for use during a function procedure. At the end of a function procedure, the realign-rotate process is performed by P03 or P04. If exiting from P04, a dummy pass through P00 is performed. This pass is not necessary and is merely a consequence of minimising the state-transition logic. Execution proceeds to zeroblanking of RD, and PM enters P09 to wait for another kick from SM. DF is cleared of the function code (DF=0) in P01, or P00. Zero-blanking Blanking of leading zeroes in the display is accomplished by modifying zero digits in RD for the period spent in wait-and-display state P09. Zeroes which are to be illuminated are modified to value 0b1000 (not a value in the 124W decimal encoding set) while blanked zeroes remain as value 0. The zero-blanking modification of RD takes place in the main execution loop after the completion of function procedures, prior to going to P09. In consequence, RD must also be unblanked prior to function procedure execution after leaving P09. The zero-blanking algorithm is based on the equation: 16 digits = z(# of integral digits = 0) + n(# of integral digits > 0) + f(# of fractional digits) 21 The blanking and unblanking involves 3 states: • P01 RD is assessed in prepara