Schematic

Sony SOBAX 2500 Calculator: Schematic Appendix

Eleven pages of supporting drawings for the Sony 2500 schematic: timing, register maps and state diagrams.

Author: Brent Hilpert
Type: Schematic
Credit: Drawn and written by Brent Hilpert, Early Electronic Calculators, madrona.ca.

Channel Timing 0µS 1.6 3.2 4.8 6.4 8 9.6 11.2 12.8 14.4 16.0 17.6 19.2 20.8 22.4 24 25.6 (625KHz) ØS ØS0 ØS1 ØS2 ØS3 ØS14 ØS15 ØB Register-Bit, Digit & Number Timing 0µS 100 200 300 400 500 640 780 820 960 1000 1100 1200 1300 1400 1500 0 100 (39KHz) ØB 0 1 2 3 (9.8KHz) ØB0 ØB3 ØB03 (610 Hz) ØD0 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 0 8 4 A 5 2 9 C 6 11 13 E F 7 3 1 0 6 B D E 7 3 1 0 8 4 A 5 2 9 C 6 6 Digit 0 => X Digit 0 illuminated ØEON UNITØD with 4 decimal places INTØD with 4 decimal places ØD.8J ØD.8K Note: Frequencies shown are approximate, may vary with unit and temperature. ØD.8 ØD.4 Unit 620173: ØS=631.74KHz, TNV=–5.71V @ 18.5C board F running in 175 Unit 620175: ØS=629.06KHz, TNV=–6.20V @ 18.5C ØS=629.18KHz, TNV=–6.18V @ – Sony SOBAX 2500 Calculator Section: Timing Block Diagram & Graph Page: A1 Rendition: Jun 22, 2025 ØD.2 ØD.1 DPC=n with 4 decimal places in display 6 Digit 0 X => DL Units Digit & DP illuminated Timing Block Diagram Coarse Phase Comparator Timing INIT 0µS 1.6 ∆Ø TNUPC COARSE PHASE COMPARATOR FINE TNUPF PHASE COMPARATOR ∆Ø 4.8 6.4 8 9.6 11.2 12.8 14.4 16.0 17.6 19.2 20.8 22.4 24 25.6 (625KHz) ØS Øn ADL SYNC CHANNEL 3.2 CHARGE PUMP TNV MASTER CLOCK 0 10 0 EON F305.9 ØS DLSYNC CHANNEL COUNTER ÷16 TNUPCp ØSn,ØB BIT COUNTER ÷4 Fine Phase Comparator Timing ØBn 0µS 1.6 DIGIT COUNTER ÷16 3.2 4.8 6.4 8 9.6 11.2 12.8 14.4 16.0 17.6 19.2 20.8 22.4 24 25.6 (625KHz) ØS ØDn Øn 0 10 14 0 INIT ØB3 DLSYNC ADL Synchronisation Sequence 0S Stage –1 Power Off ~ 0.5S 0 Power Up TNUPF ~ 2S 1 EON Capture 2 Channel Capture 3 Normal Operation Observed Normal Operation of ADL Sync Power 0µS 102 204 INIT ØB3•ØS10 TNRDY DLSYNC TNUPC TVN ØS Frequency Resolution 0V ~ –6V –10V low quick rise slow rise within & tracking target 6 ØS / EON 0.5 ØS / EON 0.5 ØS / ØD Sony SOBAX 2500 Calculator Section: Timing Block Diagram & ADL Sync Page: A2 Rendition: Jun 22, 2025 TNUPF jitter ± 1 Delay Line Timing 0µS 1.6 3.2 4.8 6.4 8 9.6 11.2 12.8 14.4 16.0 17.6 19.2 20.8 22.4 24 25.6 (625KHz) ØS ØSn 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 DLRCV T sync A D B M3 M4 M1 M2 M7 P5 M5 P7 M6 P6 P2 P3 P1 P14 T sync A D B M3 M4 M1 M2 M7 P5 M5 P7 M6 P6 P2 P3 P1 P4 DLa = f(d) P4 T sync A D B M3 M4 M1 M2 M7 P5 M5 P7 M6 P6 P2 P3 P1 P14 T sync A D B M3 M4 M1 M2 M7 P5 M5 P7 M6 P6 P2 P3 P1 DLb P1 P4 (T) sync A D B M3 M4 M1 M2 M7 P5 M5 P7 M6 P6 P2 P3 P1 P14 (T) sync A D B M3 M4 M1 M2 M7 P5 M5 P7 M6 P6 P2 P3 RT T[b-2] T[b-1] T[b] RA A[b-1] A[b] A[b+1] RD D[b-1] D[b] D[b+1] RB B[b-1] B[b] B[b+1] RS=RM2 M2[b-1] M2[b] M2[b+1] (RS=RM2) F409.4 T[b-1] X[b-1] RTw T[b] X[b] 0 0 X[b+1] RSc P3 P1 P4 (T) - (A (D) (B) M3 M4 M1 M2 M7 P5 M5 P7 M6 P6 P2 P3 P1 P4 (T) - (A) (D) (B) M3 M4 M1 M2 M7 P5 M5 P7 M6 P6 P2 RSd P2 P3 P1 P4 (T) - (A (D) (B) M3 M4 M1 M2 M7 P5 M5 P7 M6 P6 P2 P3 P1 P4 (T) - (A (D) (B) M3 M4 M1 M2 M7 P5 M5 P7 M6 P6 DLINJ P2 P3 P1 P4 T ØB0 A D B M3 M4 M1 M2 M7 P5 M5 P7 M6 P6 P2 P3 P1 P4 T ØB0 A D B M3 M4 M1 M2 M7 P5 M5 P7 M6 P6 ØB Sony SOBAX 2500 Calculator Section: Delay Line Timing Page: A3 Rendition: Jun 22, 2025 Delay-Line Storage State during ØS14 of ØB3 of ØD15 and basic bit paths during idle DLap P4 15 W DLRCV ∂ DLINJ DLa T 15 W 1023 DLb P4 15 W 1022 RSc P1 15 W 1021 RSd P3 15 W 1020 P3 P2 M6 M7 M5 M2 M1 M4 M3 B D A 15 15 15 15 15 15 15 15 15 15 15 15 ∂ W W W W W W W W W W W W 1020 1008 S 15 W 10ss ss Times shown for ØS=625KHz. RB D 15 W 1014 13 A 15 W 1013 12 1020 bits (1632–0.5) µS RS B 15 W 1015 14 Acoustic Delay Line B D A T P4 P1 P3 P2 M6 M7 M5 M2 M1 M4 M3 B 988 more bits 0 0 0 ∂ 0 0 0 0 0 0 0 0 0 0 0 0 0 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 16 1 bit 16 bits 1.6µS 25.6µS RD RA RT T 15 4 RTw 0 DXa.W – D 15 W DXb.W D 15 4 DX.4 D 15 2 DX.2 D 15 1 DX.1 D 14 W DD.W D 14 4 DD.4 D 14 2 DD.2 D 14 1 DD.1 Sony SOBAX 2500 Calculator Section: Delay Line Organisation Page: A4 Rendition: Jun 22, 2025 <register> = A,B,C,D,M1,M2,M3,M4,M5,M6,M7,P1,P2,P3,P4 = 0 (LSD) … 15 (MSD) <digit> = 1, 2, 4, W <bit> ∂ = Sync Marker D 0 1 2 A 0 ∂ 1 1 0 EDIT: ––SPC S0 •SST KSCS MANUAL AUTO LEARN LIST EDIT SPARM S7 S5 RP[SPC]=>DF,DN ++SPC 0x8=>RP[SPC] ++SPC SPARM=0 S7 DF,DN=>RP[SPC] ++SPC S5 RP[SPC]=>DF,DN ++SPC DF=>CJ S6 DN=>DM 0–>SNML,SMSET S6 9=>RD[DF] or DN=>RD[0] S2 0=>DF 0=>EXEC EXEC SNML•SMSET S0 EXEC~ P09~ DN=0~ DN=0 S6 DF=D,M: 1–>SNML DF=M: 1–>SMSET SNML: 0–>SNML,SMSET D,M,J S1 PM Sony SOBAX 2500 Calculator Section: SM State Graph Page: A5 Rendition: Jun 22, 2025 CK=0xF PM S7 DF,DN=>RP[SPC] ++SPC DF=>CJ Unblank RD NUMNML~ NML-ENTRY S1, KSCS, KCA,KCE, KTREAD SM 09 KCA,KCE 08 W=0: 0=>RD 18 <<RD, DN=>RD[i] ACALL 0A KSCS MEM-CLR, MEM-IN 02 00 00 MEM-OUT MCLR: 0=>RS MIN: RS+RD=>RS CS: RDNEG~=>RDNEG DP SHIFT: ++/–– DPC 15 03 Realign Rotate 14 Z-Blank RD, 0=>EXEC 0=>F, Z-Blank Assess 0=>F dummy state 11 01 00 12 RS=>RA 13 RA=>RD, RD=>RA,RB 04 Realign Rotate KEQ~ 00 16-DIGIT NUMBER CYCLE EXTENDED 17-DIGIT NUMBER CYCLE Sony SOBAX 2500 Calculator Section: PM State Graph - Main Page: A6 Rendition: Jun 22, 2025 Realign Rotate KTON: RT+RD=>RT 03 02 15 INIT KEQ KTREAD 12 RT=>RA REVERSE 12 PNEWN=0: RB=>RA PNEWN=1: nil Realign Rotate ABS(RA)=>RD, PNEG=>RDNEG, DF=>DFp 04 17 ARETURN ACALL QUEUE-OP 12 ADD/SUBTRACT MULTIPLY DIVIDE SQUARE-ROOT RD=>RA 16 RA=>RB 0=>RA HOME=>CJ 16 RA=>RB 0=>RA HOME=>CJ 1E RA>> RB>>–DY ––CJ 1C RA<<RB<<DY ––CJ DY=9 12 RD=>RA 0=>RD 16 RA=>RB 0=>RA HOME=>CJ 1C RA<<RB<<DY ––CJ 1D RA<<RB ––RD, <<RD ––CJ 0F (1,2)+RD=>RD 0D RA–RD=>RA RA>0: ++DY 1,2 DY≠9 DY=9 DY≠9 06 RA+RD=>RA 0E RD+RA=>RA ++DY 0D RA–RD=>RA RA>0: ++DY RA<0 07 dummy state ARETURN Sony SOBAX 2500 Calculator Section: PM State Graph - Arithmetic Page: A7 Rendition: Jun 22, 2025 0C dummy state ROUND(RB) =>RA 15 14 PPH2•CJHOME RA+RD=>RA PPH2•CJHOME RA<0 0C RA+RD=>RA PPH2•CJHOME Bit Codes IC Pinouts Numeral W421 Function 8421 Function 8421 blank-0 0000 null,EOP 0000 + 1110 1 0001 (not used) 0001 0110 2 0010 D 0010 – × 3 0011 J 0011 ÷ 1111 4 0100 M IN 0100 = 1001 0101 M CLR 0101 √ 1011 0110 – × 0110 R 1101 0111 0111 M 1010 illum-0 1000 S 1000 M IN 0100 function 1001 = 1001 M OUT 1100 501 0111 1010 M 1010 M CLR 0101 5 1011 √ 1011 S 1000 6 1100 M OUT 1100 D 0010 7 1101 R 1101 J 0011 8 1110 + 1110 null,EOP 0000 9 1111 ÷ 1111 (not used) 0001 502 503 504 IC technology is current-sinking. Inputs are DTL/TTL. Gate outputs are open-collector. Flip-flop outputs have ~ 1.1K pull-up resistors. 1 GND 14 1 GND 14 1 GND 14 1 Øa 2 +4V 13 2 +4V 13 2 +4V 13 2 Ga 3 12 3 12 3 12 3 Qa~ Inferred for 504 flip-flops: G = Gate Input Ø = Clock Input G=1 enables the JK inputs. The outputs transition on +edge of Ø. 4 11 4 11 4 11 4 Qa 5 10 5 10 5 10 5 Ja 6 9 6 9 6 9 6 Ka 7 8 7 8 7 8 7 Kb GND 14 Ja Qa Ga Øa Ka Qa~ +4V 13 Øb 12 Gb 11 Jb Qb Gb Øb Kb Qb~ Qb~ Qb 9 Jb 8 The W bit has a weight of 2. 504 Substitute No Async S/R (implemented/used 2025 Feb) Discrete Gate Substitute (implemented/used 2024 Nov) 1K 2N 5209 470 3.57K 2N 3904 Slow. Used a few times at number cycle level. J G Ø K 2N 3904 Tailored 3F309.5 for pulse capacitor drive. 10K J G Ø Higher speed. Based on SN3900. 1.4K 2.2K 2N 3904 2N 3904 K 5 6 2 5 14 14 4081 7 4027 7 7 6 4 1 3 2 6 1 8 8 11 9 5 3 9 10 10 12 13 12 7 4 13 11 11 12 ? S J Q 1 4 2 3 15 9 14 10 Q Ø K Q~ R Q~ S J Q 1.1K Q 4 Q Ø K R Q~ 4.7K Q~ 4.7K 1.1K 1.1K 3 Q~ 4.7K 2.4K 9 Sony SOBAX 2500 Calculator Section: Bit Codes & IC Pinouts Page: A8 Rendition: Jun 22, 2025 REʼd from die observation. Some presumptions regarding input transistor. ? ~0.5 µS delay from input –edge to output +edge. 10 Q Q~ 10 Board Layout Board Test Points TB1 TB44 1 2 3 4 16 comp: solder: 15 02 NB2 NB1 NB44 NB43 Nb2 Nb1 01 Nb44 Nb43 B=ABCDEF b=abcdef Board F Test Points TF44 38 36 15 9 TF6 Tf6 Tf2 Tf8 Tf1 Tf9 Tf7 1-539-224-12 Tf10 Tf4 Tf5 3 Tf3 4 02 • Note: ICs on Board A are oriented differently from the other boards. Sony SOBAX 2500 Calculator Section: Board Layout & Test Points Page: A9 Rendition: Jun 22, 2025 01 B 47 DXCA~ 46 DX B.W~ 45 DX B.W 44 DX A.W~ 43 DX A.W 42 DX.4 41 DX.4~ 40 DX.2~ 39 38 DX.2 37 36 35 34 DX.24.G 33 32 DX.1~ 31 B210.6 30 CK.1~ 29 CK.8 28 CK.8~ 27 26 PM.10~ 25 CK.2 24 CK.1 23 CK.1248.G 22 DPC.8 21 20 DPC.8~ 19 DPC.4~ 18 DPC.4 17 DPC.2~ 16 DPC.2 15 DPC.1 14 DPC.1~ 13 DPC.1248.G 12 ØDEXT 11 10 INTØ 9 CJ.8~ 8 CJ.1248.G 7 CJ.8 6 CJ.4 5 CJ.2 4 CJ.1 3 CJ.1~ 2 CJ enable ++/digit 1 CJHOME C 47 ØB01~ 46 ØB.G 45 ØB01 44 43 42 41 40 39 38 37 36 35 34 RAw 33 32 P0F 31 30 29 28 27 (Px2+x3+x6+x7)~ 26 25 24 23 22 21 20 19 18 17 P1C~ 16 15 14 P1E~ 13 12 P1E 11 OVF 10 DYINC 9 DYINC~ 8 OVF~ 7 DY.1 6 DY.1~ 5 DY.124.G 4 DY.4~ 3 DYw~ 2 DY.4 1 DY.W.G D 47 46 45 44 43 42 41 40 PM.1~ 39 P18~ 38 PM.2~ 37 PM.10 36 PM.8 35 PM.4 34 PM.4~ 33 SSKIP~ 32 31 30 29 28 27 26 25 24 23 22 21 20 P0A 19 RDNEG 18 RDNEG.J 17 16 15 14 D208.9 13 DFp.1 12 DFp.1~ 11 DFp.1248.G 10 9 8 7 6 DF.8 5 4 DF.4 3 DF.2 2 DF.1248.G 1 DF.1 E 47 DM.1 46 DM.1~ 45 DM.124W.G 44 43 DMw~ 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 ØS15 26 25 24 23 22 SPr.1 21 SPr.1~ 20 SPr.4 19 SPr.4~ 18 SPr.124.G 17 SPd.1~ 16 SPd.1 15 SPd.1248.G 14 13 SM.4~ 12 SPd.8.K 11 SM.1 10 SM.2 9 SM.2~ 8 SMSET 7 SMSET~ 6 EXEC~ 5 DN.1~ 4 DN.124W.G 3 DN.2 2 DN.4 1 DN.W F 47 46 45 44 DLINJ 43 42 41 40 39 38 QF26.B 37 36 QF21.C 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 QF10.B 14 TNUPF~ 13 12 TNUPF 11 ADLRD 10 DLRCV 9 DLRCV~ 8 7 6 QF7.B 5 4 3 2 1 - Sony SOBAX 2500 Calculator Section: Connectors Page: A10 Rendition: Jun 22, 2025 Notes: • Italicised expressions are connections with no signal name in the schematic. • Bold-faced expressions are signal sources. b – 40 39 c40 GND 6 V+8 unreg 4 V+200 2 9 7 5 3 1 P14+15 PNCEXT MDR DXwb~ PM.4 B ØD0~ 44 43 9 ØD2~ 42 41 – ØD4~ 40 39 7 8~ 38 37 6 ØD11~ 36 35 5 – 34 33 4 OVF~ 32 31 3 – 30 29 2 – 28 27 1 – 26 25 0 ØB3 24 23 – ØD15~ 22 21 – DM=M1 20 19 – RDNEG 18 17 ØDEXT~ funct ind. 16 15 DP SPEXP 14 13 INIT~ SP1ST 12 11 KCHECK~ Ø B 10 9 Ø B V+4 8 7 V+4 5 GND 3 V+8 unreg 1 V+130 d V+4 44 43 GND (KCHECK•S6)~ 42 41 KCA~ e f GND 44 43 V+4 KCA~ 42 41 KF.1~ V+4 44 43 GND KF.1~ 42 41 KN.1 b39 40 39 (PFMC+RV)~ (PFMC+RV)~ 40 39 KF.2~ (KCHECK•S6)~ 40 39 KN.2 PDPE~ 38 37 SNML~ PDPE~ 38 37 PFRECALL~ P FRECALL~ 38 37 KF.4~ RPF~ 38 37 KN.4 e27 36 35 µY µY 36 35 e36 RPF~ 36 35 KF.8~ c35 36 35 KN.W RPF~ 34 33 EXEC KCHECK 34 33 PFSR~ PFSR~ 34 33 e34 d33 34 33 keyboard PNEWN~ 32 31 PNEWN DN 32 31 PNEWN PNEWN 32 31 KLEARN~ KCHECK~ 32 31 E X E C µ C 30 29 RDD=0 RDD=0 30 29 PNEWN~ PNEWN~ 30 29 µ C KMAN~ 30 29 DN µC~ 28 27 RDD>0 RDD>0 28 27 µC~ µC~ 28 27 SSKIP SSKIP 28 27 b36 µA 26 25 SM.1 YB 26 25 SNML SNML 26 25 SNML~ F44 26 25 SNML SM.1~ 24 23 µA~ µA~ 24 23 SNML~ µA 24 23 e24 d23 24 23 µA PFSR 22 21 INTØ~ INTØ~ 22 21 SM.1~ PFSR 22 21 e22 d21 22 21 KAUTO~ JA 20 19 CJHOME~ CJHOME~ 20 19 P1D JA 20 19 SM.1~ SM.1~ 20 19 P1D S6~ 18 17 (PM.4•PM.8•CJHOME)~ – 18 17 SM.4 (PM.4•PM.8•CJHOME)~ 18 17 S6~ S6~ 18 17 d14 IDLE~ 16 15 PNEDNE PNEDNE 16 15 VC~ VC~ 16 15 KSCS~ KSCS~ 16 15 SM.4 KSL~ 14 13 Nc14 Nb13 14 13 DY=0~ e17 14 13 (KSCS•SST)~ (KSCS•SST)~ 14 13 PNEDNE KSR~ 12 11 P08+0C P08+0C 12 11 PFCE KCE 12 11 PFCE PFCE 12 11 F42 KSCS 10 P18 8 MBR 6 KRØD 4 PM.4~ 2 A c GND 44 43 V+4 KRDWN~ 42 41 – P14+15 10 PNCEXT 8 D 6 DXwb~ 4 PM.4 2 9 7 5 3 1 – (P02+03)~ e9 RB PM.4~ C 9 44 43 ØD0 8~ 42 41 PM.8 7 40 39 CHGSGN~ 6 38 37 ØD11~ 5 36 35 PM.10 4 34 33 PM.2~ 3 32 31 PM.2 2 30 29 ØD0~ 1 28 27 PM.1~ 0 26 25 D26 YB 24 23 DXCA ØD15~ 22 21 ØD15 Q 20 19 ØB3 ØDEXT~ 18 17 D X funct ind. 16 15 ØB0 DY=0~ 14 13 C14 D P 12 11 DXwa~ INITP~ 10 9 XOVF ØD15•B3 8 7 ØB3~ P08+0C 10 (P02+03)~ 8 e9 6 KSCS 4 PM.4~ 2 9 7 5 3 1 IDLE~ IDLE~ 10 P18 P18 8 KEDIT KEDIT 6 MSETMAN~MSETMAN~ 4 F44 PM.4~ 2 D 9 7 5 3 1 d6, c5 RSwENB – D26 DXwb~ E OVF~ 44 43 P09~ P09~ 44 43 OVF~ PM.8 42 41 P13+17 P13+17 42 41 PM.8 PM.8~ 40 39 P1D~ P1D~ 40 39 PM.8~ PM.10~ 38 37 P0A~ P0A~ 38 37 PM.10~ PM.10 36 35(P01+05+07+11+13+17)~ (P01+05+07+11+13+17)~ 36 35 R S PM.2~ 34 33 E32 E32 34 33 CHGSGN~ PM.2 32 31 RBw PM.2 32 31 PM.1 PM.1 30 29 Px2+x3+x6+x7 Px2+x3+x6+x7 30 29 P02+03 PM.1~ 28 27 (Px0+x1)~ (Px0+x1)~ 28 27 KTREAD ØD0 26 25 RAw e3, B25 26 25 Y B DXCA 24 23 (PFSR~•SST•x)~ (PFSR~•SST•x)~ 24 23 – ØD15 22 21 ØD15~ – 22 21 INIT~ ØB3 20 19 RDNEG RDNEG 20 19 Q DX 18 17 R A MAR 18 17 DX ØB0 16 15 D16 C15 16 15 – B13 14 13 DY=8~ DY=8~ 14 13 – (PFEQ) DXwa~ 12 11 P16~ P16~ 12 11 E12 XOVF 10 9 (P13+17)~ (P13+17)~ 10 9 SM.2 ØB3~ 8 7 P11+16 P11+16 8 7 ØD15•B3 F401.10 44 43 – F302.9 42 41 – F302.10 40 39 – – 38 37 – F302.4 36 35 – F302.3 34 33 – – 32 31 – F403.3 30 29 – F404.9 28 27 – F405.10 26 25 F404.10 F404.3 24 23 F406.3 F305.9 22 21 F407.3 F305.10 20 19 – F405.3 18 17 – F406.10 16 15 – F305.3 14 13 – F305.4 12 11 – – 10 F408.9 8 F408.4 6 F409.3 4 F409.4 2 9 7 5 3 1 – F407.4 ØB~ F408.10 – F310.8 F OVF~ 44 43 F43 PM.10~ 42 41 P09~ ØD0~ 40 39 R S w KTON 38 37 R S PM.10 36 35 RT PM.2~ 34 33 RTw~ C33, D34 32 31 ØD0 P02+03 30 29 KF.8~ KTREAD 28 27 E ØS YB 26 25 F26 ØD15~ 24 23 ØS5 ØB3 22 21 ØS10 ØD15 20 19 ØS14 DX 18 17 ØS0 DM=M1 16 15 ØS4 S P E X P 14 13 SP1ST D11 12 11 INITP~ SM.2 10 9 Ø ØD15•B3 8 7 Ø d1, e26 44 43 E43 e11 42 41 KLEARN~ RSw 40 39 RDw~ R S 38 37 KCHECK~ RT 36 35 RD RTw~ 34 33 RB ØD0 32 31 RBw RAw 30 29 SM.1 E ØS 28 27 RSwENB E25 26 25 pwr off ØS5 24 23 pwr off ØS10 22 21 RA ØS14 20 19 ØB3 ØS0 18 17 ØD15•B3 INIT~ 16 15 ØS4 ØB0 14 13 GND INITP~ 12 11 GND Ø 10 9 V–10 Ø 8 7 V+4 ØB 6 5 ØB ØB 6 5 ØB ØB 6 5 ØB ØB 6 5 ØB ØB 6 5 ØB V+4 4 GND 2 3 V+4 1 GND V+4 4 GND 2 3 V+4 1 GND V+4 4 GND 2 3 V+4 1 GND V+4 4 GND 2 3 V+4 1 GND V+4 4 GND 2 3 V+4 1 GND Section Timing Signal TNRDY TNUPF TNUPC TNV INIT INITP PWROFFP Description Master timing and power-on initialisation. Channel slice clock, this is the master clock. Channel slice timing. The bits of the 15 main registers are interleaved in the Acoustic Delay Line by slicing each register-layer bit into 16 channels. The remaining slice is used for synchronizing the frequency of the master clock to the cycle time of the delay line. Register-layer bit clock bit. Bits of a digit. Digits of a number. During some calculation phases, the 16-digit cycle is extended one digit period by inserting another digit period between ØD11 and ØD12. The inserted period is ØDINS. Ready to start tuning process after power-on. Tune UP Fine. 1 enables slow charge of charge pump controlling master clock. Tune UP Coarse. 1 enables fast charge of charge pump controlling master clock. Tuning Voltage. Frequency control input to master clock. Initialisation. 1 when power is turned on, goes 0 after initialisation is complete. Initialisation pulses. A stream of pulses during initialisation. Power Off Pulse. KMAN KAUTO KLEARN KOPER KCHECK KEDIT~ KTON KTREAD KR54 KRDWN KRØD KCA KCE KSL KSR KSCS KDP KPS KF.1,2,4,8 KN.1,2,4,W The keyboard and encoders for numerals and functions. Manual mode. Execute program mode. Learn program mode. Operate mode. Program LIST or EDIT mode. Program EDIT mode. Tally mode on. Tally read. 5 up / 4 down rounding mode. Round down mode (truncate). Selected digit pulse for rounding. Clear all. Clear entry. Shift left. Shift right. Shift or change sign. Decimal point. Program step (S key). Encoded function keys. These are the same as DF.1,2,4,8. Encoded numeral keys. SM.1,2,4 S<n> EXEC OVF SST SNML SMSET SMSKIP SADDEOP S-Machine state register bits. S-Machine states {0,1,2,5,6,7}. Execution active. Overflow latch. Start Numeral expected. In MEM-SET operation. Skip instructions during program execution. Add an End-of-Program instruction (function code 0) into the program store. PM.1,2,4,8,10 P<2-hex> PNCEXT PF… PINFX PNEWN PNEWN2 PDPE PNEG PPHE,PPH2 PQPA PQRDØ P-Machine state register bits (hex). P-Machine states - 0::1F. States which extend the number cycle to 17 digits. Combinations of the function register DF and PM state. Infix operand management. A new number is in RD (first numeral has been entered). ØS ØSn ØB ØBn ØDn ØDEXT Keyboard Supervisor Procedure Section CJ Counter CK Counter DPC Counter CKHOME DPCTH UNITØD DP SP1ST SPEXP SPOVF SØDATPC RPØS Digits F & Fp Digit N Digit X Digit Y Digit M Misc. Flags Register DF.1,2,4,8 DFp.1,2,4,8 DN DN=0 DX DXCA DXOVF DY DYINC DY=0 DY=8 DM DM=M1 RMØS INTØ RNDØ RDD=0,RDD>0 RDNEG RA RB RD RS DP entered during number entry. Negation tracking flag during procedure execution. Phase End and Phase 2 flags for M,D,Q. Pair Aligned for square root. Square root, radicand digits of RB during number cycle. RT Channel Rendition: Jun 22, 2025 CJHOME SPC Counter Sony SOBAX 2500 Calculator Section: Signal Names Page: A11 Signal Description Utility counter Utility counter: duty cycle dimming for thousands markers, realign-rotate loop counter Decimal point position counter. The current ØD is the units digit. Signal to the display to turn on the decimal point. The program counter. This must select one of the 7 program registers in the E group as well as track a position within the selected register. Program at beginning. Program memory is expanding into the M7,6,5. ØD scanning is at the program counter location. Timing slice for selecting 1 of 7 program registers in the E register group. 4-bit Function registers. Function keystrokes and program instruction to be executed. Previous function. 4-bit register for numeric keystrokes. Bit stream output. 4-bit register for arithmetic. Bit stream from the X register. Carry Flag. 4-bit register, incrementer. Bitstream output. DY performing an increment. 4-bit register to indicate which memory is currently selected. Bit stream from the M register. Memory 1 is selected. Timing slice for selecting 1 of 7 memory registers in the S register group. Goes high during digits which are part of the integral portion of the number. Assessment of last RD digit. The number in the RD register is negative. 15 16-digit registers for numbers and program instructions. Bit stream from the A register - accumulator. Bit stream from the B register - previous operand. Bit stream from the D register - current / displayed operand. During idle, illuminated zeroes are encoded as 1000, blanked zeroes remain 0000. 11 16-digit registers shared between the 7 memories and program instructions. 4 of these registers are reserved for memories 1,2,3 and 4. 4 are reserved for program instructions. The remaining 3 are shared by memories 5,6,7 and program instructions in reverse overlapping order. Thus a long program will cut into memory 7, then memory 6 then 5. The maximum length of a program is (4+3)*16=112 instructions (functions). Bit stream from the Tally register. RAw RBw RDw RTw RSw RSwENB Data selector for bit-stream into the A register. RACOMP RDCOMP RP Complementary form of bit stream from the A register in accordance with PNEG. Complementary form of bit stream from the D register in accordance with RDNEG. Bit stream from the S register for program instruction purposes. ADLINJ ADLRD Data bits for injection to the ADL. Reformed read pulses from the ADL. Enable input to the currently selected register in the S register group.