Schematic

Sharp Compet 17 Calculator: Reverse-Engineered Schematic

A 17-page schematic of the Sharp Compet 17 of 1968: MSI MOS logic and multiplexed Hitachi CD-81 Nixies.

Author: Brent Hilpert
Type: Schematic
Credit: Drawn and written by Brent Hilpert, Early Electronic Calculators, madrona.ca.

Sharp Compet 17 Calculator Contents Section Sharp Compet 17 Calculator Section: Title and Contents Page: 1 Rendition: 2020 May 20 Page Title & Contents (this page) 1 Notes, Gate Identification & Signal Names 2 Block Diagram 3 Timing 4 Keyboard & P-Cycle Generator 5 Control (Major Operation Flags) 6 Control (F, J & G Flags) 7 Control (State Matrix) 8 Control (Outputs) 9 Registers 10 Arithmetic 11 Decimal Point Counters 12 Display 13 Power Supply 14 Timing Diagram 15 IC Pinouts & Gate Construction 16 Physical Layout and Connectors 17 This schematic has been derived through reverse engineering. This is not the manufacter’s schematic, nor is it based on the manufacturer’s schematic. Notes ♦ Gate symbols and signal names are presented in accordance with: logic 1 = GND logic 0 = V–24 Signal Names Section Timing Signal Ø… Ø1 Ø2 Ø3 ØB… ØD… ØnB1+3 Øn(D16•B8•1) Description Master timing. Master clock, data capture phase. Master clock, output transition phase. Master clock, a third phase used by some flip-flops. Bit timing. Digit timing (4 bits constitutes a digit). Used for triggering digit timing and display latch. Capture pulse at the end of each full number cycle. Keyboard K… P The keyboard and numeral encoder. Indicates a number cycle during which processing occurs. Control S…, C… C D F, G, J, M, S S… IDLE CX… CW… CM… CPX… CPW… CPY… The state machine. Multiply or divide operation pending. Divide operation pending. Assorted state flags. Assorted internal state signals. 1 during display and simple operations, 0 during multi-cycle operations. Outputs from control to the X register. “ W register. “ M register. “ PX decimal point counter. “ PW decimal point counter. “ PY digit counter. X Register X… XC1,2,4,8 CARRY The operand being displayed. Arithmetic is also incorporated in this register. BCD numerals on their way to the display. Carry indication to control. W Register W The second operand. M Register M The user memory. PX Counter PX PXI Ring counter to hold the place of the decimal point for the X operand. Signal to the display to turn on the decimal point at the appropriate time. PW Counter PW Ring counter to hold the place of the decimal point for the W operand. PY Counter PY Ring counter used during multiply and divide operations. Ncp ♦ The symol denotes a physical connector pin, where c=connector and p=pin. Solid black end is the male side of the connector. White end is the female side of the connector. ♦ connection between different sections. connection limited to same section. Arrows indicate direction of signal or energy flow. ♦ The symbol without an additional label denotes VDD (–24V). ♦ Capacitance in microfarads unless otherwise indicated. ♦ This schematic includes the user memory which is not present in the Compet 17 model. Components marked with “§” are not present in the Compet 17. ♦ These drawings based on a Model CS-17C unit with Serial No. 810591T. Log ♦ 2000 Jul: Initial drawing / bhilpert. ♦ 2004 Oct: Signals on the remote connector (NR) elaborated further. Switches and notes about single-cycle control of P added. ♦ 2017 May: Format updates. Question of pins on IC 5-6 noted. Gate Identification Gates and logic elements are identified by symbols of the following form: Gate ID 1-n 2-n 3-n 4-n 5-n 6-n 7-n M-n Description inverter in µPD1 IC 2 by 2 AND–OR gate in µPD2 IC 4-input AND gate in µPD3 IC flip-flop in µPD4 IC 4-bit shift register in µPD5 IC 8-bit shift register in µPD6 IC MOSFET in µPD7 IC MOSFET discrete Discrete gates have no distinguishing identifier but their inputs are identified with a label indicating the location of the diode which implements it: Label g .p dn Description diode in TDA001 or TDA002 package g at pin p discrete diode ♦ A lowercase “n” in a symbol name indicates the logical NOT operation. ♦ The character “ • ” in a symbol name indicates the logical AND operation. ♦ The character “+” in a symbol name indicates the logical OR operation. P-Cycles and Manual Control of Operations Two switches can be plugged into the remote connector (NR) to provide the ability to single-step through the major state cycles of an operation. See the Keyboard page for wiring of the switches. A P-cycle is a full number cycle during which processing occurs and is indicated by the P signal. Major state transitions occur at the end of a P-cycle. Simple user operations such as numeral entry generate a single P-cycle without sending IDLE to 0. More complex operations requiring multiple number cycles generate a first P-cycle and send IDLE to 0. Multiple P-cycles are subsequently generated until the operation is complete, at which time IDLE returns to 1. See the IC Pinouts and Gate Construction page for more about the integrated circuits. See the Physical Layout and Connectors page for more about IC and gate location. Sharp Compet 17 Calculator Section: Notes Page: 2 Rendition: 2020 May 20 Enabling the MANUAL switch disables the automatic generation of P-cycles for multi-cycle operations. In this mode, once a multi-cycle operation has been initiated, each press of the STEP pushbutton generates a single P-cycle, so the operation can be stepped through one P-cycle at a time. Timing Power Supply IDLE Ø1 Ø2 Ø3 ØBn bit timing ØDn digit timing M Flag S Flag VCL V–24 V+90D V+90 V+190 logic supplies display supplies KCLR, KCE, KAS, KS, KMD, KD, KRC, KDP, KMC, KMR, KMAS, KMS Keyboard C Flag D Flag F Flag J Flag State Sequencing G Flag Control P Cycle Generator K0…K9 Numeral Encoder P Arithmetic Outputs X Outputs W Outputs CX… CA… CB… CWW CWX CWØ S1 M Outputs PY Outputs KMC CMX CMØ CPYPX S6 PW Outputs PX Outputs KNDP CSUB C T C CSUM CARRY KNUM X W X Arithmetic (BCD serial adder, 4 bits) M PY Ring Counter X Register (displayed operand, 48 bits) CPW… PY PW Ring Counter W CPX… PW W Register (2nd operand, 48 bits) PX Decimal Point (PX) Ring Counter M Register (user memory, 48 bits) PXI XC1 XC2 XC4 XC8 Sharp Compet 17 Calculator Section: Block Diagram Page: 3 Rendition: 2020 May 20 Display Latch (4 bits) 1-of-10 Decoder and Drivers 12 Nixie Displays 000987654321. Decimal Point Driver 7 2K 70K 200K 2K 100 pF 100pF 100pF 50K 1-1 D 5 ØnB1+3 NK7 2SC458 200 pF NL12 1K NR7 7 200 pF ØnB4 Ø2 ØnB1+3 NL10 ØnB4 ØnB1+3 Ø2 8 6 ØC ØT 6 8 6 ØnD2 ØnD3 NL40 NL38 5-2 ØC ØT D1 ØnD5 B 4 B Q2 3 B Q3 2 B Q4 1 ØnD6 NL44 ØC ØT ØnD7 ØnD8 ØnD9 B 4 B Q2 3 B Q3 2 B Q4 1 Q1 5-3 ØnD4 NL42 Q1 Ø3 NK39 NR39 Ø1 8 7 3K 01 01 01 D1 2SA549 50K ØnD10 NL11 05 05 05 05 04 04 04 04 03 03 03 03 03 ØnD2 ØnD3 ØnD4 ØnD5 ØnD6 ØnD7 ØnD8 ØnD9 ØnD10 ØnD11 ØnD12 ØnD11 ØnD12 NL9 ØnD13 NL7 ØnD13 V 11 S 1 1-1 C 4 C Q2 3 C Q3 2 C Q4 1 7 NL17 Q1 5-5 ØT 2SA549 40K D1 ØC NL14 5K 7 6 5-1 Ø1 1K 2SC458 8 B 4 B Q2 3 B Q3 2 B Q4 1 Q1 D1 2SA549 ØnB4 1K 7 8 1-1 ØB1 NK12 NR12 4 Ø3 ØnB4 ØnB1+3 1K ØnB1+3 8 6 5-4 ØC ØT C 4 C Q2 3 D Q3 2 D Q4 1 02 02 02 Q1 2SC458 100K NL19 D1 c 7 1-2 C 5 NL6 d ØD1416 2SC458 NL5 ØB2 ØnD16 5K 2SC458 NL21 9 1-1 D 3 ØB4 ØnB4 15K NL15 ØnD1 NL16 NL23 10 1-1 C 2 NL8 ØB8 ØnD1 ØnD11 ØnD12 Sharp Compet 17 Calculator Section: Timing Page: 4 Rendition: 2020 May 20 10 1-6 D 2 ØD1 1-6 D 3 ØD11 1-6 D 4 ØD12 D 5 ØD13 ØnB8 ØnD13 9 8 7 1-6 Ø1 ØnB8 ØnD16 2SC458 E 5K Øn(D16•B8•1) (CPC) C CE NR13 1 2 3 4 5 6 7 8 9 M– NK13 NR14 NK14 NR15 NK15 NR16 NK16 NR17 NK17 NR18 NK18 NR19 NK19 NR20 NK20 NR21 NK21 NR22 NK22 0 1 2 3 4 5 6 7 8 9 1 3 5 7 9 94 94 94 94 2 3 6 7 93 93 93 92 92 92 D ØB1 D 2-12 1 ØB2 ØB4 – 4 KNUM NR28 ÷ 7 Ø3 NR12 ØB1 NR3 D MC MR ØnD1 ØnD7 TEST POINTS P X NR42 GND NR10 VDD (–24V) 2N4401 IDLE ØnD3 ØnD5 NR44 STEP NR27 NK27 PTRIGGER KRC KMR KMC NR26 NK26 91.1 91.2 91.3 91.4 97.1 § 97.2 97.3 § 97.4 § d28 0.047 100K 10 D 3 1 7-12 Q 4-6 2 Øn(D16•B8•1) Ø2 2K 0.5W Ø3 BUSY NORMAL MANUAL NR35 NK35 IDLE PMANUAL KD NK24 NR9 NK9 NR31 NK31 d32 d33 0.001 E KMD KRC KMC 300K NR32 NK32 VCL NR43 NK43 nDPØD KMR NK3 NR3 NK1 NR1 NK6 NR6 NK4 NR4 NK2 NR2 0 2 3 4 6 8 11 5 1 E 2 9 D Q 4-6 DPØD ØC Øn(D16•B8•1) ØC ØT Ø2 ØT ØR Ø3 ØR E 3 4 E 7 7-12 1-7 5 KCLR 8 D 5 D 4-6 Ø2 Section: Keyboard & P-Cycle Generator Page: 5 Rendition: 2020 May 20 D 4 1-4 100K Øn(D16•B8•1) Sharp Compet 17 Calculator KEQ 100K D d42 NR24 1 NR38 KS § ØnD4 NR40 NK30 § KNDP KDP KEQ KMD KCE KNDP NR30 RC KNP NK28 ØnD1 (via diode) 150K NK29 KMAS d29 × Ø1 NR39 NR29 § 10 Controller / Monitor Unit (see Notes page) NR7 NK34 98.4 § 98.3 § 98.2 § d46 98.1 = 2-12 d26 96 96 96 96 d27 DP NR34 8 95 95 95 95 0 KMS 2 11 d31 NK33 5 D 9 NR33 KCE § 3 ØB8 8 NK25 d45 M+ D NR25 § 9 4 5 6 7 KCLR d30 IDLE 0 NK23 NR23 Ø3 7 5 1 ØC ØT ØR E Q 4 NK40 NR40 E P 8 1-7 D 4 nP ÷ × NK36 NK37 100 100 C458 8 KEQ•C•D KCLR S2•nF•J•nM(K) 67.4 67.1 67.2 67.3 KMD K 9 67 D Q E 3 4-7 M-10 CPA’ Ø2 Ø3 7 5 1 10 1-7 ØC D 2 C nC nC nD KMD KCLR S2•nF•J•nM(K) KD d43 K 8 68 ØR D 4-7 M-9 CPA’ ØC Ø2 ØT Ø3 ØR E 4 7-14 E 8 7-14 E 3 7-14 KEQ•C•D 10 K 5 KEQ•C•nD D C 68.4 68.1 68.2 68.3 7-14 9 1 nC ØT 50K 11 KEQ E D 50K 4 1-3 D d41 C458 KEQ•nC•D 7 nD D Q 4 9 1-7 D 3 D C nD D KEQ•nC•nD 2 11 KS 7-13 9 KS•nC•nD 10 C+D 2 KNDP nM+nS 7-11 3 KNDP•M•S 1 d5 KCE KMD•S d24 KCE' 1 4 (Note possibility of backflow from KNDP•M•S•nC•nD+KCLR+KMD•S to KNDP•M•S) KMS KCLR S2•nF•J•nM 17.1 17.3 17.4 17.2 17 10 D Q 4-3 KEQ KMD•S KRC 27.3 27.1 27.4 27.2 CPA’ 27 Ø2 M-3 Ø3 11 5 1 H 2 S 10 1-3 ØC D 2 nS ØR nM KMAS KMD•S KCLR S2•nF•J•nM KNDP•M•S KNP•(nM+nS) KEQ KRC S2•F•J KMR D2 § M-8 25.1 25.2 25.3 25.4 14.4 § d18 § 5 d8 d23 KCLR KMD•S KNDP•M•S•nC•nD+KCLR+KMD•S S KMD M-7 KMD•S ØT d34 16.1 16.2 16.3 16.4 S nS 7-11 E 1 KEQ•C•nD 3 7-13 4 7-13 9 7-12 2 MUL•M•nS S 16 9 D Q 4-3 CPA’ Ø2 25 M-4 Ø3 d35 D1 Sharp Compet 17 Calculator Section: Control (Major Operation Flags) Page: 6 Rendition: 2020 May 20 7 5 1 ØC ØT M H 3 9 1-3 D 3 M S nM nM nS E 5 MUL•nM•nS C458 KNP E 7 1-3 Øn(D16•B8•1) D 5 10 KNP•(nM+nS) E nP CPA’ nM+nS 5K ØR S1•nF•J•M S6•nF•J S5•F•J S1•F•J SCd S2•nF•J•M S2•F•nJ S2•nF•J•nM KEQ KCLR 36.4 § 42.4 45.4 48.4 55.4 65.1 65.2 65.3 65.4 d13 C458 65 11 1-5 Øn(D16•B8•1) D nP E 1 CPA 5K KDP S6•nF•nJ KEQ•nC•D S3 S1•nF•J•M S4•nF•nJ S6•nF•J S5•nF•J S1•nF•J•nM KEQ•C•D MUL•M•nS MUL•nM•nS CARRY ØB8 ØD12 S6•F•nJ S1•nF•J•M ØD1 1 3 2 4 3-3 5 K E 10 13.3 § D Q 4-2 M-1 Ø1 XC1 S4•nF•nJ PX SCa X SCb PXI S5•F•nJ 11 E H 2 ØC Ø2 ØT Ø3 ØR 4 SCa S4•F•J S6•F•J KEQ S2•F•nJ S2•F•J KCE' KRC SCk S1•F•J 15.4 15.1 15.2 15.3 13.4 § 23.1 23.2 23.3 23.4 33.1 58.2 d6 23 22.1 22.2 22.3 22.4 26.1 26.2 26.3 26.4 37.1 § d4 22 26 G nG S1•nJ D Q 4-3 M-5 CPA’ d36 Ø2 Ø3 7 5 1 KNP H 4 7 1-4 ØC D 5 F nF nF nF ØT nF ØR nJ 2-5 F E 2 5 F 10 2-9 3 ØD1 E 5 2 ØD11 9 2-8 DPØD E 7 CPA’ J 2-5 11 d20 KCLR 8 1 10 E 7 9 E 9 D 2-9 9 11 Q 4-2 7 10 Ø1 ØC Ø2 ØT Ø3 ØR J 3 11 1-4 D 1 1-4 D 3 nJ 8 SCm S6•nF•J SCe S3 S2•nF•nJ 32.4 W ØB8 K ØnD16 42.2 24.2 38.1 d15 9 10 11 8 Sharp Compet 17 Calculator 3-3 7 E K PX Øn(D16•B8•1) 4 1 8 D 2-8 Q 4-2 3 2 Section: Control (F, J & G Flags) Page: 7 Rendition: 2020 May 20 7 Ø1 5 Ø2 Ø3 7 5 1 ØC ØT ØR E 4 G 9 nG KNP•F nF J E E E nJ 1 11 7-12 J 3 4 11 8 J nF 8 S2•nF•nJ 8 E nF+nJ nF+J F+nJ F+J KEQ•nC•D KEQ•C•D S4•F•J S2•nF•J•M KEQ•nC•nD d16 § K d44 8 D 4-5 CPA Ø2 Ø3 7 5 1 12.1 12.3 12.4 12.2 12 E Q 4 S6•nF•J 9 D 4-5 11 E Q 3 KEQ•C•nD 10 D Q 4-5 E K 2 42.1 K 8 38.3 CPA ØC CPA ØC ØT Ø2 ØT Ø2 ØT Ø2 ØR Ø3 ØR Ø3 ØR Ø3 K 5 S1•F•J 7-9 Q 4-4 ØC 4 D S3 CPA 7 5 1 E 4 S2•F•nJ 3 7-10 7-11 11 E 2 9 D Q 4-4 CPA ØC CPA ØC ØT Ø2 ØT Ø2 ØT ØR Ø3 ØR Ø3 ØR K 5 S4•F•J 4 7-8 S4•F•nJ 3 7-8 S4•nF•nJ 9 7-8 S4•nF•J 8 S2•F•J 4 7-6 K 2 S2•F•nJ 3 7-6 K 10 S2•nF•nJ 9 7-6 5 Q ØC 1 7-10 D 4-4 1 4 10 E 3 1 1 5 S5•F•J 4 7-7 S5•F•nJ 3 7-7 S5•nF•nJ 9 7-7 S5•nF•J 8 S6•F•J 5 nF+nJ 2 K 2 K 2 S6•F•nJ nF+J 11 9 K 10 10 10 S6•nF•nJ F+J 11 8 11 7-6 7 11 7-8 7 7-7 7 S6•nF•J F+nJ 11 nM M § § 9 7-9 8 7-9 E E NR5 C+D 3 7 NR11 NK5 S1•nF•J•M 9 7-10 S1•nF•J•nM 8 7-11 d21 K NK11 d22 1 J 10 7-9 K 2 10 7 S2•nF•J•M S2•nF•J•nM 11 E 8 7-10 7 S2•nF•J•nM(K) 2SA549 2SC641 S1•nJ H IDLE to P generator 50K Sharp Compet 17 Calculator Section: Control (State Matrix) Page: 8 Rendition: 2020 May 20 NK38 IDLE to keyboard NR38 SCe SCm SCa nP SCb KNP•(nM+nS) S5•F•J S4•F•nJ S6•nF•nJ S5•F•nJ K d1 d7 K S5•nF•nJ SCk S5•F•J S1•F•J MUL•M•nS S3 S4•F•J S2•F•nJ S1•nJ KRC S1•nF•J•nM S5•nF•J KEQ•nC•D S1•nF•J•M KS•nC•nD S1•F•J MUL•M•nS 37.4 § 46.1 46.2 46.3 46.4 SCa SCb d11 SCf MUL•nM•nS SCh 43 42.3 48.2 49.2 K SCd CAX S 43.1 43.3 43.4 43.2 21.1 21.3 21.4 21.2 K CAM CAW CXD12 CBX d3 36.1 § d9 13.1 11 § 7-5 300K S1•F•J VCL S4•nF•J S6•nF•J S6•F•J SCm S1•F•J SCg SCm S6•nF•J S6•nF•nJ nP 21 SCe SCe SCm SCg SCa S6•nF•J KNP•(nM+nS) SCb MUL•nM•nS SCf KCE' S2•F•J SCc SCf SCg SCh SCm SCf SCg MUL•nM•nS S2•nF•nJ KCE' S2•F•J SCc 24.3 31.3 49.3 51.1 51.2 51.3 51.4 53.1 53.2 53.3 53.4 64.4 31.1 44.4 49.4 54.1 54.2 54.3 54.4 64.2 MUL•M•nS KNDP•M•S•nC•nD+KCLR+KMD•S SCf MUL•nM•nS 51 CXØnD11 SCm KNDP•M•S•nC•nD+KCLR+KMD•S G G SCh D2 M-2 D1 S6•nF•J SCf MUL•nM•nS KCE' 11.1 11.2 11.3 11.4 32.1 48.1 49.1 32.3 63.1 63.2 63.3 63.4 CXØD11 31.2 11 10 1-4 D 2 K 63 K 35.1 44.2 d10 K 32.2 35.2 66.1 66.2 66.3 66.4 66 K S1•nF•J•M S1•nF•J•M S2•F•J SCk KMC 13.2 § 14.3 § 37.2 § d17 § K CSUB KMC SCe KEQ•C•D SCd SCb KCE' SCf KNP•F SCc CTC CSUM SCf S2•nF•nJ SCa KEQ•C•D KCE' SCd SCc CWW S3 S2•F•nJ MUL•M•nS CWØ CMX KNDP•M•S•nC•nD+KCLR+KMD•S SCf S5•F•J S4•F•J S1•F•J CMØ KNDP•M•S•nC•nD+KCLR+KMD•S S5•F•J S4•F•J S2•F•nJ SCf SCh KEQ•C•D S3 Sharp Compet 17 Calculator Section: Control (Outputs) Page: 9 Rendition: 2020 May 20 61 56.1 56.2 56.3 56.4 56 47.3 K d12 CPXPX CPXPW CPXD1 CPXD13 d19 § d25 § K 24.1 33.4 55.3 62.1 62.2 62.3 62.4 64.1 62 44.3 52.1 52.2 52.3 52.4 55.1 64.3 52 38.2 47.4 58.1 K 35.4 44.1 45.1 K SCk CPXDPØD CPXØnD13 CPXØD13 CWX SCd K 33.3 61.1 61.2 61.3 61.4 S3 KMR 58.3 14.1 § 36.2 § S2•F•J 54 S2•F•nJ 7 CBW SCm SCm 48.3 58.4 8 § CBWG 47.1 34.1 34.2 34.3 34.4 S4•F•J S5•F•J SCf SCh S1•nF•J•M 14.2 § 36.3 § 37.3 § S4•nF•J S6•F•nJ S6•F•J 38.4 41 S2•F•J S1•nF•J•M SCk S2•F•nJ S6•nF•J S1•F•J SCg S4•nF•J SCc 24.4 31.4 41.1 41.2 41.3 41.4 45.3 KEQ•C•D SCb nP S1•nJ KNP•F nF CPWPX CPWPY CPWDPØD 55.2 35.3 45.2 57.1 57.2 57.3 57.4 33.2 d2 M-6 CPWPW K CPWØG 57 K CPWØnG CPYPX 10 4 W 2-2 CAX 3 CAW E 5 2 M 3 1 4 2 nG P CBX E 10 11 9 8 ØD13 G CBWG ØnD11 CXØnD11 ØD11 CXØD11 d39 K d14 9 P CBW CXD12 3-2 B In 9 XØ 4 Ø2 7 10 11 10 8 9 J 47.2 ØD12 P 3-1 E 7 QA8 7 8 DB1 3 2 QB8 9 6 DA1 6-9 ØC QA8 7 8 DB1 6-8 4 ØC ØT Ø2 ØT Ø2 ØR Ø3 ØR Ø3 3 2 QB8 9 6 DA1 6-8 ØC QA8 7 8 DB1 6-7 4 ØC ØT Ø2 ØT Ø2 ØR Ø3 ØR Ø3 3 2 QB8 E 6 QB8 E 6 W QB8 E 6 M 6-7 ØC X NK44 NR44 ØC ØT Ø2 ØT ØR Ø3 ØR 2SC458 82 82 82 ØD1416 Ø1 D 8 1-5 4 DA1 6-9 Ø3 E 7 Serial Sum Adder 5 E 2-7 d47 A In 3-2 8 11 KNUM 9 P W E 7 8 1 CAM 2-2 11 E XØ (CPX) 5K nP 3 CWW X CWX nP ØD13 ØD1416 Ø1 81 81 81 81 2-1 4 E 5 1 9 4 E 10 § D 2 1-5 QA8 7 8 DB1 6-3 2 Ø2 CWØ DA1 § ? Ø3 2SC458 3 2 QB8 9 6 DA1 6-3 ØC QA8 7 8 DB1 6-2 4 ØC ØT Ø2 ØT Ø2 ØR Ø3 ØR Ø3 3 2 QB8 9 6 DA1 6-2 ØC QA8 7 8 DB1 6-1 4 ØC ØT Ø2 ØT Ø2 ØR Ø3 ØR Ø3 3 2 6-1 ØC ØC ØT Ø2 ØT ØR Ø3 ØR WØ (CPW) 5K § KMC CMX d38 K d37 3 1 7-5 4 D 2 X 2-4 3 E 5 1 9 2 4 Ø2 § CMØ 4 7-5 § ? 5 § § ? § MØ (CPM) 5K Sharp Compet 17 Calculator Section: Registers Page: 10 Rendition: 2020 May 20 Ø3 2SC458 § § 3 2 DA1 ØC QA8 7 8 6-6 § DB1 ØC QB8 9 6 6-6 § 4 ØT Ø2 ØT Ø2 ØR Ø3 ØR Ø3 3 2 DA1 ØC QA8 7 8 6-5 § DB1 ØC QB8 9 6 6-5 § 4 ØT Ø2 ØT Ø2 ØR Ø3 ØR Ø3 3 2 DA1 ØC QA8 7 8 6-4 § DB1 ØC ØT Ø2 ØT ØR Ø3 ØR 6-4 § H 8 7 7-4 E 11 9 10 ØnD1 Operand Adder A In B In 8,10 7-2 7,9 E 11 7-3 E 1 7 Ø2 CSUB 3,5 7-2 E 1 E 7,9 D 8,10 XØ 2,4 8 6 D 1 H 11 2-3 7-4 H 1 H Sum 5-6 ØC ØT Q4 D 1 Q3 D 2 Q2 D 3 Q1 D 4 XC4 XC3 XC2 XC1 ! ! ! Check pin numbers and ordering on IC 5-6 outputs - might be reversed / 2017-05. Six Generator 9 10 Tens-Carry Detector E 7 11 ØB8 CTC 4 1 3 2 3-1 3 ØB2 5 E Carry Latch CARRY d 10 Ø1 Ø3 Rendition: 2020 May 20 D Q 4-1 Ø2 Sharp Compet 17 Calculator 4 1 ØnD16 Section: Arithmetic Page: 11 7-3 3,5 8 1-6 Normalisation Adder 2,4 3,5 11 CSUM 11 5 1 ØC ØT ØR ØB1 E 2 CSUB 2,4 10 11 9 2-3 E 5 9 D Q 4-1 2 Ø1 Ø2 Ø3 7 5 1 ØC ØT ØR E 3 ØnB8 Normalisation Carry Latch 2-1 E 7 8 D Q 4-1 8 Ø1 ØC Ø2 ØT Ø3 ØR E 4 PW CPXPW ØD1 CPXD1 ØD13 CPXD13 DPØD ØnD13 CPXØnD13 ØD13 CPXØD13 1 CPXDPØD 2-7 3 2-10 4 1 2 5 CPXPX E 2 11 2-10 P 2-11 1 E 5 4 9 3 4 10 Ø2 9 7 Ø3 3 2 DA1 QA8 7 8 DB1 6-12 QB8 E 6 PX 6-12 ØC ØC ØT Ø2 ØT ØR Ø3 ØR 10 11 Ø2 E 5 7 1-5 4 D 5 ØnB8 Ø1 84 84 84 Q 4-7 8 2 3 D 2SC458 Ø3 5 1 ØC ØT ØR E cpx nP 5K 3 CPWPW PX CPWPX G CPWØG nG CPWØnG 9 8 11 PY 2-11 E 7 9 1-5 2SC458 D 3 CPWPY E DPØD CPWDPØD cpw 10 2-6 4 1 5 2 E 11 9 DA1 2-6 10 4 9 7 Ø2 8 Ø3 3 2 QA8 7 8 DB1 6-11 QB8 E 6 PW QB8 E 6 PY 6-11 ØC ØC ØT Ø2 ØT ØR Ø3 ØR 5K 9 CPYPX 11 1-3 D 1 PX 8 11 2-4 E 7 9 10 nP ØnB8 Ø1 83 83 83 Ø2 Ø3 cpy 5K Sharp Compet 17 Calculator Section: Decimal Point Counters Page: 12 Rendition: 2020 May 20 4 2SC458 E 3 2 DA1 QA8 7 8 DB1 6-10 6-10 ØC ØC ØT Ø2 ØT ØR Ø3 ØR E 2 PXI 11 1-7 D 1 NL35 NK8 nPXI NR8 V+90D 2SC458 n2 n4 n8 110K a 2SC857 10K V+90D 110K 10K 2SC857 V+90D 2SC458 2 110K a 2SC857 n4 V+90D 10K 110K 10K 2SC857 V+90D 2SC458 n2 110K a 2SC857 4 10K DIGIT 12 (MSD) V+90D 110K 10K XC2 NL2 8 7-1 A 7 XC3 NL1 9 7-1 1-2 15K A 3 V+90D 2 10K 2SC458 2 110K a 2SC857 4 A 10 10K n4 10 1-2 A 2 NL3 3 7-1 2N4888 30K 0.1 250V V+90 3K V+90D 1S84 110K 10K 4 2SC857 1 XC4 ØnD13 n2 9 6 ØnB1+3 V+190 2SC458 2SC857 11 Hitachi CD81 V+90D B 2 n8 11 1-2 B 1 2SC458 40K 8 110K 2SC857 V+90D 10K 110K 10K 2SC857 V+90D XC1 NL4 4 7-1 B 5 2SC458 n1 ØnD1 ØnB1+3 8 1-2 B 4 2SC458 b nPXI 40K Sharp Compet 17 Calculator Section: Display Page: 13 Rendition: 2020 May 20 2SC857 20K 1 ØnD1 ØnB1+3 110K Ø3 b DIGITS 11 to 1 (LSD) 200pF NL35 2SC458 20K 50K 1K 1 3 5 7 9 0 2 4 6 8 . yellow 0.5 AMP. POWER 115VAC 18W 16mA 1K 1W 300 10 315V red NM11 NM10 NP4 brown 10 315V black 30K blue 470pF 0.1 30K V+190 +200V V+90 +74V 0.1 250V V+90D red 470pF 2SD175 white NM6 NP1 grey black NL27 100K ? AMP. 300 50V 20 35V 2SC857 0.047 250V 192mA NM5 NM3 NP2 white 3K NL28 –17V NL29 NL30 1K –24V NK42 NR42 VCL 12 12 12 12 10 µPD1 µPD2 µPD3 µPD4 6 6 6 6 9 10 12 12 µPD5 µPD6 µPD7 µPD7 5 5 6 6 (VDD) NL31 NL32 ØnB1+3 NK10 NR10 1-1 1-2 1-3 1-4 1-5 1-6 1-7 2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8 2-9 2-10 2-11 2-12 3-1 3-2 3-3 4-1 4-2 4-3 4-4 4-5 4-6 4-7 5-1 5-2 5-3 5-4 5-5 5-6 6-1 6-2 6-3 6-7 6-8 6-9 6-4 6-5 6-6 6-10 6-11 6-12 7-2 7-3 7-4 7-5 7-6 7-7 7-8 7-9 7-10 7-11 7-12 7-13 7-14 7-1 Unused Elements Sharp Compet 17 Calculator Section: Power Supply Page: 14 Rendition: 2020 May 20 9 § 7-5 8 10 7-13 7 600 0µS 40 80 120 160 200 240 280 320 360 400 440 480 520 560 640 0µS 600 logic 1 (0V, GND) (47.6 KHz) Ø1 logic 0 (–24V) Ø2 Ø3 (11.9 KHz) ØB1 ØB2 ØB4 ØB8 ØnB1+3 (744 Hz) ØnD1 ØnD2 ØnD16 ØD1416 Øn(D16•B8•1) X and PXI with 000987654321. in the display. X PXI ØDn 16 Digit being displayed 1 2 3 4 5 6 1 (LSD) 2 3 4 5 Sharp Compet 17 Calculator Section: Timing Diagram Page: 15 Rendition: 2020 May 20 7 8 9 10 11 12 13 6 7 8 9 10 11 12 (MSD) One full number cycle in registers 14 15 16 The µPD Integrated Circuit Family Discrete Gate Construction ♦ Based on supply voltage, circuit impedances and logic density, IC technology is presumed to be early MOS. Most OR and some AND gates are constructed from discrete diodes and resistors. More complex logic elements are contained in integrated circuits. The internal construction of discrete gates is shown in the following diagrams. A wire–OR or wire–AND construction is indicated by the input line traversing the width of the gate. ♦ Gate symbols are presented in accordance with: logic 1 = 0V, GND logic 0 = –24V ♦ Outputs are open-collector, closing to GND (logic 1) and requiring external pull-down resistor to –24V (logic 0). ♦ Inferred for flip-flops: The flip-flops in this logic family appear to be Master/Slave D-type flip-flops with the clocks for the master and slave sections kept separate. This permits a system design where data capture is done in accordance with the requirements of the logic while all outputs are changed synchronously by a single clock signal. ØC = Capture Input (master section clock) ØT = Transition Input (slave section clock) The state of the D input is captured when ØC is logic 0 (–24V). The Q output is set in accordance with the captured state when ØT goes to logic 0. AND Gate OR Gate r r OR Gate with ‘wired’ input r R R 12 11 10 9 8 7 12 GND 11 10 9 8 The diodes and resistors may be individual components or contained in TDA001 and TDA002 packages. 7 NEC V380 GND µPD1 µPD4 D ØC Q ØR ØT D ØC D Q ØR ØT ØC 1 2 3 4 5 6 1 2 3 4 5 12 11 10 9 8 7 10 9 8 7 6 GND GND ØC D1 In ØT µPD2 C –24V GND µPD5 –24V TDA001 EC Symbol (r) A B C D E H J B TDA002 1 1 4-bit Shift Register 2 2 3 3 Q4 Q3 Q2 Q1 Out Out Out Out –24V 4 0 543210 4 0 470K 3 4 5 6 1 2 3 4 5 12 11 10 9 8 7 10 9 8 7 6 12 GND DA1 QA8 DB1 QB8 In Out In Out GND µPD6 Dual 8-bit Shift Register 11 10 9 Resistance (R) 15K to VDD 20K to VDD 30K to VDD 50K to VDD 100K to VDD 150K to VDD 300K to VDD K nn 300K to VCL 470K to VCL, internal to TDA002 unit nn a b c d 40K to GND 60K to GND 100K to GND 300K to GND Occasionally individual MOSFET transistors or MOSFETs contained in µPD7 ICs are used as AND gates. The gate of these transistors functions as an inverted input. Because the MOSFET is a bidirectional device, a diode is usually required on the other input or the output to prevent ‘backflow’ of the signal. 5 2 µPD3 D2 G D1 6 1 GND Most gate outputs have load resistors (R) connected from the output to one side of the power supply. To reduce clutter these resistors are indicated in the schematic by one of the following letters (r) in a box near the output. Q ØR ØT –24V 8 7 NEC V380 or 1/4 of µPD7 G µPD7 D1 C –24V 1 2 3 4 5 6 1 ØR ØT ØC –24V 2 4 3 5 Sharp Compet 17 Calculator N R 1 ØnD3 2 ØnD7 17 key 4 30 KEQ 31 KMC § NL XC3 1 2 XC2 XC4 3 4 XC1 D2 –24V 1 Section: IC Pinouts and Gate Construction Page: 16 Rendition: 2020 May 20 R 2 3 4 5 6 Special mention must be made of the unusual use of a µPD7 for the 4-bit display latch. Controlling pin 6 allows it to function as a sample-and-hold latch, presumably relying on inter-electrode capacitance to hold the state between digit updates (see Display). N R 1 ØnD3 17 key 4 2 ØnD7 30 KEQ NL XC3 1 2 XC2 31 KMC § XC4 3 4 XC1 3 ØnD1 18 key 5 32 KMR § ØnD16 5 6 T 4 ØnD5 19 key 6 33 KMS § ØnD13 7 8 ØnB8 5 K 20 key 7 34 KMAS § ØnD12 9 10 Ø3 6 ØnD4 21 key 8 35 PMANUAL ØnD11 11 12 Ø2 7 Ø1 22 key 9 36 — 23 KCLR 37 — ØnD1 15 16 ØnD1 9 key RC 24 KMD 38 IDLE ØB1 17 18 — 10 VDD 25 KCE 39 Ø3 ØB2 19 20 — 11 K 26 KD 40 P ØB4 21 22 — 12 ØB1 27 PTRIGGER 41 — ØB8 23 24 — 13 key 0 28 KDP 15 key 2 16 key 3 29 KS 42 GND — 25 26 — 43 nDPØD GND 27 28 GND 44 X V C L 29 30 V C L 45 — VDD 31 32 VDD 6-3 6-4 6-5 6-6 2-1 4-1 2-3 3-1 7-2 2-2 7-3 3-2 A8 6-7 6-9 6-8 7-4 8 1 • Italicised expressions are connections with no signal name in the schematic. 8 2 8 3 1-3 1-4 7-5 7-6 7-7 M-2 4-4 6-12 3-3 2-5 2-6 2-7 2-8 2-9 1-5 2-10 2-11 1-6 39 14 11 15 21 31 41 51 61 12 22 32 42 52 62 21 — 43 44 ØnD7 7-12 2 13 23 33 43 53 63 14 24 44 54 64 25 34 7 35 45 55 65 5 36 46 56 12 57 66 58 67 15 4 22 16 7-10 27 9 18 8 46 19 25 17 2 ØnD7 ØnD1 3 4 ØnD5 23 K 5 6 ØnD4 Ø1 7 8 nPXI M-6 34 9 35 8 M-7 36 32 33 45 24 9 28 1 92 29 30 31 94 9 7 47 17 16 7-11 93 9 5 9 6 7-13 11 26 4-5 4-6 6 3 20 7-9 M-3 M-4 M-5 6-11 10 7-8 — 41 42 ØnD5 ØnD3 1 6-10 1 4-3 — 39 40 ØnD3 2-4 40 37 38 — 37 38 ØnD4 NK Logic Board 4-2 nPXI 35 36 — • ØnDx signals on the NK and NR connectors have a diode between the connector and the actual signal. See the Keyboard page. 8 4 (component side view) M-1 — 33 34 — • The NK and NR connector pins are numerically correlated. 6-2 — 13 14 Ø1 8 nPXI 14 key 1 6-1 37 48 38 49 13 7-14 67 M-9 4-7 44 41 26 27 1-7 43 M-10 42 2-12 M-8 KRC 9 10 VDD K 11 12 ØB1 key 0 13 14 key 1 component side: NK43 solder side: NK44 NL43 NL44 NK01 NK02 NL01 NL02 key 2 15 16 key 3 key 4 17 18 key 5 key 6 19 20 key 7 05 04 03 02 5-1 5-2 5-3 5-4 01 key 8 21 22 key 9 KCLR 23 24 KMD KCE 25 26 KD § KMC 31 32 KMR § § KMS 33 34 KMAS § PMANUAL 35 36 lamp * 5-5 Display Board PTRIGGER 27 28 KDP KS 29 30 KEQ 1-1 (component side view) 1-2 Digit 1 (LSD) Digit 12 (MSD) 7-1 lamp ÷ 37 38 IDLE Sharp Compet 17 Calculator Section: Physical Layout and Connectors Page: 17 Rendition: 2020 May 20 Ø3 39 40 P — 41 42 GND nDPØD 43 44 X NP06 NP01 47