Schematic
Eighteen-page schematic of the Royal Digital I desk calculator of 1971: 29 NEC and Mitsubishi MOS chips on -24 V, ten Ise DG-12C tubes with filaments in series, grid blanking transistor.
Royal Digital I Calculator Contents Section Page Title & Contents (this page) 1 Notes, Signal Names & Logic Design 2 Block Diagram 3 State Diagram 4 Multiplication State Sequence Example 5 Division State Sequence Example 6 Timing Diagram 7 Timing 8 Keyboard 9 Control State Machine 10 Control Counters 11 Control Flags 12 Registers & Arithmetic 13 Display 14 Power Supply 15 IC & Module Pinouts 16 IC Functional Equivalents 17 Connectors & Board Layout 18 Royal Digital I Calculator This schematic has been derived through reverse engineering. Section: Title and Contents This is not the manufacturer’s schematic, Page: 1 Rendition: 2021 Feb 16 nor based on the manufacturer’s schematic. Notes Logic Presentation Ncp Gate symbols and signal names are presented in accordance with: • The symbol denotes a physical connector pin, where c=connector and p=pin. Solid black end is the male side of logic 1 = GND the connector. White end is the female side of the connector. logic 0 = V–24 • The symbol without an additional label denotes VDD (–24V). The design uses primarily negative logic in the control portion and positive logic for data and registers. • Capacitance in microfarads unless otherwise indicated. Logic Implementation • These drawings based on unit with Serial No. 1G54100. The logic is implemented with a combination of early SSI and MSI MOS integrated circuits from the JMOS family, and discrete DTL. Most gates are constructed from discrete diodes and resistors. Inverters, active gates, flip-flops and more complex logic elements are contained in • See also the Royal Digital I Theory of Operation document. (madrona.ca/e/eec) the integrated circuits. The active elements are open-drain outputs, closing to GND (logic 1), requiring external pull-down resistors to –24V (logic 0). Log The internal construction of discrete gates is shown in the following diagrams. A wire–OR or wire–AND construction is indicated by the • 2020 Mar: Initial drawing / bhilpert. input line traversing the width of the gate. The design is heavily optimised for component reduction with many gates having one input • 2020 Oct: State sequences replaced with simulator output / bh. formed from the pull-up/down load resistor, rather than a diode and fixed-supply resistor. • 2021 Jan: Minor syntax corrections / bh. Positive-Logic AND Positive-Logic OR ‘wired’ input Signal Names r r r Section Signal Description Timing ØC Master clock, data capture phase. Negative-Logic OR Negative-Logic AND ØT Master clock, toggle outputs phase. ØB1,2,4,8 Bit timing. r r ØD… Digit timing (4 bits constitutes a digit). ØEON Capture pulse at the end of number cycle. Keyboard KNUM 0::9 numeral key bit stream. KPN Process a numeral key (state-synchronised latch). R KPD Process the decimal point key. KPO Process an operation key. R R KC, KCE Clear keys. Control STn Primary states of the control state machine. OPAS Add/Subtract operation to be performed. OPMD Multiply/divide operation to be performed. OPAM Add/Multiply. OPSD Subract/Divide. The diodes may be individual components or contained in 4-diode TSxxx modules. Gate inputs are identified either by a pin number in the OPM Multiply operation. case of a diode in a module, the ID of the discrete diode forming the input, or the R value in the case of a resistor. OPD Divide operation. NEG Negative number flag. For gates with fixed-supply load resistors (R), to reduce clutter, the resistors are indicated in the schematic by one of the following letters (r) DFLG Temporary flag. in a box by the output. ERR Latched error or overflow state. Symbol (r) Resistance (R) Symbol (r) Resistance (R) Registers RX X register bitstream. RY Y register bitstream. 3 30K to VDD a 100K to GND N1,2,4,8 BCD numerals on their way to the display. 5 50K to VDD b 200K to GND R<0 Result Less Than Zero. Flag holding a carry/borrow indication from the arithmetic unit. 1 100K to VDD c 10K to GND Counters PLT Primary Loop Tracker. DPC Decimal Point Counter. Clocking Scheme DPC=N DPC is Null – the shift register is empty. DPC<SP DPC is less than the DP switch setting. The flip-flops in the JMOS logic family are a form of Master/Slave D-type flip-flop with the clocks for the master and slave sections kept DP Signal to the display to turn on the decimal point at the appropriate time. separate. This permits a system design where data capture is done in accordance with the requirements of the logic while outputs are changed synchronously by a single clock signal. • A “~” in a signal name indicates the logical NOT operation. • The character “ • ” in a signal name indicates the logical AND operation. ØC = Capture Input (master section clock) • The character “+” in a signal name indicates the logical OR operation. ØT = Transition Input (slave section clock) The state of the D input is captured when ØC is logic 0 (–24V). The Q output is set in accordance with the captured state when ØT goes to logic 0. Royal Digital I Calculator Section: Notes, Signal Names & Logic Design Page: 2 Rendition: 2021 Feb 16 Timing Power Supply V–24 V+D ØC ØT ØB1,2,4,8 ØD0::12 ØEON logic supply display supply bit digit phases phases Control Keyboard Operation State D NEG ERR Flags Sequencing Flag Flag Flag ST0 ST9 K0…K9 PLT Numeral Control R<0 Primary Loop Tracker Encoder Signals Flag 11 10 9 8 7 6 5 4 3 2 1 0 Arithmetic Numeral KNUM BCD Y Register DPC<SP Serializer 11 10 9 8 7 6 5 4 3 2 1 0 RY Serial Adder DPC=N ØDn Binary Decimal Point Counter Adder BCD Sum Correction 5 4 3 2 1 0 X Register RX VF 11 10 9 8 7 6 5 4 3 2 1 0 4 bits Digit DP Drivers X & Y Registers: 12 BCD digits / 48 bits N1 Digits 0::9 are entered& displayed Display Latch N2 Zero-Modify VF (4 bits) N4 & 7-Segment & Error Ind. Logic Segment Drivers 0987654321. N8 Decoder Royal Digital I 10 Calculator 7-Segment Vacuum Flourescent Displays Section: Block Diagram Page: 3 Rendition: 2021 Feb 16 KC 0 Idle loop. RX => display, 0 => RY KPN + KPD 4 1 Mul: PLT = 0 Idle loop for number entry. KPO•OPMD•DPC=N RY => display Div: Mark PLT. Shift RY up, KPD,KPO: If DPC=N, 0=>DPC and PLT up Loop til RY[9] ≠ 0. KPN•DPC<SP + Sub-loop KPO•OPAS in Mul & Div OPD•DFLG OPM 2 6 5 if DPC≠N, ++DPC DPC<SP~ AX+,SX–: RX+RY => RX,RY Shift RX up one digit. KPN: KNUM => RY[0] AX–,SX+: RX–RY => RX,RY OPD•(PLT~) Shift RY up. Mul: ++PLT A,S: Shift RY up till DP at set- Mul: RX+RY => RX point. RX[11]– – Div: if DPC=N, shift PLT down Loop while RX[11] > 0. KPN OPM•(RX[11]=0) Div: RX–RY => RX RX[11]– – if RX>=0 Primary loop KPN~ • ERR~ Loop while RX >= 0. in Mul & Div (5,6,7) OPAS KPN+ERR OPM•(RX,N842=0) + OPD•R<0 7 3 8 Div: RX+RY => RX Loop while waiting for KPN to –RY => RX,RY Undo overdraft from last deassert. NEG~ => NEG OPAS•R<0~ subtraction in ST6. if DPC≠N, – –DPC OPM•(PLT=12) 9 DPC=N If DPC≠N, shift RX down and – –DPC. Loop til DPC=(0=>N). Royal Digital I Div: RX[PLT] = 0 Calculator Section: State Diagram Page: 4 Rendition: 2021 Feb 16 Multiplication State-Sequence Example Multiply 12*4.3 with DPSwitch=3 => 51.600 ERR ST OPss PLT DPC NEG X N Y N ERR ST OPss PLT DPC NEG X N Y N 109876543210 543210 109876534210 109876543210 109876543210 543210 109876534210 109876543210 KEYPRESS: C KEYPRESS: + 0* AS/AM 111111111111 ...... ............ 0 ............ 1 MD/AM 11111111111. ....1. .......12... ..........43 0 KEYPRESS: 1 4 MD/AM 11111111111. ....1. .......12... ..........43 0 1 AS/AM 111111111111 ...... ............ ............ 0 5 MD/AM 1111111111.1 ....1. ......12.... 0 ..........43 2 AS/AM 11111111111. ...... ............ ...........1 0 7 MD/AM 1111111111.1 ....1. ......12.... 0 ..........43 3 AS/AM 11111111111. ...... ............ ...........1 0 5 MD/AM 111111111.11 ....1. .....12..... 0 ..........43 3 AS/AM 11111111111. ...... ............ ...........1 0 7 MD/AM 111111111.11 ....1. .....12..... 0 ..........43 1* AS/AM 11111111111. ...... ............ ...........1 0 5 MD/AM 11111111.111 ....1. ....12...... 0 ..........43 KEYPRESS: 2 7 MD/AM 11111111.111 ....1. ....12...... 0 ..........43 2 AS/AM 11111111111. ...... ............ ..........12 0 5 MD/AM 1111111.1111 ....1. ...12....... 0 ..........43 3 AS/AM 11111111111. ...... ............ ..........12 0 7 MD/AM 1111111.1111 ....1. ...12....... 0 ..........43 3 AS/AM 11111111111. ...... ............ ..........12 0 5 MD/AM 111111.11111 ....1. ..12........ 0 ..........43 1* AS/AM 11111111111. ...... ............ ..........12 0 7 MD/AM 111111.11111 ....1. ..12........ 0 ..........43 KEYPRESS: * 5 MD/AM 11111.111111 ....1. .12......... 0 ..........43 1 AS/AM 11111111111. .....1 ............ ..........12 0 7 MD/AM 11111.111111 ....1. .12......... 0 ..........43 2 AS/AM 11111111111. ....1. ............ .........12. 0 5 MD/AM 1111.1111111 ....1. 12.......... 0 ..........43 2 AS/AM 11111111111. ...1.. ............ ........12.. 0 7 MD/AM 1111.1111111 ....1. 12.......... 0 ..........43 2 AS/AM 11111111111. ..1... ............ .......12... 0 5 MD/AM 111.11111111 ....1. 2........... 1 ..........43 2 AS/AM 11111111111. ..1... ............ .......12... 0 6 MD/AM 111.11111111 ....1. 2.........43 0 ..........43 6 AS/AM 11111111111. ..1... .......12... 0 .......12... 0 7 MD/AM 111.11111111 ....1. 2.........43 0 ..........43 0* MD/AM 11111111111. ...... .......12... 0 ............ 5 MD/AM 11.111111111 ....1. .........43. 2 ..........43 KEYPRESS: 4 6 MD/AM 11.111111111 ....1. .........473 1 ..........43 1 MD/AM 111111111111 ...... .......12... ............ 0 6 MD/AM 11.111111111 ....1. .........516 0 ..........43 2 MD/AM 11111111111. ...... .......12... ...........4 0 7 MD/AM 11.111111111 ....1. .........516 0 ..........43 3 MD/AM 11111111111. ...... .......12... ...........4 0 5 MD/AM 1.1111111111 ....1. ........516. 0 ..........43 3 MD/AM 11111111111. ...... .......12... ...........4 0 7 MD/AM 1.1111111111 ....1. ........516. 0 ..........43 1* MD/AM 11111111111. ...... .......12... ...........4 0 5 MD/AM .11111111111 ....1. .......516.. 0 ..........43 KEYPRESS: . 7 MD/AM .11111111111 ....1. .......516.. 0 ..........43 1* MD/AM 11111111111. .....1 .......12... ...........4 0 5 MD/AM 11111111111. ....1. ......516... 0 ..........43 KEYPRESS: 3 7 MD/AM 11111111111. ....1. ......516... 0 ..........43 1 MD/AM 11111111111. .....1 .......12... ...........4 0 9 MD/AM 11111111111. ....1. .......516.. ..........43 0 2 MD/AM 11111111111. ....1. .......12... ..........43 0 9 MD/AM 11111111111. ...... .......516.. ..........43 0 3 MD/AM 11111111111. ....1. .......12... ..........43 0 0* AS/AM 11111111111. ...... .......516.. 0 ............ 3 MD/AM 11111111111. ....1. .......12... ..........43 0 1* MD/AM 11111111111. ....1. .......12... ..........43 0 continue --> • The state sequence examples were first derived from imagining the logic operation, then from a logic simulation, not from observation of the electronics. • ST column: ‘*’ indicates the state loops indefinitely until a key press/release. Royal Digital I • PLT, DPC columns: ‘.’=0 Calculator • Register columns: digit state at the end of the number cycle. Section: Multiplication State Sequence Example Page: 5 Rendition: 2021 Feb 16 • N columns: the 4-bits of the N register where it is included in the bitstream of the associated X or Y register. Division State-Sequence Example Divide 12÷5 with DPSwitch=4 => 2.4000 ERR ST OPss PLT DPC NEG X N Y N ERR ST OPss PLT DPC NEG X N Y N 109876543210 543210 109876534210 109876543210 109876543210 543210 109876534210 109876543210 KEYPRESS: C KEYPRESS: + 0* AS/AM 111111111111 ...... ............ 0 ............ 1 MD/SD 11111111111. .....1 ......12.... ...........5 0 KEYPRESS: 1 4 MD/SD .11111111111 .....1 ......12.... ..........5. 0 1 AS/AM 111111111111 ...... ............ ............ 0 4 MD/SD ..1111111111 .....1 ......12.... .........5.. 0 2 AS/AM 11111111111. ...... ............ ...........1 0 4 MD/SD ...111111111 .....1 ......12.... ........5... 0 3 AS/AM 11111111111. ...... ............ ...........1 0 4 MD/SD ....11111111 .....1 ......12.... .......5.... 0 3 AS/AM 11111111111. ...... ............ ...........1 0 4 MD/SD .....1111111 .....1 ......12.... ......5..... 0 1* AS/AM 11111111111. ...... ............ ...........1 0 4 MD/SD ......111111 .....1 ......12.... .....5...... 0 KEYPRESS: 2 4 MD/SD .......11111 .....1 ......12.... ....5....... 0 2 AS/AM 11111111111. ...... ............ ..........12 0 4 MD/SD ........1111 .....1 ......12.... ...5........ 0 3 AS/AM 11111111111. ...... ............ ..........12 0 4 MD/SD .........111 .....1 ......12.... ..5......... 0 3 AS/AM 11111111111. ...... ............ ..........12 0 4 MD/SD ..........11 .....1 ......12.... .5.......... 0 1* AS/AM 11111111111. ...... ............ ..........12 0 6 MD/SD ..........1. .....1 95....12.... 0 .5.......... KEYPRESS: / 7 MD/SD ..........1. ...... ......12.... 0 .5.......... 1 AS/AM 11111111111. .....1 ............ ..........12 0 5 MD/SD .........1.. ...... .....12..... 0 .5.......... 2 AS/AM 11111111111. ....1. ............ .........12. 0 6 MD/SD .........1.. ...... 95...12..... 0 .5.......... 2 AS/AM 11111111111. ...1.. ............ ........12.. 0 7 MD/SD .........1.. ...... .....12..... 0 .5.......... 2 AS/AM 11111111111. ..1... ............ .......12... 0 5 MD/SD ........1... ...... ....12...... 0 .5.......... 2 AS/AM 11111111111. .1.... ............ ......12.... 0 6 MD/SD ........1... ...... 95..12...... 0 .5.......... 2 AS/AM 11111111111. .1.... ............ ......12.... 0 7 MD/SD ........1... ...... ....12...... 0 .5.......... 6 AS/AM 11111111111. .1.... ......12.... 0 ......12.... 0 5 MD/SD .......1.... ...... ...12....... 0 .5.......... 0* MD/SD 11111111111. ...... ......12.... 0 ............ 6 MD/SD .......1.... ...... 95.12....... 0 .5.......... KEYPRESS: 5 7 MD/SD .......1.... ...... ...12....... 0 .5.......... 1 MD/SD 111111111111 ...... ......12.... ............ 0 5 MD/SD ......1..... ...... ..12........ 0 .5.......... 2 MD/SD 11111111111. ...... ......12.... ...........5 0 6 MD/SD ......1..... ...... 9512........ 0 .5.......... 3 MD/SD 11111111111. ...... ......12.... ...........5 0 7 MD/SD ......1..... ...... ..12........ 0 .5.......... 3 MD/SD 11111111111. ...... ......12.... ...........5 0 5 MD/SD .....1...... ...... .12......... 0 .5.......... 1* MD/SD 11111111111. ...... ......12.... ...........5 0 6 MD/SD .....1...... ...... 962......... 0 .5.......... 7 MD/SD .....1...... ...... .12......... 0 .5.......... continue --> 5 MD/SD ....1....... ...... 12.......... 0 .5.......... 6 MD/SD ....1....... ...... .7.......... 1 .5.......... 6 MD/SD ....1....... ...... .2.......... 2 .5.......... 6 MD/SD ....1....... ...... 97.......... 2 .5.......... 7 MD/SD ....1....... ...... .2.......... 2 .5.......... 5 MD/SD ...1........ ...... 2..........2 0 .5.......... 6 MD/SD ...1........ ...... 15.........2 1 .5.......... 6 MD/SD ...1........ ...... 1..........2 2 .5.......... 6 MD/SD ...1........ ...... .5.........2 3 .5.......... 6 MD/SD ...1........ ...... ...........2 4 .5.......... 6 MD/SD ...1........ ...... 95.........2 4 .5.......... 7 MD/SD ...1........ ..