Schematic
Monroe 925 Calculator: Reverse-Engineered Schematic
A 17-page schematic of the Monroe 925 of 1970, with delay-line memory and multiplexed JRC B-5755 Nixies.
Schematic
A 17-page schematic of the Monroe 925 of 1970, with delay-line memory and multiplexed JRC B-5755 Nixies.
Monroe 925 Calculator Contents Section Monroe 925 Calculator Section: Title and Contents Page: 1 Rendition: Dec 23, 2023 Page Title & Contents (this page) 1 Notes & Signal Names 2 Block Diagram 3 Timing Diagram 4 Memory Organisation 5 Memory Timing Diagram 6 State Diagram 7 Timing 8 Keyboard 9 Control 10 Memory 11 Arithmetic 12 Point Counter Display 13 14 Power Supply IC Pinouts & Gate Construction Physical Layout & Connectors 15 16 17 This is not the manufacturer’s schematic. This data has been derived through the reverse engineering of a physical unit. B. Hilpert 1997 Dec Notes Sections and Signal Names Ncpps ♦ The symol denotes a physical connector pin, where c=connector, pp=pin and s=side (T=top, B=bottom). Solid black end is the male side of the connector. White end is the female side of the connector. ♦ Section Timing ØN0..3 Description 1 Mhz clock pulse. Used for injecting pulses into the acoustic delay line. 500KHz clock pulse. This is the slice clock. 100KHz clock pulse with 1/5 duty cycle. This is the basic bit clock. The bit period is divided into 5 slices. The slices are used for interleaving the bits of the registers within one bit period. Bit Slice 4. Bit clock periods. Digit clock periods. There are 16 digit periods. Bits of the displayed digits are contained in periods 0 to 12 and displayed during periods 1 to 13. 4 number cycles. Each number cycle is a complete cycle of the 16 digits. Keyboard K… SUB MLT DIV MD FU The keyboard and numeral encoder. Subtract operation. Multiply operation pending. Divide operation pending. Multiply or Divide operation active. Key-pressed flag to initiate operation execution, synchronised to state timing. Control CC0…CC7 FN FG FJ FOF CD… The 8 states of the operation execution state machine. Flag to indicate ʻwithinʼ number during entry, 1 after first digit of number has been entered. A flag to modify state actions during some operations. Data-state capture flag. Also used to indicate whether decimal point has been entered during number entry. Overflow Flag. Assorted derived control signals to various sections. Memory X Y SD… MOF X register bit stream from the memory. Y,A,B and C register bit streams from the memory. A 4-bit register used for shifting, numeral entry and display update. Overflow indication from the X register to the overlow flag. Arithmetic AD ACA FCA Bit stream output from arithmetic, after sum correction. Carry from arithmetic. Carry Flag. PC Counter PC=0 DL=PC DP 1 when the decimal point counter is 0. 1 when the decimal point counter coincides with the switch-selected decimal location. Decimal point from counter to display. connection between different sections. connection within same section. Arrows indicate direction of signal or energy flow. ♦ The symbol ØS4 ØB0,3 ØD0..15 denotes Vcc. ♦ Capacitance in microfarads unless otherwise indicated. ♦ The delay line memory transducers are based on magnetostrictive principles. See the article “Magnetostrictive Delay Lines” in “Electronics World”, Jan. 1964. Signal ØW ØR ØS0 ♦ These drawings based on unit with Serial No.: E017715. These drawings are presumed to also apply to the Monroe 920 and the Canon 1210. The Monroe 920 does not provide the accumulator functions, the Canon 1210 has 12 rather than 13 displayed digits. ♦ See EEC pages at madrona.ca for additional information. Log ♦ 1997 Dec: Initial drawing / bhilpert. ♦ 2000 Oct: Symbol names changed to Ø standard. ♦ 2005 Jan: Memory organisation and timing details added. Some other symbol name changes, some reorganisation of arithmetic page. ♦ 2023 Dec: State diagram added, copied from old simulation. A lowercase “n” in a symbol name indicates the logical NOT operation. Original Signal Names Some signal have been renamed from those names printed on the printed circuit boards: Board/Original CPR CPW nCP TS4 TBx TDx nTD12-14 SCTx Monroe 925 Calculator Section: Notes Page: 2 Rendition: Dec 23, 2023 Schematic ØR ØW ØS0 (note inversion) ØS4 ØBx ØDx nØD1314 ØNx Board/Original n(KP•FN) KN+KP n(KC+KCI) KA+KS M+D Schematic nKPFN KNP nKCE KAS MD SD1 ECP SD4 nLDSDK Timing ØW ØR Power Supply ØS… Slice Timing ØB… Bit timing K K… Keyboard AM 7 8 9 RM 4 5 6 CI 1 2 3 C 0 * + = • ÷ ØD… Digit timing FSUB flag – = K0…K9 –5V ØN… Number timing FST flag FU flag FMLT flag FN flag FDIV flag FG flag +5V +80V +185V logic supply display supplies CC0 Overflow lamp CC7 Control FJ flag Numeral Encoder FOF flag State Sequencing K…, F…, CC… to all sections WX W1 Magnetostrictive Acoustic Delay Line (?-? bits) G-SD G-B CA SD register (4 bits) X flip-flop Sum Correction W2 Arithmetic (serial adder) G-A D latch (4 bits) AD register (4 bits) 3210987654321. PC Counter (4 bits) PC comparator Monroe 925 Calculator Decimal Indicator switch Y flip-flop 13 Nixie Displays 1242 to 1-of-10 decoder G-PC Section: Block Diagram Page: 3 Rendition: Dec 23, 2023 MR flip-flop PC=0 DI=PC 0µS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 ØW ØR 0 nØS0 1 2 3 4 ØS4 ØBx 0µS 20 40 60 80 100 120 140 160 180 200 220 240 260 280 300 320 340 360 380 400 420 440 460 480 500 520 540 560 580 600 620 640 660 680 nØS0 0 1 2 3 ØB0 ØB3 ØD0 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 ØD15 ØD1314 X and PC=0 with 987654321. in the display X PC=0 0µS 640 1280 2560 0 1920 ØB0 ØD0 ØN0 ØN1 ØN2 ØN3 X and Y with 99 in X (display), 909 in Y and 90 in A Monroe 925 Calculator Section: Timing Diagram Page: 4 Rendition: Dec 23, 2023 X Y 0 1 2 3 640 Memory Organisation Figure 1: Decimal Value Encoding The Monroe 925 incorporates 5 registers for storage of numbers, each of 16 decimal digits. The decimal digits are encoded using 1242 bit weighting (figure 1), rather than 1248. The second 2 bit is referred to here as the W bit (tWo) to distinguish it from the first 2 bit. The 5 registers are: Register Use Period X displayed operand ØN0,1,2,3 Y 2nd operand ØN0 C temporary (product,dividend) ØN1 B temporary (quotient) ØN2 A user memory / accumulator ØN3 The 5 registers present a requirement for 5•16•4=320 bits of storage. The magnetostrictive acoustic delay line and a few flip-flops provide the storage for these registers. The method of achieving this storage in a single delay line is relatively sophisticated, so this discussion will start with higher-level functional representations of the storage. Figure 2 presents a representation of the storage as seen at the register-bit level. The X register cycles through the shift register ADLX and flip-flop X, totalling 16*4=64 bits. The Y, A, B and C registers cycle sequentially through ADLY, Y and the 4 AD flip-flops, totalling 4*16*4=256 bits. As a number is 64 bits long, Y, A, B and C only cycle once every 4 number cycles while the X register cycles every number cycle. Consequently operations can be performed between the X register and any of Y, A, B, and C by choosing the appropriate number cycle period (ØN) during which to execute the operation (see table above). To provide this storage in a single delay line the register bits are interleaved by ʻslicingʼ the period of each register-bit (ØBn) into 5 shorter periods (ØSn) and storing a bit of each of the 5 registers in each of the 5 bit-slices. A given register is written into the delay line during one of the 5 slice periods and read out by being clocked into the X or Y flip-flop during particular slice periods. The data persists in the X and Y flipflops for an entire register-bit period. This is shown functionally in figure 3. Figure 4 exemplifies how the sequence of the Y, A, B, C register bit-slices shifts in the delay line relative to that of X between ØN cycles. The sequence of the register slices during period ØN0 is apparent at the right end of the delay line (XYCBA). At the left end of the delay line bits have been injected which will emerge during ØN1, but now the sequence is XCBAY (the Y bits will be injected into the empty bit-slice slots by the W2 write head). In subsequent number cycles the slice sequence will be XBAYC, XAYCB before repeating. Value W421 0 0000 Bits: 1 0001 Total Delay & Length: 635 µ S 74 inches 1880 mm 2 0010 Bit-slice: 2 µS 0.23 inches 5.9 mm 3 0011 Slice-pulse: 0.5 µ S 0.058 inches 1.5 mm 4 0100 5 1011 Velocity: 0.12 in/µS 6 1100 Velocity: 6600 mi/H 7 1101 8 1110 9 1111 Figure 2: 317.5 D D Q4 AD nØS0 ØS123 D nØS0 Q251 ADLY (251 bits) D D Q20 D nØS0 Q299 ADL1 (20 bits) nØR D ADL2 (299 bits) ØS4 D Q4 AD (4 bits) D ØS0 Acoustic Delay Line Storage and Idle-State Bit Paths - before end of period ØN0-ØD0-ØB1-ØS2 - SD X 0 1 X 15 W X 15 4 X 15 2 to Display latch B C X 0 0 0 2 2 2 A B C X 0 0 0 0 1 1 1 1 B C Y X 15 15 15 15 W W W W Acoustic Delay Line B C Y X B C Y X A B C Y X A B C Y 285 15 15 15 15 15 15 15 15 15 15 15 15 15 0 0 0 0 bit-slices 4 4 4 4 2 2 2 2 1 1 1 1 1 4 4 4 4 W1 R 595µS AD Monroe 925 Calculator Section: Memory Organisation Page: 5 Rendition: Dec 23, 2023 X 0 4 W2 40µS Y 0 1 A 15 W slice-pulse slot A 15 4 A 15 2 <register> <digit> <bit> Q Y nØS0 Figure 4: Q X nØR processing logic Each bit-slice occupies 2 µS in the delay line, if the value of that bit is 1 then a 0.5µS pulse is injected into the line during that 2µS interval. Q Y Slice-level Representation of the Delay Line Storage ØS0 The delay line provides for storage of 317.5 bits. 4 bits are not utilised (shown in figure 4 as empty bit slots), leaving 313.5 bits utilised. The M, MR, X, Y and 4 AD flip-flops of the arithmetic sum correction are also part of the register storage, for a total of 321.5 bits.The extra 1.5 bits are accounted for by overlap in time of data in flip-flops and in the delay line. In figure 4 bits X02 and B02 are simultaneously in a flip-flop and the delay line. Q X A[MSB]…A[LSB] B[MSB]…B[LSB] C[MSB]…C[LSB] Y[MSB]…Y[LSB] nØS0 Figure 3: processing logic D AD (4 bits) Q63 ADLX (63 bits) X[MSB]…X[LSB] nØS0 processing logic 3.0 mm/µS 10700 Km/H Register-bit-level Representation of the Delay Line Storage processing logic A neat trick is performed at this point in the design to achieve the sequencing of the Y, A, B, and C registers. The delay line length including the M and MR flip-flops is one slice short of a full number period. Bits of the X register enter the delay line during slice ØS0 and show up in the M flip-flop during slice ØS4. They are resynchronised to the number cycle during the longer stay in the X flip-flop. Bits of the Y, A, B and C registers initially enter the delay line during slice ØS4. The bits then re-enter the delay line three more times before heading for the Y flip-flop. As a result of the delay being one slice short, each re-entry is one slice earlier than the previous entry and a particular bit only appears in the Y flip-flop during one of the four ØN periods. The ʻslippageʼ of a data bit is halted when the bit is resynchronised to the number cycle during the longer stay in the Y flip-flop. Figure 4 presents a more complete representation of the contents of the acoustic delay line memory and the flip-flops in the register bit paths during the normal or idle state. Each 1-bit storage element is labeled with the data bit contained in that element just before the end of the slice period ØS2 during the second bit (ØB1) of the first digit (ØD0) of the number cycle during which the X and Y registers are processed (ØN0). Figure 5: Some Characteristics of the Delay Line <register> = X,Y,C,B,A <digit> = 0 (LSD) … 15 (MSD) <bit> = 1, 2, 4, W M A 0 2 2µS MR B 0 2 2µS X X 0 2 10µS Y 0 2 Y Figure 6: Acoustic Delay Line Timing Re = Register(event sequence) 0µS –640 10 –630 20 –620 30 –610 0µS 50 –590 40 –600 580 630 –10 590 640 0µS 600 650 10 (1MHz) ØW ØR ØS0 0 1 3 4 0 1 2 X1 WX Wr delay line W1 current 2 X2 3 4 X7 Y1 C1 B1 Y2 C2 B2 AD / W2 X8 C6 B6 A6 A1 delay line W2 current A2 delay line read X3 Y3 C3 B3 A3 M reset M X4 MR Y4 C4 B4 A4 X5 Y5 C5 B5 X6 X Y6 Y Figure 6 presents the timing for data bits injected into the delay line. Shown is one data bit of each register being written into the delay line and the trail of events each bit produces to the point it is cycled back into the line. A bit of the X register at the WX input (X1) produces current in the W1 write coil (X2) during ØS0 to inject a pulse at the beginning of the delay line. When this pulse has traversed the delay line it produces a read pulse (X3) which sets the M flipflop (X4) and is then transferred to the MR flip-flop (X5). At the end of ØS4 it is clocked into the X flip-flop (X6) where it persists for an entire register-bit period and is available for register-level operations. If appropriate to the operation it is injected back into the delay line (X7,X8), again during ØS0. For the Y, A, B, and C registers a data bit initially enters the delay line during ØS4 via the W2 write head. Shown is a data bit from the A register starting itʼs cycle (A1,A2). It exits the delay line (A3), is transferred to M and then MR (A4,A5) and is written back out via the W1 head (A6), but now one slice earlier. In subsequent number cycles it follows the sequence of the other register bits (Bn,Cn,Yn) until finally entering the Y flip-flop after 4 number cycles. From the Y flip-flop it shifts through the 4 AD flip-flops, with appropriate register-level operations being performed, before being injected back into the delay line via W2. A5 Figure 7: Delay Line Read Timing ØSn M reset input delay line read signal ~ 8mV As shown in figure 7, a bit pulse exiting the delay line must do so within a 2µS window to set the M flip-flop during the appropriate bit-slice period. The entire 0.5 µS pulse (actually slightly wider after traversing the delay line) must be within the 2µS window to avoid triggerring the M flip-flop inappropriately. The longer W1 delay is centered around 635µS (measured 635.5). The shorter W2 delay is centered around 595µS (measured 595.5). M set input Monroe 925 Calculator Section: Memory Timing Diagram Page: 6 Rendition: Dec 23, 2023 0µS 1µS 2µS window for pulse reception 2µS 610 660 20 State Diagram Lines represent state transitions occuring at the end of a full number cycle. State Actions 1 Shift X left till aligned with selected DP 2 - KAS 2 - Mul,Div ? Swap X <–> Y 3 - KN: 3 - KRM 3 - KMD Shift X left, KN–>X[LSD] Copy A –> X Copy X –> Y 4 - Add 4 - Mul,Div Copy Y –> X X–>Y, B–>X, if KAM: A+X–>A 5 Shift Y, B & C left as unit 6 - KAS 6 - Mul 6 - Div If KAM: A±X–>A --Y[MSD], if no borrow C+X–>C C-X–>C, ++B[LSD] 7 - KAS 7 - Mul 7 - Div Y±X–>Y Cear or ++ Y[MSD] C+X–>C (restore) Monroe 925 Calculator Section: State Diagram Page: 7 Rendition: Dec 23, 2023 idle 0 KAS•MD 1 KN KRM 2 KMD KAS 2 3 3 3 6 7 4 6 5 7 5.6K 1 2SC641 56K 100K 5.6K 3 9 IC111 47pF 47pF 8 47pF 1K 5 47pF 4 IC111 56K 47pF 13 47pF 12 IC111 6 5.6K 11 N119T N215T 47pF 4 8 ØR 47pF 47pF 56K ØR 5 1 2 IC113 4 6 47pF 2 47pF 6 9 10 IC110 47pF 1 IC110 3 22K 22K 11 1 IC109 ØS0 9 IC120 3 N115T N207B 47pF ØR 12 IC120 nØS4 6 47pF 47pF 1 IC121 12 IC114 22K 9 10 IC114 47pF 8 1 2 IC114 47pF 3 5 4 IC114 nØS0 47pF 6 47pF 22K 5 3 47pF 22K 10 8 10 9 IC246 47pF 8 nØD0 12 13 IC214 47pF 5 4 1 IC115 2 4 IC121 12 IC122 11 n4 1 n2 10 6 9 IC122 8 4 n1 2 470pF N117T N213T N116T N212T 6 11 13 IC246 47pF 13 12 10 IC213 9 47pF Rendition: Dec 23, 2023 9 IC121 2 1 8 2 IC122 3 12 IC119 47pF 13 12 IC121 9 IC119 4 IC122 1 IC119 11 DIGIT 6 DIGIT 10 11 to display 8 DIGIT 3 DIGIT 7 DIGIT 11 DIGIT 4 DIGIT 8 DIGIT 12 3 5 4 IC119 6 22K n2 6 DIGIT 2 DIGIT 13 2 n8 5 11 DIGIT 9 10 47pF ØB0 DIGIT 5 13 9 10 IC118 8 22K nØD1314 8 13 nØB0 12 IC118 560 11 22K N111B N215B N108B ØD1314 N214B 22K 8 47pF ØN0 22K 10 9 IC203 8 470 5 4 1 IC213 2 22K 47pF 6 nØN0 13 IC203 nØB0 11 47pF 47pF 22K ØD15 nØD15 13 12 10 IC202 9 ØDO 8 nØB0 12 22K 22K Monroe 925 Calculator 1 DIGIT 1 47pF nØD0 12 22K Section: Timing Page: 8 8 ØN1 ØN2 ØN3 nØN3 nØD0 47pF 13 3 10 47pF 6 9 IC214 n2 22K 22K 2 IC214 13 12 10 IC115 9 nØS0 22K 22K 3.9K n8 22K ØB3 nØB3 22K 11 nØS0 1 470pF 22K 13 4 IC214 3.9K n8 n1 5 22K 47pF 11 22K 22K 47pF 2 22K ØS4 22K 22K 470pF n4 13 2 4 IC109 n2 8 nØS0 5 8 3.9K n4 4 10 2 12 IC110 1 6 8 47pF 13 5 IC110 5 IC120 22K 47pF 22K 470pF 22K N109B N217T 22K 3.9K 4 4 ØR 47pF 13 10 12 IC113 9 n1 3 8 5.6K N117B N208B 22K 1 IC120 nØB0 2SC641 330pF 15K 330pF 2 10 2 IC111 1.8K 47pF 2.000 MHz 22K ØW 5.6K 560 5 4 1 IC202 2 6 N219T N106B nØDO AM K N311T 5.6K N310T 5.6K KAM nKK 47nF C DP 0 1 2 3 4 5 6 7 8 9 N309T nKP N310B nK0 N309B nK1 N308B nK2 N307B nK3 N306B nK4 N305B nK5 N304B nK6 N303B nK7 N302B nK8 N301B nK9 CI 10 9 IC220 0 1 2 3 4 5 6 7 8 9 0 2 4 6 8 1 3 5 7 9 2 3 5 8 9 4 6 7 8 9 5 6 7 8 9 5.6K N306T nKC 5.6K nKCE N307T 10 8 FN 9 IC221 8 nKPFN += 5.6K N302T 4.7nF A nKADD –= 5.6K S A S 3 13 12 IC220 × KNP 11 N304T M nKMLT nKNP ÷ N305T RM N308T nKRM 2 IC246 5 IC220 1 IC221 N204T N102T N205T N103B N202T N103T 5.6K N201T N104B nKN1 nKN2 FG CC0 nKK nKN4 nKC nKNW 1 2 IC222 13 SUB 3 5 5.6K 4 IC221 nSUB 6 D 4 M 5.6K KAS 6 2 S nFU RM KRM 3 4 D nKDIV 5.6K 1 4.7nF nKSUB 1 2 IC220 5.6K N303T RM 5 IC211 MLT 6 2 12 1 IC211 nMLT 3 M 10 D 9 IC211 DIV 8 1 12 13 IC211 2 IC210 3 11 MD 4 5 IC210 6 nMD 5.6K M nKMD D 5.6K A S RM 0.1 nKNP 4.7nF 10K 10K nFOF nKPFN 4 5 IC212 6 2 1 IC212 FIU 22K 3 68pF nKPFN 13 FU 12 IC212 11 9 10 IC212 8 nØN0 68pF Monroe 925 Calculator Section: Keyboard Page: 9 22K Rendition: Dec 23, 2023 nFU CC6 1 DL=PC 2 IC218 KAS nMLT DIV nKK 4 5 IC219 12 1 2 IC219 13 IC219 3 nFJ 3 FU 9 10 IC219 5 3 IC206 4 11 6 nMD CC7 FG PC=0 CC1 DL=PC KAS 5 4 IC217 3 9 10 IC217 11 12 1 FU 2 13 IC218 IC217 12 13 CC1 DL=PC 9 10 IC218 47pF 6 4 5 IC218 22K SF1 nCC5 nCC3 CC7 nDL=PC nKNP CC3 8 FCCn 13 12 IC208 1 11 47pF 9 10 IC208 n1 8 22K 6 11 10 IC206 9 n1 n2 n4 nØN0 RF1 nKMD 13 1 IC206 2 1 n2 n4 13 2 IC205 1 n1 2 n4 6 9 11 IC205 10 1 2 n4 8 4 3 IC204 5 n1 n2 4 11 22K 8 2 SF2 1 IC207 47pF nCC5 2 3 nCC3 nCC7 5 47pF 4 IC207 RF2 n2 6 22K 22K nCC2 10 11 IC204 9 n1 2 4 nØN0 5.6K 1 2 IC204 13 1 n2 4 5 3 IC205 4 1 2 4 47pF 22K 11 9 IC216 8 11 8 8 6 6 12 11 2 1 IC203 6 47pF 12 13 IC210 11 nFN (A) 22K CC7 PC=0 CC2 (A, P) 5.6K 68pF SCFG 10 9 IC209 8 FG (K) nØN0 nCC2 MD nKMD CC3 (P) 5.6K 47pF RFG 12 13 IC209 11 nFG (A) 22K CC4 (P) nCC5 ACA CC5 (M, A, P) nØD0 47pF nCC6 4 SFJ 6 22K CC6 (A) 3 5 IC209 6 FJ (A, P) nØN0 nCC7 1 2 IC215 FN (K) 22K 3 5 4 IC203 8 22K 56K 8 9 IC210 CC1 (M) nCC4 (P) 13 12 IC215 5.6K RFN nCC3 4 5 IC215 nCC2 nKC nKMD nCC2 12 10 9 IC215 CC0 (K, M, P) nCC1 (P) 12 13 12 IC216 10 nØN0 10 8 nCC2 nCC6 nKCE nKMD CC7 (A) 4 8 2.2K 12 IC221 47pF 10 9 IC207 13 5.6K RFJ 47pF 22K 1 2 IC209 3 nFJ nKPFN nØN0 47pF nCC4 nMLT 12 13 IC207 n4 11 22K DL=PC FJ CDA nØB3 ØD15 nØD1314 ØN0 CC3 2 1 IC231 2 IC241 CDA (M, A, FOF) 3 KNP ØN3 CC3 KRM ØN2 CC4 MD Section: Control Page: 10 Rendition: Dec 23, 2023 12 IC123 10 11 9 IC123 22K 8 MOF 5.6K nØS0 OFD 8 N113B N213B 47pF 2 1 IC208 3 nFG nMLT 9 10 IC228 ØN0 CC2 8 ØN0 CC4 11 9 IC222 10 8 3 4 IC225 5 6 4 5 IC227 3 1 2 IC227 13 2.2K nKCE CDC (M, P) ØD15 ØN0 CC6 MLT ØN1 CC6 DIV 6 CC1 12 CDD (M,A) ØN0 CDA 13 12 IC228 CDB (M, P) ØN0 CC7 nMD 11 KNP 3 5 IC230 4 10 9 13 IC223 12 2 1 IC230 13 4 IC208 6 CDE (M, A) 6 8 SFJ (A, FJ) 12 1 2 IC228 3 nCDG (M) 5 4 IC228 1 6 FOF (D) 5 10K 1 3 nFN Monroe 925 Calculator 13 11 10 13 12 IC232 9 2 IC239 3 CDG (M) nFOF (FU) 2SC641 SD1 CDG X CDD CDC nKCE 1K 5 4 IC239 13 9 10 IC237 12 6 5.6K 4.7nF 5.6K 9 IC239 red nØS0 nØS4 2SC641 ØR ØW 56K 5.6K ACOUSTIC DELAY LINE white W1 red W2 white 1.8K 5.6K 2.7K 2.7K 2SC641 2SC641 2SC641 33K 2SC641 0.001 56 470 2SC641 ØS0 10 11 33 10V MS0D nCDG 13 IC239 5.6K N208T 4.7nF 33K 11 CDE 12 4.7 1W N110B 8 33 10V 1K 0.001 33K R 10K 33 10V 560 2.7K 0.01 2.7K 33 10V 2.2K 5.6K 8 –Vcc 30 0.5W 470 2SC641 5.6K AD ØS4 ØR ØW 10K 10 33pF 10K 2SC641 10K 9 IC112 8 2.7K 2 33pF 10K N119B N210B 1 IC112 3 2.7K MR 5.6K 2.7K 13 IC112 ØR ?pF 5 33pF 2.7K 4 IC112 11 6 X 6 1 82pF nMR N120T N209B 10K 5.6K 2.2K 5 IC233 ØS4 ØR 12 10K 4 82pF 10K 10K 2.2K 2 IC233 3 nX 10 9 IC234 82pF 8 Y ØS0 82pF 13 12 IC234 11 10K 12 nX 13 IC233 11 MOF 10 CDA ØD0 ØB0 ØR 5 4 2 IC232 1 N206T N113T 6 5.6K nLDSDK CC5 X nFU CC0 X CDG CDB 4 5 IC231 5 4 IC222 3 13 2 IC238 1 N209T N104T nKN4 5 IC105 68pF 12 Rendition: Dec 23, 2023 6 nØS0 47pF nKN2 1 IC106 3 68pF 3 22K 47pF 22K 68pF 22K 22K 2 nØS0 1 22K 68pF 22K 22K 4 2 IC105 Monroe 925 Calculator Section: Memory Page: 11 nG-SD 68pF 22K 22K 6 6 220pF 68pF nKNW Y 9 IC233 X 5.6K 47pF nKN1 22K 2 1 IC107 3 nØS0 5 4 IC106 68pF 6 22K 22K 47pF 2 1 IC108 2.7K N112B N211T 3 SD1 nØS0 5 4 IC107 68pF 6 5 4 IC108 6 22K SD2 nSD2 SD4 nSD4 SDW nSDW 8 Carry Flag 22K KAM ØN3 MD CC4 nMD CC6 4 5 1 IC247 2 6 CDE 11 SUB 8 nSUB N312T % 11 KRM nMD CDD 8 5 4 IC246 11 9 IC238 10 G-y X 6 nFCA 47pF ØB0 ØD0 9 IC240 8 3 5 IC238 4 2 IC236 3 8 6 SD1 nØN3 CC5 1 5 4 IC237 2 11 9 IC225 10 Carry Half-Adder C 13 Operand Half-Adder nB 10 IC236 12 IC235 1 9 4 IC236 12 4 5 1 IC223 2 1 10 8 8 1 2 IC225 13 11 10 IC230 9 5 Y 9 10 12 IC226 13 N106T N210T 8 11 nX 6 9 11 IC227 10 ØD15 ØN0 CC7 MLT 2 IC235 3 8 5 IC235 6 12 13 IC236 nA 10 11 9 IC235 6 8 4 IC234 ACA 6 N203B N202B N204B N206B N205B N105T N112T N105B N114T N107B SW N312T % N313T 11 IC237-2 % modification as wired. 13 IC201 SUB nS4 SW 5 4 IC103 nS2 ACA S4 6 2 1 IC103 S4 1242 Sum Correction 3 13 12 IC103 11 OK SW S4 nS4 22K 3 5 IC117 47pF 1 6 2 IC117 22K Rendition: Dec 23, 2023 8 9 10 IC103 8 47pF 68pF 6 2 IC102 3 S4 nS2 nS1 11 10 IC104 9 8 nS4 S2 S1 2 13 IC104 1 12 4 5 IC102 ØB3 8 S1 13 12 IC117 11 13 IC101 11 9 10 IC101 8 68pF 22K OK 12 9 IC116 8 nØS0 nOK 11 nS1 22K 10 47pF 47pF 5 4 IC116 6 nØS0 13 12 IC116 22K 6 13 IC102 12 nØS0 22K 22K Monroe 925 Calculator 3 10 IC102 9 IC117 ACA 1 22K 10 9 6 5 4 IC104 3 nACA S2 nS2 nOK OK 22K nØS0 5 nOK OK 4 1 Section: Arithmetic Page: 12 5 3 6 12 nØN3 4 IC101 2 8 1 IC234 nKC N313T 2 IC101 6 6 4 IC224 CC5 % modification as specified on note inside case. nACA nOK 11 4 5 nØN3 6 SFJ 13 IC240 8 1 5 2 IC226 4 CC2 nØN0 nØN3 2.2K 9 IC109 12 6 9 10 IC241 nFG nFN CDA 1 2 IC225 3 10 nG-FCA 22K 4 IC241 ØN1 CC7 DIV 12 IC201 N218B N109T 8 5 13 IC241 11 nØS0 22K FJ ØN1 CC6 MLT 13 9 10 IC201 12 IC109 47pF 6 CC6 nSUB nØN3 3 ØN1 12 13 12 10 IC247 9 4 IC118 2 IC118 ØD15 13 5 1 ØB3 47pF 11 22K 68pF 22K 1 2 IC116 3 AD CDC nCC4 CC5 DIV CC5 MLT CC2 MLT CC3 FJ KNP ØD15 12 13 IC231 11 nØD15 9 10 IC224 5 4 IC229 3 4 IC201 3 1 IC240 8 12 IPC 4 IC240 13 IC244 11 CDB nKCE 8 1 56K 9 100pF 22K 10 IC244 8 n1 22K 4 2SC722 5 IC244 6 2 47pF 2 1 IC224 11 nØBO 22K 10 11 IC229 9 FPCn 12 56K 6 3 nØD0 PC=0 6 100pF 22K 5 ØN1 8 6 22K 1 2 IC229 13 nFU CC0 nKCE 2 13 12 IC224 2 IC201 9 10 IC231 5 1 1 3 47pF 2 IC244 3 n2 nCC1 22K 22K 10 9 IC245 8 3 47pF 12 47pF 13 IC245 11 n3 22K 22K 2 1 IC245 3 4 47pF 5 47pF 4 IC245 22K Monroe 925 Calculator Section: Decimal Point Counter Page: 13 Rendition: Dec 23, 2023 6 n4 n1 2 n3 n4 13 12 10 IC243 9 1 2 n3 n4 1 2 4 IC242 5 n1 n2 3 n4 10 12 13 IC242 9 n1 n2 n3 n4 1 2 4 IC243 5 1 2 3 4 N312B 8 nPC=2 N313B 6 nPC=3 2 3 4 N311B nDL=PC 2 1 IC216 3 DL=PC N314B 8 nPC=4 5 6 4 IC216 6 PC=0 N203T N110T nØB3 DP to display Ebb/2 nX N207T N108T 22K 9 IC108 nØBO 100K 10 3.9K 8 W n2 47pF 10 of 2SC780A n4 12 X 47pF N211B N107T 13 IC108 11 nW 22K 3.9K 22K nSDW 2 9 10 IC105 8 4 nW 47pF nØBO 12 47pF SDW 13 IC105 11 n4 22K nSD4 nW 13 11 2 47pF 2SC857 E /2 bb 100K 3.9K n4 9 IC106 8 n2 22K 22K 0.5W from Timing W 10 47pF SD4 DIGITS 12 to 1 (LSD) Ebb Ebb/2 4 12 IC106 nØBO DIGIT 13 (MSD) 3.9K 22K 3.9K Ebb/2 n2 W JRC 0 2 4 6 8 . B-5755 1 3 5 7 9 100K 3.9K 2 4 22K SD2 9 10 IC107 nØBO 47pF nSD2 2SC780A 13 IC107 5.6K 10K 11 2SC780A Rendition: Dec 23, 2023 22K 2SC780A DP 2SB857 2.2K 39K FOF 33 10V Monroe 925 Calculator OVERFLOW 330pF 51K 22K Section: Display Page: 14 39K Ebb/2 nØDO 12 47pF Ebb 10K 8 N218T N111T 10K red POWER black 1 AMP. 115VAC 13W 0.001 5.1K 190 VAC 4.7 350V yellow blue 0.001 white Ebb +185V 51K 1W 470K ? Ebb/2 +80V 51K 1W 1 AMP. green 15 VAC 2SB377 220 16V 4.7nF 2200 10V 2SD77 1K 4.7nF N222T Vcc +5V 33 10V 4.7nF N222B 33 10V 1.8K 33 10V N121B blue Vcc N121T 2SD77 1.8K –Vcc 470? 220 16V N118B 33 10V TR-5S –Vcc –5V N122T N122B N221T N301T N221B N314T 14 14 14 14 14 14 SN3920 SN3925 SN3931 SN4553 SN4554 7400 dual 4-input NAND quad 2-input NAND triple 3-input NAND dual 4-input NAND quad 2-input NAND quad 2-input NAND 7 7 7 7 7 7 104 113 115 203 209 210 211 212 215 220 224 228 233 234 244 245 246 111 223 226 232 237 242 243 247 101 102 103 105 106 107 108 114 116 117 118 123 201 207 208 214 216 218 219 221 231 235 236 239 240 241 204 205 206 217 222 225 227 229 230 238 202 213 109 110 112 119 120 121 122 Unused Gates 1 2 IC123 3 4 Monroe 925 Calculator Section: Power Supply Page: 15 Rendition: Dec 23, 2023 5 IC123 6 SN3900 / 4500 Series DTL IC Pinouts 14 13 12 11 10 9 SN3900 / 4500 Series DTL Gate Construction SN3920 SN3925 SN3931 SN4554 8 Vcc +5V SN3920 SN4553 Discrete Gate Construction A few gates are constructed from discrete diodes and resistors. The internal construction of these gates is shown in the following diagrams. A wire–AND construction is indicated by the input line traversing the width of the gate. AND Gate AND Gate with ʻwiredʼ input Wired-AND Gate 1.75K 2K 0V GND 6K Output 1 2 3 4 5 6 7 Inputs 14 13 12 11 10 9 8 Expansion Input 3K SN3925 SN4554 7400 Vcc +5V OR Gate SN4553 0V GND 1 2 3 4 5 6 7 14 13 12 11 10 9 8 Vcc +5V 1K 850 2.75K 1.85K 150 Inputs Output 2K Expansion Input 630 SN3931 0V GND 1 2 3 4 5 6 7 Monroe 925 Calculator Section: IC Pinouts and Gate Construction Page: 16 Rendition: Dec 23, 2023 N1 N2 Board 1 (top board, component side) 109 110 N1 111 DIGIT 13 N2 T B T B GND 22 22 GND Vcc 22 22 Vcc Vcc 21 21 Vcc GND 21 21 GND nMR 20 20 113 ØR 19 19 M R 122 - 18 18 –Vcc 108 114 ØB0 17 17 ØS0 112 121 nØB0 16 16 - 115 107 120 106 N122T (top, component side) N122B (bottom, solder side) 123 ØS4 15 15 nACA 14 14 nLDSDK 13 13 OFD S W 12 12 SD1 105 119 118 101 102 103 104 116 117 DIGIT 1 N101T N101B 246 212 211 210 209 208 221 220 219 207 218 206 216 217 205 204 215 203 202 214 201 (top, component side) N301T (bottom, solder side) N301B 231 247 230 229 228 227 226 225 224 223 222 N201T N201B N314T N314B 245 244 243 242 241 240 239 238 237 236 235 - 16 16 ØR 15 15 nØD15 - 14 14 ØD1314 ØB0 13 13 OFD nØB0 12 12 SD1 11 11 X DP 10 10 MS0D nFCA 10 10 M R nG-FCA 9 9 nØS0 nG-SD 9 9 nMR nX 8 8 nØD15 MS0D 8 8 ØS0 X 7 7 ACA nX 7 7 ØS4 nFCA 6 6 nØD0 nLDSDK 6 6 nACA 5 IC235-8 (A) nKN2 5 5 ACA nG-SD 4 4 nKNW nKN1 4 4 IC235-8 (A) nKN4 3 3 nKN2 DP 3 3 IC235-3 (A) nKN1 2 2 - nKN4 2 2 SW - 1 1 - nKNW 1 1 - 213 N222T (top, component side) N222B (bottom, solder side) 232 FOF 18 18 nG-FCA nØS0 17 17 - FOF 11 11 ØD1314 IC235-3 (A) 5 Board 2 (bottom board, component side) - 20 20 nØD0 19 19 - 234 233 • Bold-faced expressions are signal sources. N3 B T nK1 1 1 GND nK2 2 2 nKADD nK3 3 3 nKSUB nK4 4 4 nKMLT nK5 5 5 nKDIV nK6 6 6 nKC nK7 7 7 nKCE nK8 8 8 nKRM nK9 9 9 nKDP nK0 10 10 nKK nDL=PC 11 11 KAM nPC=2 12 12 nPC=3 13 13 - Monroe 925 Calculator Section: Physical Layout and Connectors Page: 17 Rendition: Dec 23, 2023 nPC=4 14 14 GND