Reference / Paper · 2026
A 33-page theory of operation of the IME 84: the 20 kHz clock and digit cycle, core read and write, decade-counter arithmetic, the procedures for each key, and notes on replacing germanium parts (BAT46, 2N3906, MPSA92).
IME 84 Calculator Theory of Operation bhilpert / madrona.ca 2025 Oct Rendition: 2026-Mar-29 Contents Introduction ...........................................2 • Architectural Overview ..........................2 • Relation to Mech. Calcs & IME 86 ........2 Sequencer Procedures .......................18 • PREPARE-MULTIPLY .........................18 • TOTAL .................................................19 • RECALL ..............................................20 • Nn .......................................................21 • IM ........................................................22 • RM ......................................................22 Electronic Implementation of Logic ....5 • Logic Nomenclature ..............................5 • Gates ....................................................5 • Flip-Flops ..............................................5 • Pulsers & Asynchronism .......................5 • Semiconductor Replacement ................6 Synchronised Procedures ..................23 • NUMERAL-ENTRY .............................24 • ADD/SUBTRACT ................................24 • MULTIPLY ...........................................25 • DIVIDE ................................................26 Timing & Data Elements .......................7 • Timing ...................................................7 • Digit Memory (Core) ..............................8 • Number Registers ...............................10 • Transfer ..........................................10 • Shifting ...........................................11 • Arithmetic ............................................12 • DP Counters .......................................13 • Negative Flag ......................................13 • Overflow Flag ......................................14 Appendices ..........................................28 Appendix 1: Core Cycle Scoping .......28 Appendix 2: Core Sense Scoping ......29 Appendix 3: Engineering Mods ..........30 • MOD196X.A: Stabilise FSM7 ..............30 • MOD2026.01: KNn Pulser Margins .....30 Procedures ..........................................15 Keypress Procedures .........................16 • CLEAR Procedures .............................16 • REGISTER-SELECT ...........................16 • DECIMAL-POINT ................................16 • PREPARE-DIVIDE ..............................17 Appendix 4: User-Interface Mods.......31 • MOD2025.11: DP Display for Sums ....31 • MOD2025.12: Clear RA for Div & Nn . .31 • MOD2026.02: Clear RK for RM ..........32 1 Introduction The IME-84 is a desktop calculator from the early 1960s, implemented in discrete-component electronics. A schematic - with interpretation to logic and block & timing diagrams - has been produced based on three sources: • A schematic from a reverse-engineering effort in 1986/7 by Klemens Krause. This schematic is limited to a representation of the discrete electronics. A few errors were uncovered in the process of creating the new logic schematic. • PCB photos and examination of IME-84 unit #1.8400903 by Jef Ongena. • PCB photos of an IME-84 unit obtained via the DoPECC website. [https://dopecc.net]. This commentary has been produced from analysis of the new logic schematic. [reference]: Text within square brackets is a reference to some page, figure or logic element in the new logic schematic. E.g. [logic.15] [17.1PL]. Architectural Overview The IME-84 is a digit-serial design. At a functional architectural level, data processing involves 4 registers, each holding a 16-digit decimal number comprised of 4-bit BCD-encoded digits, and several decade counters. Arithmetic is performed in the counters via counting algorithms, not binary arithmetic. The digits of the 4 registers are implemented in a magnetic core memory. The control and sequencing of the higher-level arithmetic and entry operations is implemented with a monostable-based sequencer, assorted flags, counters and ad-hoc logic. Relation to Mechanical Calculators & the IME 86 As one of the very earliest electronic desktop calculators, the IME-84 took many design cues from the mechanical calculators of the day. Beyond the mentioned counter-based arithmetic the most noticeable inheritance is in aspects of the user interface. Mechanical calculators had significant shortcomings around matters such as decimal point management and handling of negative numbers. Additional complexity would have been required to deal with these in a more thorough manner, in already mechanically complex machines. While the IME-84 made some improvements on these matters, it retained many of the shortcomings. The IME-84 preceded the IME-86 in the market by around 2 years. The two models appear quite similar as seen from the exterior and in the internal construction. The 86 however, is not simply a few minor improvements on the 84. The 86 would take significant steps away from the mechanical heritage: • Keyboard The 84 mimics the keyboard interface and register structure of mechanical calculators, as seen for instance in the two "=" keys - one for multiplication, one for division - and effectively a third in the "*" key. The "*" is a direct inheritance from mechanical adding machines where it meant "Print Total", not the modern computing-language use as a 2 symbol for multiplication. The 86 steps away from these anachronisms, towards a simpler, more flexible and more intuitive keyboard interface. • Decimal Points Decimal point management in the 84 was limited. There are two DP position counters: one for the keyboard entry and one for the result. Values in registers could thus have different DP positions but inconsistencies can arise when transferring values between registers. DP management in the 86 is much improved. The DP position is the same for all registers, the position may be moved by the user in the course of operations, with consistency being maintained between all the registers. • Signs In the 84, there is a single sign flag - applicable only to the result of an operation. The internal 10's-complement arithmetic is exposed to the user at times and the proper presentation of a negative value is not performed until the "*" key is pressed. Negative values will not be dealt with properly in multiplication and division. In the 86, each register has a sign flag and proper handling and presentation of negative values is maintained through all operations. The electronic implementation of logic is largely the same in the 84 and 86. Architecturally though, there are again significant differences between them, some notable ones being: • Digit Cycle In the 84, the digit cycle is variable, being extended for 10 pulses of the master clock for arithmetic counting. In the 86, the digit cycle is fixed, the arithmetic counting period is always included in the digit cycle. • Core Power In the 84, the core drive supply is a typical linear dropping regulator with a resistive divider for V–c. In the 86, the core drive supply comes directly from the main logic supply with V–c derived from the drive currents with a charge pump and shunt regulator. • Core Drive Both models use a 2-wire arrangement for the core, with drive and sense shared on the wires of one axis. The 84 employs a 2D drive scheme: 1/2-current XY addressing is used for write, but unit-current addressing is used for read. The 86 employs a 2-1/2D drive scheme, 1/2-current XY addressing is used for both read and write. • Core Access In the 84, each of the 4 registers has an associated decade counter, and the registers are all being scanned simultaneously with digits continually transferred between core and the register's decade. In the 86, the 7 registers are only scanned and loaded into a decade when it is necessary to do so, with just 3 decades shared between the registers on a need basis. 3 • Execution The procedure execution facilities are significantly different. The 84 has an odd unsynchronised state machine built with pulsers and monostables for some procedures, and multiple counters and ad-hoc logic for others. The 86 is more regularised with two sequencing counters controlling most procedures. Some carry-over similarity can be seen in the PQ Counter of the 84 and the QB Counter of the 86: both sequence the primary loops of multiplication and division in 4 states. 4 Electronic Implementation of Logic The IME-84 is implemented in discrete Ge solid-state electronics. Active components are Ge transistors, primarily PNP. As a PNP-based design the main power supply for the logic is positive-ground, with Vcc = –12V. A base-bias supply of +4.5V for the logic is also present to ensure transistors are pulled into cutoff, to compensate for the forward voltage drop from diodes in the logic. The transistors are used for flip-flops, inverters, a few buffers, and in inverting 'pulsers'. The internal construction of logic elements is presented on [logic.20::22]. Logic Nomenclature • Logic 0 = 0V • Logic 1 = –V • 0-edge = transition from logic 1 to 0, positive-going voltage edge • 1-edge = transition from logic 0 to 1, negative-going voltage edge Gates Gates are constructed with Ge diodes, in a form which may be called "Diode-AND-OR-Logic". This form allows a limited degree of cascading of gates without active devices in-between. 'Wired' gates are also used. Flip-Flops Flip-flops were expensive to implement in discrete form, giving rise to optimisations that appear quite odd in the post-discrete era of integrated circuity. Capacitor triggering was common. The capacitive storage and RC time constants provide a storage element prior to the active transistor flip-flop, in a limited sense functioning as a master stage to an active slave stage. The capacitive storage allows a zero-to-negative hold time for the flip-flop. At the time, this was more economic than full M-S flip-flops. IME-84 flip-flops are formed starting with a standard base-portion of two transistors and associated loopback and bias components. A range of input constructs may then be applied to the base-portion, in single or in multiple. Flip-flop construction is presented on [logic.22]. Pulsers & Asynchronism Producing a fully synchronous design can be costly, with doubled flip-flops and more gates. In avoiding this, the IME-84 design - as with other discrete-electronic logic designs - has significant asynchronous aspects. A readily apparent example of this is the counters all being of ripple form. One of the techniques used in asynchronous designs is the introduction of a circuit element which will be called here 'pulsers'. Pulsers produce a pulse at their output when an edge occurs at their input. These may be used for objectives such as: • To 'soak up' glitches by maintaining assertion for a brief period, so a glitch will not 5 appear as a distinguished edge. • To delay an edge briefly to bridge over a period in which glitches may be occurring, with the delayed edge then triggering some action. • To produce a brief pulse to quickly perform some action. • To disambiguate actions triggered by the same event. • Pulser types There are several types of pulsers to provide different edge response and pulse polarity. Some pulsers also have a gate input which must be enabled first for a pulse to be propagated out when an edge occurs. • Tuning Pulsers do not all produce pulses of the same period. There was some amount of 'tuning' performed in the design to achieve the desired objective of each pulser, as evidenced by the range of RC values used [logic.21,22]. Semiconductor Replacement The Ge diodes and transistors of the implementation may be difficult or inconvenient to obtain more than 50 years after the production of the design. This isn't really much of an issue in effecting repairs as Si tends to be fine for replacements. • Diodes The higher forward junction voltage of Si versus Ge might give rise to a concern around threshold voltages. The concern is that for AND-form gates if the Vf drop were too high, a 0 wouldn’t be able to shut off the transistor the gate eventually feeds into. This cascades where an AND gate directly feeds another AND gate, with an accumulating voltage drop from diodes in series. 'AND gate' here includes many of the multiple inputs of flip-flops which are essentially negative-logic OR gates (AND-form). However, the bases of most transistors are pulled down well below conduction by a bias resistor to V+4.5. This provides some headroom before increased Vf drop would leave a transistor conducting. Simple silicon switching diodes such as 1N914 or 1N4148 may work for most or many gate diodes, however the higher Vf may reduce the engineered tolerance margins. Schottky diodes with their low Vf similar to Ge are the other option. The BAT46 is one suggestion, and has been used in repairs of both an IME84 & IME-86S. • Transistors The following standard Si transistors were used for replacements in repairs of an IME-84 and IME-86S: • Logic transistors: • Core drivers: • Nixie anode drivers: • Nixie cathode drivers (IME84): • Nixie cathode drivers (IME86): 6 2N3906 2N2907 MPSA92 MPSA92 MPSA42 (suggested, not tried) Timing & Data Elements Timing A timing diagram for the major clock signals is presented on [logic.18]. • Master clock Timing begins with an astable flip-flop operating at ~ 20 KHz generating signal ØM. • Digit period By default, the master clock triggers a 2-bit binary ripple counter: the Cycle Counter (ØCC) [FØC1,2]. The 4-stage cycle produced by this counter constitutes a digit cycle or period (delimited by the 0-edge of FØC2=ØD) during which digits of numbers in the main registers are processed. During the ØCC stages several timing signals are produced: • Arithmetic • ØDp A pulse to clear the Register Decades prior to core sense. • ØRp A digit of the each of the 4 main registers is retrieved from core memory into a Decade counter/latch. • ØWp The digit values - perhaps modified - are written back / restored to core. • ØX A selected register digit is enabled for display in one of the Nixie tubes. A digit period may be extended, for performing arithmetic on digit values. The extension is 10 cycles of the master clock inserted in the middle of the digit period, between the read and write. A 0-edge on A_START~ sets flag ØA=1. This halts ØCC, and enables counting of 4-bit decade counter ØAC. ØAC counts out 10 cycles of the master clock - producing signal ØA10 - and then clears flag ØA, inhibiting itself, and restarting the digit cycle. • Digit-of-number The 0-edge of FØC2 represents the end of one digit and the beginning of another. This edge clocks the ØD Counter [FØD1,2,4,8], a 4-bit binary ripple counter. The 16 states of this counter define the digits of a number, from ØD0 (LSD) to ØD15 (MSD). • Up/down The ØD Counter can count up or down, so can scan or process a number from LSD to MSD or MSD to LSD. The default counting direction is up, LSD to MSD. • Number cycle Flip-flop [FØN] is 1-set at the beginning of a number cycle [25.1Nd]. This pauses the clocking of ØDC for one digit period (ØN). A full number cycle is thus actually 17 digit periods in time. ØDC=0 during ØN regardless of counting direction. 7 Digit Memory (Core) The digits of the numbers held by the 4 registers are stored in a small core memory. • Physical The core memory is physically organised as a 2D planar array of 16 • (4 • 4). • Logical Logically, the core memory is a 3D array of 4 registers, by 16 digits per register, by 4 bits per digit. The 16 wires on the digits/register axis will be referred to as digit-lines, the 4 wires on the bits/digit axis as the register-bit-lines. • Encoding The digits are encoded in standard 4-bit 1248 BCD code. • Electrical Electrically, the form is what was referred to in the era of core memory as "2D 2-wire". All the cores on one axis will be accessed during a read cycle with a linear address applied on the other axis. The 16•16 physical array is electrically being treated as 16 words of 16 bits, the 16 bits of a word then being logically treated as 4-bit digits of 4 registers. • Drive policy Core requires bidirectional current drive through the cores, one direction for clear-read, one for set-write. For the 2D form, the core drive policy differs from the usual X/Y 1/2-current drive of more-common 3D core implementations. In the IME-84, during clear-read, all 16 cores on a digit-line are to be cleared-read simultaneously - to clear a digit of all 4 registers and load the Decade(s) of all 4 registers. As such, there is no need to involve register-bit-line selection during the clear-read. The clear-read can be accomplished by driving a full unit-current pulse through the digit-line rather than 1/2 currents on each axis (a unit-current being the current level required to flip the magnetic state of a core). For writing, there is a need to distinguish register-bit-lines, as cores on different register-bit-lines will of course typically have different intended states. A digit-line will now carry a 1/2-current (in the opposite direction to clear-read) while the register-bit-lines carry a coincident 1/2-current for the cores which are to be set 1. [Core Cycle Scoping TOP.28] This drive policy is summarised in the following table: Core Drive Relations Digit-Line Register-Bit-Line Pulse Clear-read +1 sense ØRp Write 0 –1/2 0 ØWp Write 1 –1/2 –1/2 ØWp One benefit of this scheme is the register drivers [MR] only need to drive current in one direction, making them much simpler. For the bidirectional drive of the digit-lines the common end of the wires 8 is connected to a supply of ~ –2.5V while the drivers are capable of switching the other end to either –4.5V or 0V [MD]. • Shared sense With the 2D form, a separate sense wire may be avoided. Rather, sensing can be accomplished using the drive wires of the independant axis, here the register-bit-lines. The magnetic flip which will produce a sense pulse is triggered by ØRp on the digit-lines. As these lines are orthogonal to the register-bit-lines which are observed for the sense pulses, the magnetic field of the triggering pulse has minimal inductive influence on the register-bit-lines and the small sense pulses remain distinguishable from the triggering pulse. The drive policy provides a second benefit here in that there is no need to drive current on the sensing wire during the sensing process, further reducing potential drive-sense conflict. • Sense Amplifer The 16 sense amplifiers are formed from two transistors each. The 1 st transistor is directly coupled to a grounded register-bit wire. An emitter resistor to V+4.5 biases it into the linear region with negative feedback. The collector is AC-coupled to the 2nd transistor. The 2nd transistor has a bias network switched by the strobe input [diode into the bias resistors]. The inhibit state for the strobe input is logical 0. In this state the diode conducts, lowering the bias at the transistor base to some volts below cutoff, its collector thus logical 1. When the strobe input is asserted 1 during the 1 st half of the digit cycle, the bias for the 2nd transistor is raised much nearer to conduction. After the clear-read pulse (ØRp) at the beginning of the digit cycle, a positivegoing sense pulse on the register-bit wire is amplified to produce a negative-going pulse at the base of the 2 nd transistor, pushing it into conduction, and thus a 0-going pulse at the collector. This pulse is ACcoupled into an SK~ edge-set type input for parallel-load of a register Decade. [Core Sense Scoping TOP.29] There are two (known) versions of the sense amplifier, the primary difference being the bias network of the 2 nd transistor. The precise voltage levels at the base for the two strobe states thus differ between the two versions. 9 Number Registers The 4 number registers are each comprised of its 16 digits in core memory and one or two 'Decades', where a Decade is either a 4-bit decade counter with parallel load or a 4-bit latch. The 4 registers are: Number Registers RK Keyboard entry. During multiplication, this is the multiplicand. During division, this is the divisor. RA Accumulator. During multiplication, the product will accumulate in RA. For division, the first-entered operand is transferred to RA to become the dividend. RB For multiplication, the first-entered operand is transferred to RB to become the multiplier. During division, the quotient will build in RB. RM User memory. • Decades The digit contents of registers are continually & sequentially read from core into a decade counter (RrD) associated with each register. While in a counter the value may be altered via counter arithmetic, or cleared. The value is then written back to core to restore or update the digit value. • RK 2nd decade RK has an associated 2nd decade, RKX. This decade is a latch only and does not have counter functionality. It does include a 2 nd parallel-load input for loading numerals from the keyboard. • RB 2nd decade RB also has an associated 2nd decade, RBX. • Transfer One might anticipate that copying one register to another would be accomplished in the common manner of using the arithmetic facilities to effectively perform D=S+0. It is not clear why this sort of method was not used but, in the IME-84 as it is, only the RA and RM registers are able to receive a sum. Instead, copying the contents of one register to another is accomplished with 4 transfer gates. Each transfer gate gates the sense outputs and decade parallel-load inputs of a register onto a single shared 4-bit transfer bus. • Construction Logically, a transfer gate is constructed from two gated pulsers on each bit line - one for input onto the bus and one for output off the bus; both are enabled when the transfer gate is enabled. Electrically, the transfer gates establish a low-impedance AC connection between a register sense-decade circuit and the transfer bus. The AC connection suffices 10 for transporting sense pulses. • Operation In copying one register S to another register D, the first action is to clear D. The transfer gates of both registers are then enabled. This effectively places two sense outputs and up to four decade inputs on each bit-line of the transfer bus. During the subsequent digit cycles, sense pulses from register S trigger-set those decades of both S & D which have their parallel-load enabled. Register D having been cleared prior will generate no sense pulses to confuse matters on the transfer bus. • Shifting The operations of Numeral Entry, Multiplication & Division require the ability to shift appropriate registers. Shifting is performed by a mechanism formed from flip-flop FSHLF and logic controlling the core read and write of the decades for RK and RB. Only RK & RB are available for shifting, selected by SH0B1K. • Enable Shifting is enabled when FPWORK=1 and SHIFT=1. SHIFT=1 when: • Add/Subtract is not being performed, • and either: - the PQ Counter is in state 2 or 3 during M/D, - or, M/D is otherwise NOT being performed. • Action With shifting enabled, FSHLF (Flag Shift Leap Frog) is toggled on the 1edge of ØD and thus operates in quadrature with digit cycles which are synchronous to the 0-edge of ØD. The 4-state sequence thus produced is used to leap-frog a digit value into an adjacent digit using two Decades as the leaping frogs of interim storage: • step 1: load digit (d) from core into one decade (a) • step 2: write the digit from another decade (b) • step 3: load digit (d±1) into decade (b) • step 4: write digit (d±1) from decade (a) • Direction The shift direction (d+1 versus d–1) is determined by the count direction of the ØD Counter. ØDC counts up by default, producing an up/left shift. When PQC=2, ØDC counts down for a down/right shift. • Rotate The shift operation is end-around, it actually produces a rotation of the digits: during ØN at the end of a shift-up number cycle, the MSD which was loaded into one of the decades is written into the LSD, as ØDC=0 during ØN. During a shift-down, the LSD loaded during ØN at the beginning is written into the MSD as ØDC=15 at the first digit step. This is used for benefit in some arithmetic operations, e.g. during Multiply, RB is being shifted down, at the end of the multiply RB digits have been restored to their proper position, and the value thus retained for further use as an operand. 11 Arithmetic & the Digit Cycle The arithmetic logic performs an addition or subtraction with the two operand digits in the RK and RA Decades. The operations performed are: FSUB=0: RAD += RKD FSUB=1: RAD –= RKD This is accomplished with counting techniques, not binary-addition logic. Following is an explanation of the add and subtract process, by example. Given RKD=7 and RAD=5: • Reading An operation condition sets A_START~=1. In the 1 st half of the digit cycle, the RKD and RAD decades are loaded as usual. • Add At the middle of the digit period the 0-edge of ØD~ sends A_START~=0, setting ØA=1 and FRKR=0. During the ØA period, the 10 pulses of ØA10 will clock RKD to perform a full rotation [RKD.INC~]. RKD will roll over after 10-7=3 pulses, the rollover triggers FRKR=1. With FSUB=0 (add) and FRKR=1, ØA10 pulses are enabled to increment RAD. ØA and the ØA10 pulses end after another 7 pulses. The 10th pulse of ØA10 completes a ØAC cycle: on the 0-edge of FØA8, FØA is cleared 0. The net result when ØA ends is: • RKD returns to its initial value of 7 having been incremented 10 times. • RAD has been incremented 7 times from 5, rolling over and ending at 2. • The rollover of RAD has set the Carry Flag FRACY=1. • Writing The normal 2nd half of a digit cycle now proceeds and at ØWp the RKD digit is restored to core (necessary due to the destructive read of core) and the RAD digit modified with the sum written to core. • Carry-in FCYIN is set 1 during the 1 st pulse period of ØA10. If there is a carry-in (FRACY=1) from the previous digit, the 1st pulse of ØA10 increments RAD. At the end of the FCYIN period, FRACY is cleared 0, so is ready for a carry generation from the current digit. • Subtract For subtraction, FSUB=1. During ØA, the behaviour of RKD is the same as for addition. However, incrementing of RAD is now enabled while FRKR=0 with the exception of the FCYIN period - thus from the 2 nd pulse of ØA10 till the RKD rollover. The exception is tied up with the borrow strategy. • Borrow A borrow necessitates one less increment of RAD. The FCYIN exception produces this borrow by default. As the carry flag produces an increment of RAD, if the carry flag is set such that its assertion indicates 12 the lack of need for borrow, the carry increment will compensate for the default borrow. When subtracting, rollover of RAD indicates no borrow is necessary. For example, for (5–2): RAD=5,RKD=2, the 5 will be incremented 8 times producing RAD=3 and FRACY=1. FRACY is as desired for providing the compensating increment to the next digit. For (5-6): RAD=5,RKD=6, the 5 will be incremented 4 times producing RAD=9 and FRACY=0. With FRACY=0, the default borrow is effective in the next digit. An initial increment of RAD is generated for the first digit [ØD0 to AND gate], this compensates for the missing increment in that digit. • GT Mode With the Memory Mode switch set to the GT position (Grand Total), all arithmetic increment pulses directed to RA are also directed to RM, thus all additions & subtractions performed on RA are also performed on RM. DP Counters There are two 4-bit hex counters present for decimal-point management. DPKC stores the digit position of the decimal point for the number in the RK register. DPRC stores the DP for operation results. • Enable Pressing of the DP key sets FDPKE=1, enabling DPKC & DPRC to count numeral entries. • DPKC Once enabled, DPKC will increment on each entry of a numeral, • DPRC DPRC will similarly count on each numeral entry, however it may either increment or decrement. The count direction is determined by the operation about to be performed: • Multiplication: DPRC continues counting up as the numerals of the 2nd operand are entered, so the result DP will be the sum of those of the two operands. • Division: DPRC counts down, subtracting the DP position of the divisor from that of the dividend. Negative Flag The Negative flag [FNEG] drives the Negative lamp to indicate the result of an operation is less than 0. • Strategy The Negative flag detects whether a borrow occurred out of digit 15 during a subtract operation. Recall from the Arithmetic commentary that a borrow from a digit subtraction is indicated by the lack of rollover of RAD, alternatively stated as the rollover of RAD indicates no borrow. If a subtraction arithmetic number cycle is being performed, at the beginning of the arithmetic period of digit 15, FNEG is set 1 [18.9Nv]. If a rollover of RAD occurs during the digit 15 arithmetic, FNEG is cleared 13 0 [18.15Bf]. • Already negative If a subtraction is being performed from an already negative number, the Negative-Hold flag [FNEGH] is asserted, which then holds FNEG at set1, to inhibit it from being cleared. Overflow Flag The Overflow flag [FOVF] drives the Overflow lamp to indicate the result of an addition or multiplication has overflowed the register capacity. • Strategy A carry out of digit 15 is detected: FOVF is enabled to set during ØA of digit 15 as long as FNEG has not been set and the procedure is not SUBTRACT or DIVIDE. If RAD rolls over FOVF is set 1. 14 Procedures A procedure is a sequence of actions taken to perform some function. IME-84 procedures can be characterised into 3 categories in regard to their mechanism of execution, as presented in the table below. The categories and the procedures in them are described in following sections. List of Procedures Procedure Keypress Sequencer Sync Description CLEAR-ALL • Clear state CLEAR-RK • Clear entry CLEAR-RM • Clear user memory REG-SELECT • Select register for display DECIMAL-POINT • Enter decimal point PREPARE-DIVIDE • Prepare for division PREPARE-MULTIPLY • Prepare for multiplication TOTAL • Present sum, negate if needed RECALL • Copy result to entry Nn • Raise exponent IM • Store in user memory RM • Copy user memory to entry NUMERAL-ENTRY • Enter a numeral ADD/SUBTRACT • Calculate add or subtract MULTIPLY • Calculate multiply DIVIDE • Calculate divide 15 Keypress Procedures Keypress procedures are comparitively simple procedures that - while they may perform multiple actions - do not require state-memory beyond the indication of the procedure. Keypress procedures are not synchronised to the number cycle. Procedure: CLEAR-ALL, CLEAR-RK, CLEAR-RM The CLEAR procedures clear some subset of state in the calculator. • CLEAR-ALL Pressing the C key clears registers RK, RA & RB and assorted other state-holding entities such as the control counters, DP Counters, etc. to bring the machine to a determined state. It does not clear RM. • CLEAR-RK Pressing the Clear-entry (CT) key clears RK. • CLEAR-RM Pressing the Clear-mem (CM) key clears RM. • Register clear Clearing a register is accomplished simply by asserting Rrd_CLR~=0 for the Register Decade(s) for long enough for all the register digits in core to be written. Note this does not require synchronising to the number cycle. Clearing can begin at any digit, as long as the clearing persists for 17 or more digit periods. The operation is reliant on the minimum period of a keypress being longer than 17 digit periods. • Variation A modification was introduced around 1965 whereby the C key would clear only RK & RB, and the CT key would clear both RK & RA. Procedure: REG-SELECT A keypress of one of the 4 Register-Select keys directly sets the state of the RS Latch formed from RS1,2 with a 2-bit encoding of the register. The RS Latch state is decoded to 1-of-4 and used to enable data from the according Register Decade to be applied to the display numeral decoder via the Display Selector. Procedure: DECIMAL-POINT Pressing of the DP key sets FDPKE=1, which enables counting for DPKC and DPRC on each entry of a numeral. • Anomaly DP management does not work properly for addition & subtraction, entering sequential operands with decimal points simply results in a continually incrementing DP position. See MOD2025.11 [page 31]. 16 Procedure: PREPARE-DIVIDE Pressing of the Divide key (÷) enables the RK and RA transfer gates to copy RK to RA, where it will become the dividend in the upcoming divide procedure. When the Divide key is released, RK is cleared by a pulse long enough to clear a register [T19.6,7,8,et al]. • Anomaly RA is not cleared prior to the transfer. If RA is not zero it must be manually cleared before pressing the Divide key. See MOD2025.12 [page 31]. 17 Sequencer Procedures Sequencer procedures are performed by a state machine which will be referred to as the Sequencer. The Sequencer does as its name implies: sequences in time a set of actions. The Sequencer is constructed from a large set of pulsers and 10 monostable flip-flops. The pulsers along with NORN gates in essence form next-state logic, while the monostables are the state-holding entities. In operation, a keypress triggers a pulser to initiate a sequence. The pulser triggers one of the state monostables. When the period of that monostable expires, it triggers another pulser which triggers another state monostable, and so on for as long as the sequence requires. Most of the pulsers have a gate input to conditionally direct the sequence. The notable aspect of this design is that a sequence is entirely dependant on RC timeconstants and is unsynchronised to the master-clock-derived number cycle. This places inherent restrictions on what can be accomplished with the Sequencer. The actions performed by the Sequencer are primarily clearing and transferring registers, both of these are idempotent - the result is the same as long as the state action period is at least 17 digit periods. These actions can begin in the middle of a number cycle and can include a fractional portion of a number cycle. Other actions performed are simple triggered actions, and triggering a keypress at the end of the sequence. In the Sequencer procedure descriptions following, a transfer of one register to another means both registers are placed on the transfer bus (register transfer-gate enabled). The indicated direction of transfer is derived from which register was cleared prior. Procedure: PREPARE-MULTIPLY The Multiply key (X) invokes a sequenced procedure to copy the multiplier entered into RK to RB. PREPARE-MULTIPLY State Action - Press X key S3.3 0 => RB S5.1 RK => RB S8.4 0 => RK (S2.2) 0 => RA • Variation In some units, RA is cleared in preparation for the eventual summing of the product. However, the pulser components that produce S2.2 are absent in some units, thus RA is not automatically cleared and must be manually pre-cleared if necessary. Without a pre-clearing, the product will simply accumulate into RA with its prior contents. This allows sumof-product operations to be performed without requiring or using an additional register. 18 Procedure: TOTAL The Total key (*) presents the result of a series of additions and subtractions by switching the display to RA. If a sum is less than 0 it is natively in 10s-complement form, the Total key (un)complements it by performing a subtraction so it displays as the expected negative value. TOTAL State Action - Press T key State Action if RA current: if RK current: * * select RK select RA if NEG=1: S8.1 0 => RK S1.1 RA => RK S2.1 0 => RA S7.1 trigger KSUB • Subtotal A 2nd press of the Total key (while RA is displayed) switches the display back to RK in preparation for another entry, and complements a negative sum back to 10s-complement form so further entries will accumulate properly into the sum. A double press then, permits a subtotal to be observed in the course of a summation sequence while properly accounting for negative sums. • Suppress count If the Item-Count (N) mode is enabled, a Subtract operation increments the item-count in RM. This increment needs to be suppressed for complementing SUBTRACT procedures instigated by the TOTAL procedure for negative values. The suppression is performed by an AND gate inhibiting RM_INC~ during the FSM7 period [logic.11]. 19 Procedure: RECALL The Recall key (R) retrieves another register for re-use as entry. • If RA is current, copy RA to RK. • If RB is current, copy RB to RK. • Clear RA & RB, and select RK • If neither RA or RB was selected, RK is cleared with no other actions taken. RECALL State Action - Press R key S8.6 0 => RK H1 - State Action if RA current: if RB current: S1.3 RA => RK S5.3 RB => RK S2.1 0 => RA S2.3 0 => RA S3.1 0=>RB select RK Note KR~ is asserted during CLEAR-ALL, and thus the RECALL sequence is also performed by CLEAR-ALL. 20 Procedure: Nn The Exponentiation key (Nn) raises a base N entered into RK to some power n, where n is determined by how many times the Nn key is pressed. This is accomplished with some register copying followed by triggering a multiply operation. Nn State Action State - Press Nn key Action if RK current: if RA current: S3.2 0 => RB S8.5 S5.2 RK => RB H2 S4.1 RB => RA S1.2 RA => RK S8.3 0 => RK S2.1 0 => RA trigger KME S6.1 trigger KME 0 => RK H2 S6.2 • Power 1 If RK is the register selected for display, a press of the Nn key will initiate the exponentiation process. The base entered in RK is copied to RB and RB to RA (RA is presumed to have been cleared prior), RK is cleared, and the multiplication procedure triggerred. The multiplication multiplies RB by 0, so nothing is added into RA. The multiplication displays RA at completion. RA has been preloaded with the base, so the display is effectively base^1. • Power 2+ On each subsequent Nn keypress with RA being the displayed register, the product in RA is copied to RK to enter it as the next multiplicand, RA cleared, and another multiplication triggered. • Counting powers If the Memory Mode switch has been set to N, each multiplication increments RM by 1: The assertion of FPWORK at the beginning of the multiply sets FNINC=1. This enables MF_N to assert during FCYIN of ØD0, which enables an increment pulse to be applied to RM. As MF_N deasserts, FNINC is cleared 0, so only a single increment is performed for each assertion of FPWORK. • Anomaly RA is not cleared on the 1 st press of the Nn key. If RA is not zero it must be manually cleared before starting an exponentiation operation. See MOD2025.12 [page 31]. 21 Procedure: IM The Store Memory key (IM) copies RK to RM and clears RK. IM State Action - Press IM key if RK current: S9.1 0 => RM S10.1 RK => RM S8.2 0 => RK Procedure: RM The Recall Memory key (RM) copies RM to RK. RM State Action - Press RM key if RK current: S10.2 RK <=> RM • Anomaly RK is not cleared prior to the RK<=>RM transfer. If RK is not zero it must be manually cleared before pressing the RM key. See MOD2026.02 [page 32]. 22 Synchronised Procedures Synchronised procedures modify a number value in a register and consequently must be synchronised to the number cycle. For example, a (serial) add must begin at the LSD and not continue after the MSD. There is a small sequence counter involved for some of these procedures but there is no formal state machine governing the overall execution of a procedure, rather, there is some amount of procedure-specific ad-hoc logic. • Debounce Pressing of a numeral key or an arithmetic operation key is debounced with one of two Schmitt triggers [T24.1,2] [TK.1,2,3]. • Syncing Synchronised procedures are initiated by de-assertion of KNML or the assertion of KOP~. The 0-edge of either signal sets FPSYNC=1. This is then synchronised to the