Schematic · 2026
IME 84 Calculator: Reverse-Engineered Schematic
A 26-page schematic of the IME 84 of 1964: germanium DTL, core memory, decade counters and the 16-digit multiplexed Nixie display, with a board list (408 transistors, 1,045 diodes).
Schematic · 2026
A 26-page schematic of the IME 84 of 1964: germanium DTL, core memory, decade counters and the 16-digit multiplexed Nixie display, with a board list (408 transistors, 1,045 diodes).
IME 84 Calculator Schematic Contents Section IME 84 Calculator Section: Title & Contents Page: 1 Rendition: Mar 29, 2026 Page Title & Contents (this page) 1 Notes 2 Block Diagram 3 Timing - Master Clock, M & A Cycle Counters 4 Timing - Digit Counter 5 Keyboard - Operations 6 Keyboard - Numerals & Register Select 7 Control - Sequencer 8 Control - Synchronised Processing 9 Control - Register Controls & Shift Logic 10 Arithmetic 11 Register Decades 12 Register Core Matrix & Drivers 13 Counter Modules & Display Selector 14 Display 15 DP Counters 16 Power Supply 17 Timing Graph 18 Timing Graph - Division 19 Modules - Gates Modules - Pulsers, Buffers & Inverters Modules - Flip-Flops Connectors N1::N17 Connectors N18::N32 Connectors NK, NN, NP & Board List Signal Names 20 21 22 23 24 25 26 This schematic has been derived through reverse engineering. This is not the manufacturer’s schematic. Notes ♦ Gate symbols and signal names are presented in accordance with: logic 0 = 0V, GND logic 1 = –12V Nbb.pp ♦ The symbol denotes a physical connector pin. bb=board, pp=pin. Solid black end is the male side of the connector. White end is the female side of the connector. ♦ Arrows indicate direction of signal or energy flow. ♦ The symbol with no label denotes –12V. ♦ The symbol with no label denotes +4.5V. ♦ These drawings are based on three sources: - Redrawing and interpretation to logic of the reverse-engineered discrete-component schematic produced by K. Krause in 1986-7. - Photos and examination of Unit 1.8400903 by J.Ongena. - Board photos of a unit, from DoPecc. Revision Log ♦ 2025 Sep: Initial drawing / bhilpert. IME 84 Calculator Section: Notes Page: 2 Rendition: Mar 29, 2026 Timing Arithmetic Cycle Counter ØAC ÷10 Power Supply FØA –12V –4.5V +4.5V –100V +100V display supply logic supplies Master Clock Mem. Cycle Counter ØCC /4 Digit Counter ØDC /16 Timing Decoders 4 to 2-of-8 Decoder ØD,ØRp,ØWp, … ØDA,B,C,D ØDa,b,c,d Keyboard KN1,2,4,8 ØDA,B,C,D ØDa,b,c,d Register Selector FRS FRS 1 2 Register Digit Decoder 2-of-8 to1-of-16 Core Array Numeral Encoder Control 2 to 1-of-4 Decoder 16 Digit-Line Drivers FØN FSM1 FPSYNC FSM2 FPWORK FSHLF FSM3 Transfer Bus 4 Reg-Bit Drivers 4 Sense Amps FSM4 Xfr Gate Arithmetic RKD Decade Counter RKX Decade Latch Sequencing Matrix FPAS FSM5 FSM6 FRKR FPML FSM7 4 Reg-Bit Drivers 4 Sense Amps Multiply Secondary Counter MSC ÷10 FBXLD FMBXR FSM8 Xfr Gate RBD Decade Counter RBX Decade Counter FSUB FSM9 FPDV1 FSM10 FPDV2 Division Stage 1 Counter D1C ÷16 FDK15Z FDA15R Primary Loop Counter PLC ÷16 PL Seq. Counter PQC /4 FCYIN 4 Reg-Bit Drivers 4 Sense Amps 4 Reg-Bit Drivers 4 Sense Amps Xfr Gate RAD Decade Counter FRACY Xfr Gate ØDA,B,C,D ØDa,b,c,d FNINC RMD Decade Counter Display Digit Decoder FNEGH FDPKE Negative Lamp Overflow Lamp FNEG DPK Counter FOVF FDPRD DPR Counter Display Selector IME 84 Calculator Section: Block Diagram Page: 3 Rendition: Mar 29, 2026 ØN FRMCY 16 Digit Anode Drivers DP Anode Driver logic state interface Numeral Decoder 10 Numeral Cathode Drivers 16 Nixie Displays 6543210987654321. I/O multiple signals 4-bit data bus KC~(29b) FPWORK MPPAE SHIFT FPWORK 20A-0 R~ ØA COUNTER FØA1,2,4,8 !! duplicate diode 23A-0 25A-2.2 A_START~ N20.U N25.K N29.U K~ DIV10 Master clock N23.L N6.L 24.9Nd ØM~ 24A-2.2 N24.K N29.S N25.H N25.J SE~ -f Q FØA T25.6 7 RE~ -m Q~ N25.S N18.D 4K7 ØA 5µ 10n N25.V N18.H ØA10 N23.C ØA~ 1K 10K 200p* 6K8 200p* 1K ØM N23.T N30.Y N25.M T25.4 T25.5 Q 25A-2.2 T~ -m FØC1 T25.9 8 Q~ N17.V Q FØC2 T~ -m T25.11 10 Q~ ØD N25.W N8.M N24.L N9.M ØD~ N10.M N11.M N25.B 25.15PH N2.J ØDp N3.J N4.J N5.J N6.J N7.F ØCC=0 25A-1.5 ØN~ 25.14PH 25A-2 N25.C N13.J ØRp N14.J N15.J N16.J 25.13Nd 25A-2 N25.D N13.K ØX N14.K N15.K N16.K ØCC=2 25A-1.5 25.12PH N25.E N8.F N9.F N10.F *ØM capacitors: K87: Both 200p. #903, DOPH: T25.4.C=1n, T25.5.C=2n N11.F N13.H N14.H IME 84 Calculator Section: Timing Page: 4 Rendition: Mar 29, 2026 N15.H N16.H ØWp FPQ2 FPQ1~ UP~ (PQC≠2)~ 17A-1 DOWN~ (PQC=2)~ 17.9Nd TG~ -gg Q ØN~ ØD 17A-2 T~ -g TG~ -gg TK~ FØD1 T17.1 2 Q FØD2 T17.3 4 Q~ TK~ TG~ -gg TK~ Q TK~ FØD4 T17.5 6 Q~ TK~ TG~ -g Q ØD0 500p FØD8 T17.7 8 Q~ TK~ TG~ -g 25.1Nd SE~ -x Q FØN T25.2 3 Q~ ØD RE~ -n Q~ N25.L N18.J ØN N20.L N21.K N22.L N30.K TG~ -g N31.K 1~ 1 2~ 2 4~ 4 8~ 8 ØN~ N25.U N17.W 2 1 17A-6 N17.B N13::16.C ØDd 8 4 17A-6 N17.K N13.B N18.Z ØDD 17A-0 2 1~ 2~ 1 2~ 1~ 17A-6 17A-6 17A-6 N17.C N13::16.D N17.D N13::16.E N17.E N13::16.F ØDc ØDb ØDa 8 4~ 8~ 4 8~ 4~ 17A-6 17A-6 17A-6 N17.J N14.B N17.H N15.B N17.F N16.B N17.M N18.C N22.K ØDB ØDA N17.L N18.Y N20.X N23.B N25.F 2 • (1-of-4) a b c d ––––––––––– A | 0 1 2 3 B | 4 5 6 7 C | 8 9 10 11 D |12 13 14 15 IME 84 Calculator Section: Timing - Digit Counter Page: 5 Rendition: Mar 29, 2026 ØD15 ØDC 17A-0 Major-minor Decoding N23.K ØD0 keyboard daughter board 4K7 76 37 C 60 22K NK.11 N21.A N24.Z KC~ 68K 2K2 68K 2n 15K 2n 10K TK.1 33K TK.2 10K 2K2 A~ +5 S~ KC~ M~ N28.T 100K KA-0 470 TK.3 470n D~ 1K N29.T N30.M N31.M S~ 100 KC~ + KC~(28) N28.Y 28A-0 D~ 22K 62 KPL-a KA-0 24 A~ KPL-a KA-0 15 5µ A~ 100 KC~ 29A-0 59 KPL-a CM 58 * 67 FSM6~ KCM~ 22K 5µ NK.29 N27.K KTOT~ 47K KA-22 NK.74 N27.Y 27A-0 5µ KCT~ M~ 22K 74 22K KME~ KA-4.7 KPL-a KTOT~ A~ 22K 73 KDE~ 5µ D~ S~ KA-4.7 79 22K NK.41 N26.U 5µ : 65 22K NK.25 KDIV~ 80 22K 5µ IM S~ KMUL~ M~ – 5µ Nn N30.A N30.L KDIV~ 5µ N31.L NK.42 N26.X KNn~ 81 A~ KA-0 20 NK.20 N24.M KPL-a 21 NK.21 NK.44 N27.M $DPL-c KIM~ $DA-0 22K NK.43 N27.B TM~ KA-4.7 $D.N KR~ NK.23 N18.L N26.V KC~ N24.S KOP~ KA-0 NK.22 N19.A KASD~ 2K2 6K8 100n T19.8 3K3 2K2 T19.7 5µ 12V T19.6 N19.B N27.D KCLR_RK~ 22K Q~ 22K 5µ KOPAS~ KA-0 Q F$D2 T$D.3 24mS 4 KRM~ KOPDE~ 22K 2K2 22K $D.K 63 N22.F 22 100K R NK.35 S~ KDIV~ 100K RM FSM7a~ 35 KOPME~ D~ KA-22 $D.D 68K 82 22K 64 N21.J 22K KA-4.7 A~ x NK.36 22K KPL-a ÷= 36 22K M~ D~ A_SETADD~ KA-4.7 KC~(29) N29.Y = CT A_SETSUB~ KA-4.7 RSEL_K~ 22K $DPL-d $DA-0 $DPL-d $DA-0 TM~ 5mS Q F$D1 T$D.1 2 Q~ 1K $DA-0 $D.C RAD_CLR~ N30.V 30A-0 • KCLR_RK~ is a 0-pulse of ~ 28mS. • $D: MOD2025.12 Modification to clear RA for division and exponentiation (KNn(K). • 68K R: MOD2026.01 Adjust KNn~ pulse margins. IME 84 Calculator Section: Keyboard - Operations Page: 6 Rendition: Mar 29, 2026 • Keyboard daughter board appears to be a modification to the initial design. With the daughter board these diodes are inactive: KME~ 20 KDE~ 21 22 pulser K7 , 1 2 3 4 5 6 7 8 9 0 57 47 3K3 N30.T NK.4 N7.H NK.3 N7.J NK.2 N7.K NK.1 N7.L KP~ 1 8 48 NK.6 2 9 KA-3.3 KN8~ 10n 4 49 3 5 6 50 4 KA-3.3 KN4~ 10n 7 2 51 5 3 6 52 6 KA-3.3 KN2~ 10n 7 1 53 7 3 5 54 8 KA-3.3 9 55 KNML KN1~ 10n 7 2K2 100 9 NK.5 KA-0 N24.U 100K 500p 470n T24.1 2K2 N24.X N30.U KNML~ 33K 22K T24.2 56 1K RK rd 61 KC~ KA-22 KCT~ KTOT~ KPL-f 10K RSEL_A~ 10n NK.14 N19.S K~ A~ SC~ M~ SC~ N26.Y FSM3 RB yl KR~ 77 47 KA-22 KDE~ N30.F 1~ 2~ Q NK.39 N19.T B~ 470n 69 KME~ KTOT~ K~ RC~ B~ RC~ 78 NK.31 N19.U A~ B~ SC~ M~ SC~ 22K 10K N1.14 N19.C N26.T N27.T 10n NK.40 N19.V M~ K~ RC~ A~ RC~ RSEL_K RSEL_K~ N31.F NK.30 Q~ 68 2~ 19A-0 2~ Q 1 Q~ 1~ FRS1 T19.4 5 KPL-f RSEL_K~ RM wh KA-22 19.12Nd N19.J 2 1 RA gn 19A-0 FRS2 T19.2 3 26A-0 26PL-c FPWORK~ RK = 0 RB = 1 RA = 2 RM = 3 1~ 19.11Nd 19A-0 2 19.10Nd N19.K N1.13 N19.D N26.W NK.46 N19.L N1.15 N19.E N26.S NK.28 RSEL_B RSEL_B~ 84 RSEL_A RSEL_A~ 66 1 IME 84 Calculator Section: Keyboard - Numerals & Register-Select Page: 7 Rendition: Mar 29, 2026 2 19A-0 19.9Nd N19.M N1.16 N19.F NK.45 RSEL_M 83 Sequencing Matrix 1.1T 26PL-d TM~ 26A-0 1.2T KMUL~ 1.2G KTOT~ 1.3T KR~ 1.3G 26PL-d 26A-0 N26.J N27.J FSM1p~ 27PL-c 27A-0 2.1T 26PL-d 26A-0 RSEL_K~ 2.2T 26PL-c 26A-0 RSEL_A~ 2.2G RSEL_B~ 2.3T 26PL-c 26A-0 NEG~ 2.3G FSM1 3.1T FSM2 3.1G Q FSM1 4.1T FSM1 T26.1 2 1.1G 26PL-c TM~ 26A-0 Q~ Q FSM4 TM~ 3.2T FSM4 3.2G FSM5 3.3T FSM2 5.1T FSM2 T26.3 4 KRM~ FSM3 Q 26PL-c 26A-0 26PL-c 26A-0 26PL-c 26A-0 26PL-c 26A-0 TM~ 5.2T Q~ FSM2~ Q 5.3T 8.3T 26PL-d 26A-0 FSM5 8.4T 26PL-c 26A-0 FSM8p~ 26PL-d 26A-0 8.6T 26PL-d 26A-0 9.1T 27PL-e 27A-0 8.5T FSM5~ FSM8 N27.L N26.L Q~ FSM8~ FSM2 FSM7~ 27A-0 !! double-diode N26.F N27.F N27.X NK.19 FSM2 FSM7a~ N18.V N27.H N26.H Q FSM9 Q~ FSM9~ Q FSM10 Q~ FSM10~ FSM8 FSM8 5.3G 26PL-c 26PL-d TM~ 26A-0 Q 6.1T FSM3 T26.5 6 26A-0 6.1G 6.2T Q~ 26PL-d FSM3 FSM3~ 26PL-d N26.Z N27.Z FSM6p~ TM~ Q FSM6 T27.1 2 26A-0 Q~ 6.2G FSM6~ $10.3T 26PL-c 26A-0 H1 22K H.1G 26PL-c H.2T 7.1T 27PL-c 27A-0 TM~ Q H2 Q~ 22K Sequences Triggered Pulsers KMUL: 3.3 5.1 8.4 KTOT(NEG): 8.1 1.3 KR(A): KR(B): 8.6 8.6 KNn (K): KNn (A): 10.1T FSM7 T27.3 4 7.1G 26A-0 H.2G Initiator FSM9 T27.7 8 26A-0 $10.3G H.1T TM~ 9.1G FSM9 Action Description (2.2) FSM1: 24mS RK <=> RA Enable transfer RK & RA 2.1 7.1 FSM2: 5mS 0 => RA Clear decade RAD H1 H1 1.2 5.3 2.1 2.3 3.1 3.1 FSM3: 5mS 0 => RB Select RK if KR Clear decades RBD & RBX Pulse KRK if KR 3.2 8.5 5.2 H2 4.1 1.1 8.3 2.1 H2 6.1 KIM(K): 9.1 10.1 8.2 KRM(K): KRM(K): 10.2 8 via 10.2 $10.3 FSM4: 24mS RA <=> RB Enable transfer RA & RB FSM5: 24mS RK <=> RB Enable transfer RK & RB FSM6: 5mS Trigger Multiply Pulse KME FSM7: • $10.3: MOD2026.02 Modification to clear RK for Recall-Memory. 18mS Trigger Subtract Suppress RM Incr. Pulse KSUB 5mS 0 = >RK Clear decades RKD & RKX FSM9: 5mS 0 => RM Clear decade RMD RK <=> RM Enable transfer RK & RM Pulser 2.2 is absent. RA is not pre-cleared. • K87: PL 91 & 102 are both type e. DOPH: PL 91 is type c while PL 102 is type e. 27A-0 TM~ FSM10 T27.9 10 27A-0 10.2G Destination Destination Pulsers Pulsers Source Outputs 1 1 2 2 3 1 KMUL~ 2 3 3 1 2 G KTOT~ 4 3 1 T 5 1 2 6 3 1 7 2 1 2 4 9 5 KNn~ 6 1 10 1 G G G G T G T G G G G G G G RSEL_B~ G NEG~ G T FSM2 T T FSM3 T T T FSM4 T FSM5 T T T T T T T FSM10 T H1 H2 2 G KRM~ G 1 T G RSEL_K~ H 3 T T KIM~ RSEL_A~ 2 T G FSM9 Rendition: Mar 29, 2026 3 G G G 8 1 G G KR~ FSM8 IME 84 Calculator Section: Control - Sequencer Page: 8 27PL-c 27PL-e 10.2T FSM7~ FSM1 FSM8: FSM10: 24mS 26A-0 Sequencing Matrix Connections Period 6.2 26PL-c 10.1G Actions Mono • #903: Q FSM8 T27.5 6 8.4G FSM8 FSM10 TM~ 8.5G Q~ 5.2G 27A-0 8.2G FSM5 T26.9 10 5.1G 27PL-c 8.2T FSM4~ KNn~ KIM~ 27A-0 8.1G Q~ FSM1~ 27PL-d 8.1T FSM4 T26.7 8 4.1G T T T T T T FPWORK FPML FPWORK FDK15Z FPDV2 FPQ2 FPQ1~ SG~ -y* 20A-10 KNML SK~ KOP~ SE~ -f 20A-10 20.9Nv 20R-0 ØN 20A-3.3 20PL-v FPML 20PL-v RE~ -m N20.B 20A-6.8 SC~ *B22 SE~ -m FPSYNC T24.4 3 20A-10 20A-10 FPDV2~ Q Q FPWORK T24.6 5 RK~ Q~ RG~ -m FPWORK N24.W N20.H N24.V N18.W N23.J Q~ N24.T FPWORK~ N19.H SYNC~ N22.E PQC=2 KOPAS SE~ -m Q FPAS T24.7 8 FPQ2 FPML~ 20PL-p 20A-3.3 FPQ2~ FPDV2~ FPWORK~ 22A-6.8 20PL-p 20A-0 22.11Nv 22PL-s KC~(29) 22A-0 N22.W 10n N29.L PLINC~ 22A-3.3 22PL-w 22PL-w KOPME~ SE~ -f* N22.B 22A-2.2 R~ Q~ PL COUNTER FPL1,2,4,8 K~ DIV16 N29.K N21.H N28.L D1CINC~ PLEND~ RE~ -m Q~ RC~ FDK15Z~ SG~ -m FPWORK~ SK~ R~ DIV16 N28.K N22.D D1CEND~ RE~ -m N21.S N5.L N20.C FPML FPML~ FPML 21A-6.8 FPDV2 21A-6.8 PQC=0,1 Q~ Q RE~ -??c KC~ 21A-2.2 N21.V FPQ2~ FPDV2 N22.H FPDV2 T22.9 10 N22.C N21.T N20.J Q SE~ -m FDA15R~ N21.D FPDV1 T22.7 8 D1 COUNTER FD11,2,4,8 K~ Q FPML T21.5 6 KC~ KC~(28) ØN RE~ -m N20.Z 10K 20A-3.3 FPWORK N20.F N21.L N29.W Q~ RC~ *B29 N22.V N18.E FPDV2~ N19.W RBX_INC~ N20.E KC~(28) FPML FPWORK PQC=0 FPQ2~ 20A-6.8 20.4Nv FPQ1~ N20.V N28.U 3.3K MSCINC~ NK.17 R~ MS COUNTER FMS1,2,4,8 K~ DIV10 N28.S SG~ -p N21.U SK~ MSCEND~ SG~ -p ØN SK~ FPDV2 FDA15R~ 21A-3.3 ØN ØN 21A-6.8 TK~ TG~ -gf Q FPQ1 FPQ1 T21.1 2 Q~ *FPSYNC - SG~: Additional 47K to V–. N21.C N17.U FPQ1~ N19.X *FPWORK - B22: Diode for this Set input is on board 22. N20.K NK.16 *FPML - SE~: Additional 22K to V–. Q *FPDV2 - B29: Diode for this Reset input is on board 29. IME 84 Calculator Section: Control - Synchronised Processing Page: 9 Rendition: Mar 29, 2026 T~ -m N21.E Q~ N17.T N20.D FPQ2 T21.4 3 FPQ2 NK.18 N21.F N20.M FPQ2~ 21R-0 21A-0 21.8Nv N21.W N24.E SHIFTa 24A-2.2 SHIFT FPML~ PQC=3 FPQ2 PQC=0,2 24A-2.2 21A-10 FPQ1~ 21A-10 21R-0 21.7Nv N21.B 24A-2.2 N24.D KD 24.14Ne SHIFT B 24A-2.2 SHIFT FPWORK FPML~ FPQ2 20.8Nv FPQ1~ FPQ1~ 24A-2.2 ØD~ 20A-2.2 20PL-y 220 N20.Y N24.J FPML RKD_PLD~ RKD_WEN N24.B 20A-3.3 ØN FPQ2 24.13Nv BX N24.F BD N24.C 6.9Nv FSM8~ KCT~ KC~ N7.M KA-0 NK.12 N6.S RKX_PLD~ ØDp RKX_WEN 7A-6.8 7.2Nv FSM8~ Q~ KCLR_RK~ RC~ KCT~ RC~ KC~ N4.H 1K N4.M 220 RKX_CLR~ 27A-0 N27.S KA-0 NK.13 N7.S RBD_PLD~ N4.F SG~ -m RBD_WEN SK~ SE~ -m Q ØDp 4A-6.8 4.9Nv FSM3~ FDK15Za~ Q~ FPDV2~ 20A-6.8 N20.W 20.5Nv FPQ2~ BXLD~ N5.H 1K N5.M 220 KC~ 5A-6.8 NK.8 5.9Nv FDK15Za~ T19.1 10n FPQ1~ KA-0 N4.S RBX_WEN 4K7 1K 5n N26.B RBX_PLD~ FSM3~ FPDV2~ RBD_CLR~ 26A-0 N5.F ØDp N19.Y N27.U 1K Q RE~ -f RKD_CLR~ 27A-0 7.1Nd FBXLD T20.6 7 ØD0 6A-6.8 KCLR_RK~ FSHLF T~ -m T24.11 10 RC~ 20A-0 1K ØDp 24.12Nd PQC=2 N6.H N6.M SH0B1K 24A-2.2 FPDV2~ N24.H N6.F SHIFT K FPQ1 FPML KX KC~ RBX_CLR~ 26A-0 N26.M 19A-0 N19.Z KA-0 NK.9 N5.S 19A-1.5 10n 6K8 N3.H 1K N3.M 220 RAD_PLD~ N3.F RAD_WEN ØDp N2.H 1K N2.M 220 3A-6.8 3.9Nv RAD_CLR~ FSM2~ 26A-0 N26.D KC~ KA-0 NK.10 N3.S RMD_PLD~ N2.F RMD_WEN ØDp 2A-6.8 2.9Nv FSM9~ KCM~ IME 84 Calculator Section: Control - Register Controls & Shift Logic Page: 10 Rendition: Mar 29, 2026 RMD_CLR~ 27A-0 N27.V NK.7 N2.S FSUB 18A-6.8 18.12Nv SG~ -m Q RBX_ROLL FNEGH T18.11 10 ØA~ SK~ ØN RE~ -m !! superfluous double application of FPQ2 FPQ2~ RE~ -m Q~ NN.4 NEG ØA FSUB~ 18A-4.7 18.9Nv NN.3 SG~ -s SK~ Q 3K3 18.13Nd N18.B N27.C RK~ 18A-3.3 FPDV2 RC~ KR~ RC~ 22A-6.8 ØD15 Q~ RG~ -n FPDV2~ FPQ2~ RC~ FPML RC~ BXLD~ RC~ FPML Q~ 20.1Nv 20A-6.8 MPPAE NEG~ FNEG T18.8 7 18.15BF RAD_ROLL Q FMBXR T20.3 2 SC~ ØD15 SE~ -m 22.1Nv SG~ -u RAD_ROLL SK~ FDA15R T22.2 3 FPQ1~ 17A-0 N22.S N17.S ØA10 29A-0 N29.M DA15RE Q ØN RE~ -m Q~ KOPDE~ SE~ -* Q N22.T N21.M FDA15R~ NN.31 OVERFLOW NN.30 FSUB~ FPDV2~ 18A-6.8 18.4Nv Q SG~ -m ØD15 ØA KR~ 18.14Nd N18.A FOVF T18.5 6 SK~ RC~ ØD15 RK_W8 RK_W4 Q~ RK_W2 RK_W1 29R-22 N28.F 29R-22 N29.F N22.J 22.12BF 22A-0 N22.U 22.4Ne 3.3K RKWZ~ RE~ -f KC~ N20.A N28.W FDK15Z T22.6 5 Q~ FDK15Z FDK15Z~ RC~ *B28 22A-0 !! double-diode N22.A N26.K FDK15Za~ A_SETSUB~ KDE~ KA-22 KPL-r NK.24 KA-0 N23.E SE~ -m 10K FPQ2 KPL-r NK.15 N23.D FPDV2~ A_SETADD~ KC~ KR~ KA-22 KPL-r ØA~ RE~ -m N18.F A_START~ A_START~ N23.A N18.K FSUB~ 23A-2.2 FSUB FCYIN~ ØAa~ 23A-2.2 RAD_ROLL SK~ RE~ -m FCYIN FRKR T23.8 7 RE~ -m 23A-2.2 FCYIN ØD0 Q Q~ N18.X ØN~ FCYIN~ SE~ -m Rendition: Mar 29, 2026 Q FNINC T18.2 3 *FDK15Z - B28: Diode for this Set input is on board 28. Section: Arithmetic Page: 11 RE~ -m FPWORK RC~ ØN~ RC~ N23.Z NK.34 FCYIN FPWORK~ IME 84 Calculator 23A-2.2 Q 23R-0 22K ØA10 23A-0 N23.F N3.L Q~ MPPAE RA_INC~ N20.S 20A-0 FCYIN N23.M ØD0 *FDK15Z - SE~: Board layed out for SE~, but in DOPH: Ck=2n, 4K7 to GND, 22K to V– FCYIN SK~ FRACY T23.2 1 Q~ SE~ -m SG~ -m FSUB Q FCYIN T23.5 6 ØA10 FSUB~ FCYIN~ 23R-0 Q~ SG~ -m RKD_ROLL FSUB ØAa~ KPL-r FPDV2~ N23.X 23A-2.2 1n KA-0 10K FPQ1~ Q FSUB T23.9 10 RE~ -m MF_GT 18A-3.3 N18.T NK.32 MF_N ØAa~ RMD_ROLL GT 72 NK.33 N23.Y 71 N MF_FCT 70 SG~ -m FCYIN SK~ FRMCY T23.4 3 Q~ 23A-2.2 Q FCYIN RE~ -m FPWORK RC~ ØN~ RC~ Q~ 23R-0 ØA10 N23.H N18.U 33K *DOPH 18.1BF FSM7a~ 23A-0 18A-3.3 N18.S N2.L RM_INC~ N6.W FSM1~ FSM5~ FSM10~ KDIV~ N26.E 27A-0 N27.E KA-0 P8~ N6.V 26A-0 NK.26 N1.46 RK_S8~ 1.5K TFR_RK~ RKD_PLD~ PLD~ ØA10 INC~ RKD_CLR~ CLR~ N7.W 1.nnPL N1.1 1.nnPL 1.nnPL P1~ FSM1~ FSM4~ KDIV~ FSM10~ N26.A S8~ FRKX1,2,4,8 S4~ KN2~ S2~ KN1~ S1~ RKX_CLR~ CLR~ 26A-0 N26.C KA-0 NK.27 27A-0 N27.W N1.45 TFR_RB~ N1.8 RB_S4~ N1.6 RB_S2~ N1.4 RB_S1~ N1.2 N1.44 RB TRANSFER GATE N1.36 RA_S4~ N1.38 RA_S2~ N1.40 RA_S1~ N1.42 REGISTER B DECADE COUNTER Q4 FRBD1,2,4,8 Q2 P8~ Q8 REGISTER B EXTENSION DECADE COUNTER Q4 FRBX1,2,4,8 Q2 RBX_PLD~ PLD~ RBX_INC~ INC~ RBX_CLR~ CLR~ Q1 P8~ Q8 N3.W RA TRANSFER GATE Q8 Q1 P1~ N3.V P4~ N3.U P2~ N3.T P1~ REGISTER A DECADE COUNTER Q4 FRAD1,2,4,8 Q2 RAD_PLD~ PLD~ RAD_INC~ INC~ RAD_CLR~ CLR~ Q1 N1.35 P8~ Q8 RM_S4~ N1.37 RM_S2~ N1.39 RM_S1~ N1.41 N2.W RM TRANSFER GATE IME 84 Calculator Rendition: Mar 29, 2026 N2.V P4~ N2.U P2~ N2.T P1~ RMD_PLD~ PLD~ RMD_INC~ INC~ RMD_CLR~ CLR~ N6.C 6A-15 6R-0 N6.D 6A-15 6R-0 N6.E N11.B N1.29 RK_W8 N1.25 RK_W4 7A-15 7R-0 N7.B 7A-15 7R-0 N7.C 7A-15 7R-0 N7.D 7A-15 7R-0 N7.E N11.D N1.21 RK_W2 N1.17 RK_W1 N28.B CLR~ P2~ 6R-0 N11.E N4.K RBD_WEN REGISTER M DECADE COUNTER Q4 FRMD1,2,4,8 Q2 Q1 4A-15 4R-0 N4.B N10.B RB_W8 N1.30 4A-15 4R-0 N4.C N10.C N1.26 4R-0 N4.D 4R-0 N4.E 5A-15 5R-0 N5.B 5A-15 5R-0 N5.C 5A-15 5R-0 N5.D 5A-15 5R-0 N5.E 3A-15 3R-0 N3.B 3R-0 N3.C 4A-15 INC~ P4~ 6A-15 N28.C N10.D N1.22 4A-15 N10.E RB_W4 RB_W2 RB_W1 N1.18 N5.K N3.K N20.T N18.M RBX_ROLL RAD_ROLL RBX_WEN RAD_WEN N22.M N9.B N1.31 3A-15 N9.C N1.27 N23.U 3A-15 3R-0 N3.D N9.D N1.23 3A-15 TFR_RM~ RM_S8~ Section: Register Decades Page: 12 N5.V N5.U N5.T TFR_RA~ RA_S8~ N1.43 N5.W PLD~ N6.B N29.B Q2 P4~ RBD_PLD~ N4.L 6R-0 N11.C Q1 P8~ P1~ 6A-15 N29.C Q4 KN4~ P2~ RKD_WEN RKX_WEN KN8~ RBD_CLR~ RB_S8~ RKD_ROLL Q8 PLD~ N4.T 26A-0 N23.W Q1 RKX_PLD~ N4.U FSM5~ Q2 REGISTER K EXTENSION DECADE LATCH N4.V FSM4~ FRKD1,2,4,8 P2~ N4.W 15K Q4 N6.K P4~ N7.T 1.nnPL REGISTER K DECADE COUNTER P8~ N7.U N1.3 1.nnPL RK_S1~ P1~ N7.V N1.5 1.nnPL RK_S2~ 1.nnPL P2~ N6.T N1.7 1.nnPL RK_S4~ RK TRANSFER GATE Q8 P4~ N6.U 3R-0 N3.E N9.E N1.19 N2.K N23.V RMD_ROLL RMD_WEN 2A-15 2R-0 N2.B 2RA-0 N2.C 2R-0 N2.D N8.B RA_W8 RA_W4 RA_W2 RA_W1 RM_W8 N1.32 2A-15 N8.C N1.28 2A-15 N8.D N1.24 2A-15 2R-0 N2.E N8.E N1.20 RM_W4 RM_W2 RM_W1 ØDD ØDC ØDB ØDA MD ØDM 4K7 ØDm bA-0 3K3 ØWp 1K Tb.+8 V–4.5 Tb.+7 22K 4K7 bA-0 3K3 ØRp 10 1K Tb.+6 5 Tb.+5 10K MD +5 +6 +7 ØDd ØDc ØDb ØDa +8 MD0 0 T16.5 T16.6 T16.7 T16.8 MD1 1 T16.9 T16.10 T16.11 T16.12 MD2 2 T16.13 T16.14 T16.15 T16.16 MD3 3 T16.17 T16.18 T16.19 T16.20 MD4 4 T15.5 T15.6 T15.7 T15.8 5 T15.9 T15.10 T15.11 T15.12 MD5 6 T15.13 T15.14 T15.15 T15.16 7 T15.17 T15.18 T15.19 T15.20 MD7 N16.W N16.X N16.Y N16.Z N15.W N15.X N15.Y MD6 8 core digit line 9 10 11 T14.5 T14.6 T14.7 T14.8 MD8 T14.9 T14.10 T14.11 T14.12 MD9 T14.13 T14.14 T14.15 T14.16 MD10 T14.17 T14.18 T14.19 T14.20 MD11 12 T13.5 T13.6 T13.7 T13.8 13 T13.9 T13.10 T13.11 T13.12 14 T13.13 T13.14 T13.15 T13.16 15 T13.17 T13.18 T13.19 T13.20 N15.Z N14.W N14.X N14.Y N14.Z N13.W MD12 N13.X MD13 N13.Y MD14 N13.Z MD15 N11.L MR RK_W1 MRK1 15K N11.K ØD~ 2K2 V–4.5 register-bit write R bA-3.3 ØWp 2K2 3K3 470 Tb.+1 47 3K3 5n 5n Tb.+4 RK_W2 MRK2 RK_W4 MRK4 N11.J 3K3 5n sense 10K 6K8 N11.H RK_W8 MRK8 RB_W1 MRB1 N10.K K87 1K 200n RB_W2 MRB2 RB_W4 MRB4 N10.J core register-bit line N10.H +1 +2 +3 +4 K1 T11.1 T11.2 T11.3 T11.4 K2 T11.5 T11.6 T11.7 T11.8 K4 T11.9 T11.10 T11.11 T11.12 K8 T11.13 T11.14 T11.15 T11.16 N11.U RK_S4~ N11.V RK_S8~ N11.W 10K N10.L MR N11.T RK_S2~ Tb.+3 Tb.+2 10K RK_S1~ RB_W8 MRB8 RA_W1 MRA1 RB_S1~ N10.T RB_S2~ N10.U RB_S4~ N10.V RB_S8~ N10.W MR 15K ØD~ 22K B1 T10.1 T10.2 T10.3 T10.4 B2 T10.5 T10.6 T10.7 T10.8 2K2 B4 T10.9 T10.10 T10.11 T10.12 Tb.+3 B8 T10.13 T10.14 T10.15 T10.16 A1 T9.1 T9.2 T9.3 T9.4 A2 T9.5 T9.6 T9.7 T9.8 A4 T9.9 T9.10 T9.11 T9.12 A8 T9.13 T9.14 T9.15 T9.16 M1 T8.1 T8.2 T8.3 T8.4 M2 T8.5 T8.6 T8.7 T8.8 M4 T8.9 T8.10 T8.11 T8.12 M8 T8.13 T8.14 T8.15 T8.16 5n Tb.+4 5n N9.L 3K3 10n sense 10K 6K8 N9.K RA_W2 MRA2 N9.J RA_W4 MRA4 N9.H 10K 1.5K 200n RA_W8 MRA8 RM_W1 MRM1 Unit 1.8400903 Modified sense amplifier N8.L core register-bit line N8.K RM_W2 MRM2 N8.J RM_W4 MRM4 N8.H RM_W8 IME 84 Calculator Section: Register Core Matrix, Drivers & Sense Amps Page: 13 Rendition: Mar 29, 2026 MRM8 RA_S1~ N9.T RA_S2~ N9.U RA_S4~ N9.V RA_S8~ N9.W RM_S1~ N8.T RM_S2~ N8.U RM_S4~ N8.V RM_S8~ N8.W V–c RSEL_K P1~ P2~ P4~ P8~ RK_W8 1A-3.3 R RA_W8 1A-3.3 R RM_W8 1A-3.3 R RB_W8 1A-3.3 R RSEL_A 1.5K PLD~ RSEL_M SG~ -w SG~ -w SK~ T~ -k INC~ RC~ Q SG~ -w SK~ Fr1 Tb.2 1 bA-3.3 Q~ T~ -k RC~ Q SG~ -w SK~ Fr2 Tb.4 3 T~ -k Q~ RC~ Q SK~ Fr4 Tb.6 5 SE~ -a RE~ -d Q~ RC~ RSEL_B Q Fr8 Tb.8 7 REGISTER DECADE COUNTER MODULE Q~ CLR~ FDPK8 RSEL_K~ FDPR8 Q1 S1~ P1~ Q2 S2~ P2~ Q4 S4~ P4~ S8~ P8~ SK~ SC~ RC~ SG~ -m SK~ Q Fr1 Tb.2 1 SC~ Q~ RC~ Q SC~ Q~ RC~ Q SK~ Fr4 Tb.6 5 SC~ Q~ RC~ Q Fr8 Tb.8 7 REGISTER DECADE LATCH MODULE Q~ CLR~ 1A-3.3 R RM_W4 1A-3.3 R RB_W4 1A-3.3 R FDPK4 Q2 Q4 N1.9 N32.W DD8 N31.W ØN RA_W4 FDPR4 Q1 31A-1.5 N30.B N31.B 31R-0 1A-3.3 R SG~ -m SK~ Fr2 Tb.4 3 30R-0 RK_W4 PLD~ SG~ -m 30A-1.5 Q8 1.5K SG~ -m 1R-0 R 31A-3.3 31R-0 1R-0 30A-1.5 30R-0 31A-1.5 N30C N31.C 31R-0 N1.10 N32.V DD4 N31.V ØN R 31A-3.3 31R-0 Q8 RK_W2 1A-3.3 R RA_W2 1A-3.3 R RM_W2 1A-3.3 R RB_W2 1A-3.3 R 4K7 Q K~ bA-10 T~ -m 100 RR~ Q 22K 1n Fm1 Tb.2 1 PL Q~ T~ -p RR~ Fm2 Tb.4 3 Q T~ -p Q~ RR~ SE~ -p Fm4 Tb.6 5 Q DIV10 Fm8 Tb.8 7 Q~ R~ RE~ -p Q~ DIV10 COUNTER MODULE RR~ FDPK2 FDPR2 Q K~ T~ -m RR~ Fm1 Tb.10 9 Q~ Q T~ -p RR~ Fm2 Tb.12 11 Q~ Q T~ -p RR~ Fm4 Tb.14 13 Q~ Q T~ -p RR~ Q~ DIV16 COUNTER MODULE Section: Counter Modules & Display Selector Page: 14 Rendition: Mar 29, 2026 30R-0 31A-1.5 N30.D N31.D 31R-0 RA_W1 1A-3.3 R RM_W1 1A-3.3 R RB_W1 1A-3.3 R FDPK1 FDPR1 N1.11 N32.U DD2 N31.U ØN 1A-3.3 R R~ IME 84 Calculator 30A-1.5 RK_W1 DIV16 Fm8 Tb.16 15 1R-0 R 31A-3.3 31R-0 1R-0 30A-1.5 30R-0 31A-1.5 N30.E N31.E 31R-0 N1.12 N31.T ØN R 31A-3.3 31R-0 N32.T DD1 V–100 1K V–100 47K DD8 22K T32.7 V–100 47K 10K V–100 V–100 T32.13 8~ 47K 47K T32.8 8 8 4~ N32.M NN.10 N32.L NN.8 1015 1014 1013 1012 1011 1010 109 108 107 106 105 104 103 102 101 100 2~ 10K 10K 1 8 DD4 T32.5 T32.6 4~ 4 DD2 DD1 T32.3 T32.1 T32.4 T32.2 4~ T32.18 2~ 2~ 1~ 2 8~ 1~ 4 1 2 MULLARD 0 2 4 6 8 ZM1080 1 3 5 7 9 T32.12 N32.K NN.29 NN.6 1 8~ 4 N13.L T32.17 N32.J 4K7 NN.2 2 ØDD 1~ ØDd 8~ 4 N32.H NN.1 100K N13.M N13.U N13.V N14.L N14.M N14.U N14.V N15.L N15.M N15.U N15.V N16.L N16.M N16.U N16.V N30.W T13.4 T13.3 ØDD T13.2 ØDD T13.1 ØDD T14.4 ØDC T14.3 ØDC T14.2 ØDC T14.1 ØDC T15.4 ØDB T15.3 ØDB T15.2 ØDB T15.1 ØDB T16.4 ØDA T16.3 ØDA T16.2 ØDA T16.1 ØDA ØDc ØDb ØDa ØDd ØDc ØDb ØDa ØDd ØDc ØDb ØDa ØDd ØDc ØDb ØDa 10K ØX T32.11 100n NN.28 NN.27 NN.26 NN.25 NN.24 NN.23 NN.22 NN.21 NN.20 NN.19 NN.18 NN.17 NN.16 NN.15 NN.14 V+100 1K5 2~ 4K7 1 8~ 4 T32.16 N32.F 1K5 N32.E NN.9 N32.D NN.11 N32.C NN.12 N32.B NN.13 2 1 8~ 4~ T32.15 2 1~ 8~ 4~ T32.9 2~ 1 8~ 4~ T32.14 2~ 1~ IME 84 Calculator Section: Display Page: 15 47K 47K T32.10 Rendition: Mar 29, 2026 V+A V+A ØD NN.7 1~ 4~ V+A V+A V+100 5µ 12V 1K5 V+100 47K 5µ 12V 1K5 V+100 47K 5µ 12V 1K5 V+100 10n 100n ØN 2~ 8~ 33K V+A NN.5 T30.1 10K 47K 5µ 12V 1K5 V+100 5µ 12V Q KNML~ 30.13Nv 4.7K 30PL-g 15K Q Q Q FDPK1 T~ -g T30.5 6 FDPK2 T~ -n T30.7 8 FDPK4 T~ -n T30.9 10 FDPK8 T~ -n T30.11 12 RB RB RB RB Q~ Q~ Q~ Q~ 220 KP~ SC~ 47n N30.Z KCLR_RK~ RC~ KMUL~ RB KDIV~ 30A-6.8 KR~ Q FDPKE T30.3 4 FDPK1 FDPK2 FDPK4 FDPK8 Q~ 30.2PH+ 10n KC~ DPINC~ SC~ Q 31A-2.2 Q~ 31A-2.2 N30.H N31.H UP~ FDPRD T31.2 3 30A-3.3 N30.J N31.J DPRDR~ RC~ DOWN~ RB TG~ -hg Q FDPR1 T~ -g T31.4 5 RB TG~ -hg TK~ Q FDPR2 T31.6 7 Q~ TK~ TG~ -hg TK~ Q TK~ FDPR4 T31.8 9 Q~ TK~ Q FDPR8 T31.10 11 Q~ TK~ TG~ -h TG~ -h TG~ -h RB RB RB Q~ 31.1PH+ FDPR1 N30.Z: MOD2025.11 Modification to allow the DP to be set & fixed for the duration of a summation. IME 84 Calculator Section: DP Counters Page: 16 Rendition: Mar 29, 2026 FDPR2 FDPR4 FDPR8 V–100 bu 4.5 56Ω 100µ 100V bu pk NP.3 bu NP.5 N32.S 4.4 100µ 100V 4.6 N13::16.T, N30.S V+100 8.2 10W bk 2• 1000µ 25V 4.7 2.4Ω 2N555 bk POWER 220VAC 50Hz bk bn 1000µ 12V TP4.4 GP297/1 10n NP7,8 –12V N2::32.N NK.38 N1.33 N2::32.P NK.37 N1.34 N2::32.R NK 300µ 12V gy 1 1K 1K 0.35A 4.7K NP14,15 TP4.3 T6055 9 rd 100µ 12V rd black 1K gn TP1.3 2N555 2 bu 1.5 500µ ?V 3 rd 680 500µ ?V TZ5.1 14 rd +4.5V V–4.5 power supply boards 111 & 114 TP1.2 2N555 470 3K3 red 1K 3K3 1K TP1.1 T6056 11 yl 1000µ 12V 9.8 2% 13.5 2% N8::16.S NP.2 10 100µ ?V wh NP.6 –2.6V N11.X V–c 1.16 core board bn TP4.1,2 T6055 330 rdbu 4.12 Rendition: Mar 29, 2026 NP.4 14 rd IME 84 Calculator NP.12,13 9 1.5K 1.4 4.4Ω Section: Power Supply Page: 17 NP.1 8 N11.Y NP.9 MTEMP T logic 1,T (–12V) (~ 20 KHz) ØM FØC1 logic 0,F (0V, GND) 0 1 2 0 1 2 3 0 1 2 3 3 FØC2 / ØD sense strobe ØD~ decade clear ØDp core clear (read) ØRp core write ØWp nixie trigger ØX ØA 0 1 2 3 4 5 6 7 8 9 ØA10 FCYIN ØD0 ØDn 0 0 1 2 ••• 14 15 0 0 1 2 ØN FPWORK Internumber phase Normal Digit Cycle 200µS Normal Number Cycle 3.4mS IME 84 Calculator Section: Timing Graph Page: 18 Rendition: Mar 29, 2026 • The diagram shows the transition from a normal number cycle to an arithmetic number cycle such as occurs when FPWORK asserts for an ADD or SUBTRACT procedure. • Unit 1.8400903: ØM = 18.9 KHz Arithmetic (extended) Digit Cycle 650µS Arithmetic Number Cycle 11.05mS Pulser-generated pulse (RC) 3 ØN KDE~ e0 KOP~ FPSYNC KOPDE~ FPWORK e1 SYNC~ e4 e10 e3 FDK15Z FPDV1 FPDV2 D1C PLC PQC 0 1 2 ••• 12 13 14 15 0 0 0 ••• 0 0 1 0 0 0 ••• 0 0 sync shift RK up shift RK up shift RK up shift RK up inc. PLC e5 0 0 0 0 0 0 ••• 0 0 0 0 2 3 3 3 4 4 4 ••• 15 0 0 0 0 0 0 0 2 3 0 ••• 1 2 3 0 inc. PLC inc. PLC RA–=RK RA–=RK shift RK down shift RB up RA–=RK etc. e6 1 e7 e8 FSUB RA+=RK 2 secondary-loop iterations 3 arithmetic number cycles 1 primary-loop iteration Stage 1a IME 84 Calculator Section: Timing Graph - Division Page: 19 Rendition: Mar 29, 2026 Stage 1b • Division example with a 4-digit divisor, and for which the first digit of the quotient will be 1. Stage 2 e9 AND-Form Gates OR-Form Gates +logic AND Wired Inputs (AND-form example) +logic OR bb A- t bb R-0 bb A- t bb R- t –logic OR Distributed Gates (OR-form example) bb A- t G~ G~ G~ bb R- t –logic AND bb A- t Distributed Gate Separated on Pages (–logic OR example) bb A-0 bb R- t G~ bb A-0 This gate has 6 inputs in total. R The black tab symbol indicates this circuit electrically has multiple sources. R R = t •1000 If t=0, no resistor is present. R R = t •1000 If t=0, no resistor is present. The perpendicular output line on a gate symbol indicates this is part of a distributed gate. One of the contributors provides the load R while the others are (typically) type-0 (no load R). AND-Form with pull-up as input: R bb A- t R Gate Identification Gates are identified with a label of the form: or bb gg - t bb . tt gg - t where: bb tt gg t gg = A R Nv Nd Ne BF PL PH PH+ • Logic 0, F = 0V, GND Logic 1, T = –12V IME 84 Calculator Section: Modules - Gates Page: 20 = board [1::34] = transistor number in PCB foil = gate type = optional type variation Rendition: Mar 29, 2026 AND OR NOT NOT with diode & Rh NOT with delay cap on base buffer pulse 0 on 0-edge pulse 1 on 0-edge like PH but swings down to + for FF-RB inputs Pulsers Buffers bbPL-t bb.tt PH Inverters bb.tt BF G Monostable Flip-flops bb.tt Nv bb.tt Nd bb.tt Ne bb.tt Nv bb.tt Nd bb.tt Ne TM~ Q Name Tbb.q q~ Q~ 1 0 RL Rb Cp 1 0 Rg G=1 G=0 G 1 0 Rb Cp 1 0 RL Rh RL RL tt Ci Ri Ci Ci Ri tt tt Rg Rb RE Ri Cd Rb 2K2 tt tt Rb Cp Rg Rb bb.tt Rg a 10n 6K8 - 25.12 c 10n 22K - 25.14 d 10n 22K 47K 25.15 e 10n 22K 22K f 10n 10K - g 10n 47K - p 5n 4K7 - Rb RL bb.tt RE bb.tt Rh Ri Rb RL Ci - 2n 4K7 2K2 18.1 220 2.9 - 4K7 15K 4K7 1n - ?2n 4K7 2K2 18.15 33?330 3.9 - 4K7 15K 4K7 1n - 5n 4K7 2K2 4.9 - 4K7 15K 4K7 1n 5.9 - 4K7 15K 4K7 1n 6.9 - 4K7 15K 4K7 1n 7.1 6K8 4K7 15K 3K3 1n 7.2 - 4K7 15K 3K3 1n r 5n 10K s 5n 15K - 17.9 6K8 4K7 15K 2K2 - - 18.4 - 4K7 15K 2K2 500p v 5n - 6K8 18.9 - 6K8 15K 2K2 w 5n - 10K 18.12 - 4K7 15K 2K2 500p y 10n - 4K7 18.13 2K2 3K3 10K - - 18.14 2K2 3K3 10K - - 19.9 2K2 3K3 10K - - 19.10 2K2 3K3 10K - - 19.11 2K2 3K3 10K - - 19.12 2K2 3K3 10K - - 20.1 - 4K7 15K 2K2 5n 20.4 - 4K7 15K 2K2 500p FSM7: 20.5 - 4K7 15K 2K2 500p 20.8 - 4K7 15K 2K2 20.9 - 4K7 15K 2K2 500p 21.7 - 4K7 15K 2K2 500p 21.8 - 4K7 15K 2K2 500p 22.1 - 4K7 15K 2K2 22.4 - 6K8 15K 2K2 500p 22.11 - 4K7 15K 2K2 500p 24.9 6K8 4K7 15K 2K2 470p 24.12 6K8 4K7 15K 2K2 470p 24.13 - 4K7 15K 2K2 470p 24.14 - 4K7 15K 2K2 25.1 6K8 4K7 15K 2K2 500p 25.13 2K2 15K 15K 2K2 - 30.13 - 22K 15K 2K2 - bb.tt PH+ RL Rb Cp 1 0 1 +0 tt tt Re If the gate input is not present on a symbol instance, Rg is grounded (always enabled). bb.tt Rb Cp RL bb.tt Re 30.2 33K 10n 2K2 22.12 3K3 31.1 33K 10n 1K5 Register Transfer Gate Circuit 3K3 5n 10K Rr_Sb~ Rr_Sb~ 6K8 1n 4.7K TFR_Rr~ Sense Amplifier 1.5K 10n other 3 bits of register 15K 10n 15K Transfer Gate 15K TRANSFER BUS bit b of other registers IME 84 Calculator Section: Modules - Pulsers, Buffers & Inverters Page: 21 Rendition: Mar 29, 2026 Decade Flip-Flop 1n 10n - - Cm 2K2 Q~ Cp Ne Special: 22.4: 2n capacitor base-GND 24.14: 1n capacitor base-GND Rm 4K7 Tbb.q t 6K8 Q Tbb.q~ 22K TM~ MONO Cm Rm mS FSM1 470n 68K 24 FSM2 100n 68K 5 FSM3 100n 68K FSM4 470n 68K FSM5 470n 68K FSM6 100n 68K FSM7 220n 100K 18 FSM8 100n 68K 5 FSM9 100n 68K FSM10 470n 68K FSM6 " 33K FSM7 470n 47K #903: DOPH: MOD196X.A Stabilise FSM7 by changing RC values per DOPH above. Flip-Flops Flip-Flop Base in Q Name Tbb.q q~ in RL Q Base Component Values Cf Cf Tbb.q RL Q~ Tbb.q~ Q~ Types SC~ and RC~ Rb Flip-Flop FØA 1K 6K8 500p 22K FPSYNC 2K2 6K8 ?? 22K FØA1,2,4,8 2K2 10K 500p 22K FPWORK 2K2 6K8 500p 22K FØC1,2 680 6K8 500p 22K FPAS 2K2 6K8 - 22K FØD1,2,4,8 2K2 4.7K 1n 15K FPML 2K2 6K8 500p 22K FØN 2K2 4.7K 500p 22K FPDV1 2K2 6K8 500p 22K FPDV2 2K2 6K8 500p 22K FRS1,2 2K2 6K8 5n 22K FPQ1 2K2 6K8 5n 22K FRKD1,2,4,8 2K2 10K 470p 22K FPQ2 2K2 6K8 500p 22K FRKX1,2,4,8 2K2 10K 470p 22K FSHLF 2K2 6K8 5n 22K FRBD1,2,4,8 2K2 10K 470p 22K FNEG 2K2 6K8 500p 22K FRBX1,2,4,8 2K2 10K 470p 22K FNEGH 2K2 6K8 * 22K FRAD1,2,4,8 2K2 10K 470p 22K FOVF 2K2 6K8 500p 22K FRMD1,2,4,8 2K2 10K 470p 22K Control Counters FBXLD 2K2 6K8 500p 22K FPL1,2,4,8 2K2 10K 500p 22K FMS1,2,4,8 2K2 10K 500p 22K 2K2 10K 500p 22K - 22K FD11,2,4,8 Q FCYIN 2K2 6K8 500p 22K DP Counters FRKR 2K2 6K8 500p 22K FDPK1,2,4,8 2K2 10K 500p 22K FRACY 2K2 6K8 500p 22K FDPR1,2,4,8 2K2 10K 500p 22K FRMCY 2K2 6K8 500p 22K FDPKE 2K2 22K 500p 22K FNINC 2K2 6K8 500p 22K FDPRD 2K2 10K 22K FMBXR 2K2 6K8 500p 22K FDK15Z 2K2 6K8 - 22K FDA15R 2K2 6K8 500p 22K Q~ Rg Ck Edge-triggered Set & Reset. Ck SE~ Q goes 1 on 1-to-0 edge of SE~. Q goes 0 on 1-to-0 edge of RE~. RE~ <<RL *FNEGH: In DOPH, Cf(Q.C)=500p Cf(Q~.C)=5n Types SG~ and RG~ RR~ Type RR~ Tbb.q Gated Edge-triggered Set & Reset. Rg Q goes 0 if RR~ = 0. Ck Ck SG~ SK~ Rg Q goes 1 if SG~=0 on 1-to-0 edge of SK~. Q goes 0 if RG~=0 on 1-to-0 edge of RK~. Q~ Type T Toggle. Rt Ct Ct Tbb.q 2• Rb Toggle Q on 1-to-0 edge of T~. T~ Q Q~ Type TG Q goes 0 when RB is –. RB Rt Ct 10K Ct Rt additional toggle gates Rg TG~ IME 84 Calculator Section: Modules - Flip-Flops Page: 22 Rendition: Mar 29, 2026 Ck TK~ SG,RG : SE,RE : T : TG : - cRC - cRC - cRC - gcRC tcRC cRC –> Ck,Rg cRC –> Ck,Rg cRC –> Ct,Rt gcRC –> Ck,Rg; tcRC –> Ct,Rt Rt Q Reset by raising bias R. Must be driven by a source that swings + and –. Input Component Value Codes RK~ RG~ Q Type RB Rb 6K8 Types SE~ and RE~ Similar to RC~. Cf 2K2 SC~ RL Rf FSUB Q goes 1 if SC~ = 0. Q goes 0 if RC~ = 0. Q RL Control Arithmetic Rg Collector Set & Reset. RC~ Cf Input Options Edge-Triggered Input Options Level-Set Q Rf Registers Rf 2• Rb RL Timing q & q~ are transistor numbers in PCB foil. Q~ Rf Flip-Flop in are input options. Gated Toggle. Toggle Q if TG~=0 on 1-to-0 edge of TK~. cRC R a 3K3 d 15K C 470p 470p u 10K 220p k m n p s 3K3 4K7 6K8 10K 22K 1n 1n 1n 1n 1n f g h 4K7 6K8 15K 5n 5n 5n w x y 4K7 6K8 10K 2n 2n 2n - N17 N16 N15 N14 N13 A B ØDd C ØDc D ØDb E ØDa F ØDA H ØDB J ØDC K ØDD L ØD0 M ØD15 N V–12 P GND R V+4.5 S DA15RE T FPQ2 U FPQ1~ V ØD W ØN~ X Y Z - A B ØDA C ØDd D ØDc E ØDb F ØDa H ØWp J ØRp K ØX L NXA3 M NXA2 N V–12 P GND R V+4.5 S V–4.5 T V+100 U NXA1 V NXA0 W MD0 X MD1 Y MD2 Z MD3 A B ØDB C ØDd D ØDc E ØDb F ØDa H ØWp J ØRp K ØX L NXA7 M NXA6 N V–12 P GND R V+4.5 S V–4.5 T V+100 U NXA5 V NXA4 W MD4 X MD5 Y MD6 Z MD7 A B ØDC C ØDd D ØDc E ØDb F ØDa H ØWp J ØRp K ØX L NXA11 M NXA10 N V–12 P GND R V+4.5 S V–4.5 T V+100 U NXA9 V NXA8 W MD8 X MD9 Y MD10 Z MD11 A B ØDD C ØDd D ØDc E ØDb F ØDa H ØWp J ØRp K ØX L NXA15 M NXA14 N V–12 P GND R V+4.5 S V–4.5 T V+100 U NXA13 V NXA12 W MD12 X MD13 Y MD14 Z MD15 N12 N11 N10 N09 N08 N07 N06 N05 N04 A B RK_W8 C RK_W4 D RK_W2 E RK_W1 F ØWp H RK_S8~ J RK_S4~ K RK_S2~ L RK_S1~ M ØD~ N V–12 P GND R V+4.5 S V–4.5 T MRK1 U MRK2 V MRK4 W MRK8 X (V–c) Y (MTEMP) Z - A B RB_W8 C RB_W4 D RB_W2 E RB_W1 F ØWp H RB_S8~ J RB_S4~ K RB_S2~ L RB_S1~ M ØD~ N V–12 P GND R V+4.5 S V–4.5 T MRB1 U MRB2 V MRB4 W MRB8 X Y Z - A B RA_W8 C RA_W4 D RA_W2 E RA_W1 F ØWp H RA_S8~ J RA_S4~ K RA_S2~ L RA_S1~ M ØD~ N V–12 P GND R V+4.5 S V–4.5 T MRA1 U MRA2 V MRA4 W MRA8 X Y Z - A B RM_W8 C RM_W4 D RM_W2 E RM_W1 F ØWp H RM_S8~ J RM_S4~ K RM_S2~ L RM_S1~ M ØD~ N V–12 P GND R V+4.5 S V–4.5 T MRM1 U MRM2 V MRM4 W MRM8 X Y Z - A B RK_W8 C RK_W4 D RK_W2 E RK_W1 F ØDp H KN8~ J KN4~ K KN2~ L KN1~ M RKD_PLD1~ N V–12 P GND R V+4.5 S RKX_CLR~ T RK_S1~ U RK_S2~ V RK_S4~ W RK_S8~ X Y Z - A B RK_W8 C RK_W4 D RK_W2 E RK_W1 F RKD_WEN H RKD_PLD1~ J ØDp K RKD_ROLL L ØA10 M RKD_PLD2~ N V–12 P GND R V+4.5 S RKD_CLR~ T RK_S1~ U RK_S2~ V RK_S4~ W RK_S8~ X Y Z - A B RB_W8 C RB_W4 D RB_W2 E RB_W1 F RBX_WEN H RBX_PLD1~ J ØDp K RBX_ROLL L RBX_INC~ M RBX_PLD2~ N V–12 P GND R V+4.5 S RBX_CLR~ T RB_S1~ U RB_S2~ V RB_S4~ W RB_S8~ X Y Z - A A B RB_W8 B RA_W8 C RB_W4 C RA_W4 D RB_W2 D RA_W2 E RB_W1 E RA_W1 F RBD_WEN F RAD_WEN H RBD_PLD1~ H RAD_PLD1~ J ØDp J ØDp K {RBD_ROLL} K RAD_ROLL L {RBD_INC~} L RA_INC~ M RBD_PLD2~ M RAD_PLD2~ N V–12 N V–12 P GND P GND R V+4.5 R V+4.5 S RBD_CLR~ S RAD_CLR~ T RB_S1~ T RA_S1~ U RB_S2~ U RA_S2~ V RB_S4~ V RA_S4~ W RB_S8~ W RA_S8~ X X Y Y Z Z - CORE IME 84 Calculator Section: Connectors N1 :: N17 Page: 23 Rendition: Mar 29, 2026 • Bold-faced expressions are signal sources. N03 N02 A B RM_W8 C RM_W4 D RM_W2 E RM_W1 F RMD_WEN H RMD_PLD1~ J ØDp K RMD_ROLL L RM_INC~ M RMD_PLD2~ N V–12 P GND R V+4.5 S RMD_CLR~ T RM_S1~ U RM_S2~ V RM_S4~ W RM_S8~ X Y Z - N01 EMPTY EMPTY N22 N21 N20 N19 N18 A FDK15Za~ B D1CINC~ C PLEND~ D D1CEND~ E FPWORK~ F KOPDE~ H FPDV2 J RKWZ~ K ØD15 L ØN M RAD_ROLL N V–12 P GND R V+4.5 S DA15RE T FDA15R~ U FDK15Z V FPDV2~ W PLINC~ X Y Z - A KC~ B SH0B1K C FPQ1~ D FPML E FPQ2 F FPQ2~ H PLEND~ J KOPME~ K ØN L FPDV2 M FDA15R~ N V–12 P GND R V+4.5 S RBX_INC~ T MSCINC~ U MSCEND~ V FPML~ W SHIFTa X Y Z - A FDK15Z B SYNC~ C FPML~ D FPQ2 E FPDV2~ F FPDV2 H FPWORK J FPML K FPQ1~ L ØN M FPQ2~ N V–12 P GND R V+4.5 S RA_INC~ T RBX_ROLL U A_START~ V MSCINC~ W RBX_PLD2~ X ØD0 Y #33 Z PLINC~ A KASD~ B KCLR_RK~ C RSEL_K~ D RSEL_B~ E RSEL_A~ F RSEL_M~ H FPWORK~ J RSEL_K K RSEL_B L RSEL_A M RSEL_M N V–12 P GND R V+4.5 S KRK~ T KRB~ U KRA~ V KRM~ W FPDV2~ X FPQ1~ Y #33 Z RBX_CLR~ A OVF~ B NEG~ C ØD15 D ØA E FPDV2~ F FSUB H ØA~ J ØN K FSUB~ L KR~ M RAD_ROLL N V–12 P GND R V+4.5 S RM_INC~ T MF_N U RM_INCa~ V FSM7a~ W FPWORK~ X FCYIN Y ØD0 Z ØN~ N32 N31 N30 N29 N28 N27 N26 N25 N24 N23 A B NXK0 C NXK1 D NXK2 E NXK3 F NXK4 H NXK5 J NXK6 K NXK7 L NXK8 M NXK9 N V–12 P GND R V+4.5 S V–100 T DD1 U DD2 V DD4 W DD8 X Y Z - A B DDP8 C DDP4 D DDP2 E DDP1 F RSEL_K~ H DPINC~ J DPRDR~ K ØN L KDIV~ M KC~ N V–12 P GND R V+4.5 S T DD1 U DD2 V DD4 W DD8 X Y Z - A KMUL~ B DDP8 C DDP4 D DDP2 E DDP1 F RSEL_K H DPINC~ J DPRDR~ K ØN L KDIV~ M KC~ N V–12 P GND R V+4.5 S V+100 T KP~ U KNML~ V KR~ W NXADP X Y ØD Z - A B RK_W4 C RK_W8 D E F RKWZ~ H J K PLEND~ L PLINC~ M DA15RE N V–12 P GND R V+4.5 S FØA8 T KC~ U ØA10 V W FPDV2 X Y {KC~(29)} Z - A B RK_W1 C RK_W2 D E F RKWZ~ H J K D1CEND~ L D1CINC~ M N V–12 P GND R V+4.5 S MSCEND~ T KC~ U MSCINC~ V W FDK15Z X Y {KC~(28)} Z - A B KRM~ C NEG~ D KCLR_RK~ E TFR_RK~ F FSM2 H FSM8 J FSM1p~ K KTOT~ L FSM8p~ M KIM~ N V–12 P GND R V+4.5 S RKX_CLR~ T RSEL_K~ U RKD_CLR~ V RMD_CLR~ W TFR_RM~ X FSM7a~ Y KME~ Z FSM6p~ A TFR_RB~ B RBD_CLR~ C TFR_RA~ D RAD_CLR~ E TFR_RK~ F FSM2 H FSM8 J FSM1p~ K FDK15Za~ L FSM8p~ M RBX_CLR~ N V–12 P GND R V+4.5 S RSEL_A~ T RSEL_K~ U KMUL~ V KR~ W RSEL_B~ X KNn~ Y KRK~ Z FSM6p~ A B ØDp C ØRp D ØX E ØWp F ØD0 H A_START~ J FØA8 K ØA10 L ØN M ØD N V–12 P GND R V+4.5 S ØA T U ØN~ V ØA~ W ØD~ X Y Z - A B RKDW,XR~ C RBDW,XR~ D SH0B1K E SHIFTa F RBXW,DR~ H RKDR~ J #33 K A_START~ L ØD~ M KOPAS~ N V–12 P GND R V+4.5 S KOP~ T SYNC~ U KN~ V FPWORK~ W FPWORK X KNML~ Y Z KC~ A FSUB~ B ØD0 C ØA10 D A_SETADD~ E A_SETSUB~ F RA_INC~ H RM_INCa~ J FPWORK K ØN~ L A_START~ M FCYIN N V–12 P GND R V+4.5 S T ØA~ U RAD_ROLL V RMD_ROLL W RKD_ROLL X FSUB Y MF_FCT Z MF_GT IME 84 Calculator Section: Connectors N18 :: N32 Page: 24 Rendition: Mar 29, 2026 N1 NK NN 1 RK_S1~ 2 RB_S1~ 3 RK_S2~ 4 RB_S2~ 5 RK_S4~ 6 RB_S4~ 7 RK_S8~ 8 RB_S8~ 9 DD8 10 DD4 11 DD2 12 DD1 13 RSEL_B 14 RSEL_K 15 RSEL_A 16 RSEL_M 17 RK_W1 18 RB_W1 19 RA_W1 20 RM_W1 21 RK_W2 22 RB_W2 23 RA_W2 24 RM_W2 25 RK_W4 26 RB_W4 27 RA_W4 28 RM_W4 29 RK_W8 30 RB_W8 31 RA_W8 32 RM_W8 33 V–12 34 GND 35 RM_S8~ 36 RA_S8~ 37 RM_S4~ 38 RA_S4~ 39 RM_S2~ 40 RA_S2~ 41 RM_S1~ 42 RA_S1~ 43 TFR_RM~ 44 TFR_RA~ 45 TF