Schematic

TEAL IME 41 Calculator: Reverse-Engineered Schematic

Nineteen-page schematic of the IME 41 desk calculator of 1970, built on MSI MOS logic with individual fluorescent tubes.

Author: Brent Hilpert
Type: Schematic
Credit: Drawn and written by Brent Hilpert, Early Electronic Calculators, madrona.ca.

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TEAL: IME 41 Calculator Contents Section Page Title & Contents (this page) 1 Notes, Signal Names & Logic Design 2 Block Diagram 3 Timing Diagram 4 Timing 5 Keyboard - Numeral Encoding 6 Keyboard - Operation Flags 7 Control - Next-State Logic 8 Control - State Register & Flags 9 Sign Flags, A/S Logic & DP Flags 10 PLC & DP Counters 11 Registers 12 Arithmetic 13 Display 14 Power Supply 15 IC & Module Pinouts 16 IC Functional Equivalents 17 Connectors & Board Layout 18 Repairs 19 TEAL: IME 41 Calculator This schematic has been derived through reverse engineering. Section: Title and Contents This is not the manufacturer’s schematic, Page: 1 Rendition: Oct 15, 2023 nor based on the manufacturer’s schematic. Notes Logic Presentation Ncp Gate symbols and signal names are presented in accordance with: • The symbol denotes a physical connector pin, where c=connector and p=pin. Solid black end is the male side of logic 1 = GND the connector. White end is the female side of the connector. logic 0 = V–24 • The symbol without an additional label denotes VDD (–24V). The design uses primarily negative logic in the control portion and positive logic for data and registers. • See also the TEAL/Riccar schematic (madrona.ca/e/eec). A state diagram is included in the Riccar schematic. Logic Implementation • See also the TEAL/Royal Digital I Theory of Operation document (madrona.ca/e/eec). The logic is implemented with a combination of early SSI and MSI MOS integrated circuits from the JMOS family, and discrete DTL. Most gates are constructed from discrete diodes and resistors. Inverters, active gates, flip-flops and more complex logic elements are contained in • This drawing is based on observation of board photographs of two units. the integrated circuits. The active elements are open-drain outputs, closing to GND (logic 1), requiring external pull-down resistors to –24V Photographs, tracings of hidden tracks and measurements supplied by Jef Ongena of Belgium. (logic 0). The internal construction of discrete gates is shown in the following diagrams. A wire–OR or wire–AND construction is indicated by the input line traversing the width of the gate. The design is heavily optimised for component reduction with many gates having one input Log formed from the pull-up/down load resistor, rather than a diode and fixed-supply resistor. • 2023 Aug: Initial drawing / bhilpert. Positive-Logic AND Positive-Logic OR ‘wired’ input r r r Differences Negative-Logic OR Negative-Logic AND Two units of the IME-41 have been examined with several differences observed between the two. These differences r r and the components involved are noted in blue text , the units distinguished as #J and #S. The IME-41and Riccar model from TEAL are nearly identical in logic design. Most of the differences between the two IME-41 units bring the #S unit closer to consistency with the Riccar. R R R The diodes may be individual components or contained in 4-diode TSxxx modules. Gate inputs are identified either by a pin number in the case of a diode in a module, the ID of the discrete diode forming the input, or the R value in the case of a resistor. For gates with fixed-supply load resistors (R), to reduce clutter, the resistors are indicated in the schematic by one of the following letters (r) in a box by the output. Symbol (r) Resistance (R) Symbol (r) Resistance (R) # 10K to VDD a 110K to GND 3 30K to VDD b 200K to GND 5 50K to VDD 1 110K to VDD d 30K to GND 2 200K to VDD e 300K to GND 30 300K to VDD #J: ‘1’ is 110K to VDD. #S: ‘1’ and ‘a’ are 100K to VDD . Other 110K are also 100K. Clocking Scheme The flip-flops in the JMOS logic family are a form of Master/Slave D-type flip-flop with the clocks for the master and slave sections kept separate. This permits a system design where data capture is done in accordance with the requirements of the logic while outputs are changed synchronously by a single clock signal. TEAL: IME 41 ØC = Capture Input (master section clock) ØT = Transition Input (slave section clock) Calculator The state of the D input is captured when ØC is logic 0 (–24V). The Q output is set in accordance with the captured state when ØT goes to Section: Notes, Signal Names & Logic Design logic 0. Page: 2 Rendition: Oct 15, 2023 Timing Power Supply V–24 V–N, V–D ØC ØT ØB1,2,4,8 ØEOD ØD0::16 ØEON bit digit logic supply display supply phases phases Keyboard KPN KPD KPR KPO Control FKOP FDAT Flag Flag Flag Flag Flag Flag State ERR Machine Flag Primary Loop Counter OPAS/MD OPAM/SD OPEA/ES OPE FDP FDPAL K0…K9 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Flag Flag Flag Flag Flag Flag ST11 ST35 Numeral Encoder Interim DP Counter Control 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Signals Numeral KNUM Serializer Display DP Counter 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RX Register RX 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Arithmetic: Leading-Zero Blanking Counter RX,RY,RM: BCD Serial Adder 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 16 BCD digits / 64 bits, RY Register RY A 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Digits 0::11 are entered & displayed BCD Sum Oper. Correction Norm. ØDn Adder Adder SUM RM Register RM B 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 4 bits Digit Drivers B–A N1 Sign M Sign I Display Latch N2 Flag Flag Add / (4 bits) Subtract N4 Decoder 109876543210. Sign D Logic N8 Drivers TEAL: IME 41 Flag 12 Calculator Neg. Vacuum Flourescent Lamp Display Tubes Section: Block Diagram Page: 3 Rendition: Oct 15, 2023 184µS 46µS 10 µS ØC 8µS 5µS 23 ØC / ØT frequency = 22 KHz. µS ØT Number cycle = 16•4•ØT = 2.9mS = 340Hz. TB0~ TDx~ 0 2520 2700 2880 0µS 180 360 540 720 900 1080 1260 1440 1620 1800 1980 2160 2340 2520 2700 2880 3060 ØC ØT ØB1~ ØB2~ ØB4~ ØB8~ logic 1 (0V) ØD16~ logic 0 (–24V) 14 15 16 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 ØD0~ ØD1~ LSD MSD Display Display ON ON One number cycle in registers TEAL: IME 41 Calculator Section: Timing Diagram Page: 4 Rendition: Oct 15, 2023 Master Clock Bit Phases Ring Counter ØB2~ 110K 110K DW9 5K 5K 200p 330p 330p 5 ND.17 TT1 DW8 A611 3 # 9 1 6 3 11 1 DW7 TU2 TU1 50K D Q UU2 D Q D Q ØC 4 10 5 12 C371 C371 ND.18 UV1 UV1 UV1 5K DV2 DV1 2 1 ØC ØC ØC ØC ØC ØC 7 10 3 3 ND.4 2K ØT ØT ØT ØT ØT ØT UW1 ØB1~ 15 330p TT2 A611 110K ND.19 ØT ØB8 ND.16 5K 3 ND.10 1 UW1 ØB8~ 16 ND.22 ØB4~ Digit Phases Ring Counter 2 3 ACIN 2 ACIN 1 1,2 b ACC 1 ACC ØB4~ 4 MAU1 13 6 13 6 ØB4~ ØC ØB4~ ØC 2 ØC 8 ACT 8 ACT 1 7,10 ØB1~ ØT DQ ØB1~ ØT DQ ØB1~ 9 9 ØT ØT ØT ØC ØC ØC ØC ØC ØC ØC ØC ØC ØC ØC ØC ØC ØC ØC ØC 1 4 1 1 3 DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ UW1 DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ 14 ØT ØT ØT ØT ØT ØT ØT ØT ØT ØT ØT ØT ØT 6 ØT 11 ØT 14 ØT UT3 UT2 UT1 1 12 1 11 1 10 5 5 4 5 3 5 12 5 11 10 5 4 1 3 1 4 1 5 1 12 1 13 ØD1~ ØD2~ ØD3~ <–– ØD to display ––> ØD4~ ØD5~ ØD6~ ØD7~ ØD8~ ØD9~ ØD10~ ØD11~ ØD12~ ND.7 ND.8 ND.6 ND.9 NE.S2 DP ØD15~ ØD16d~ ØD0~ ØD1~ <–– ØD to logic ––> NK.S16 4 SELECT ØD12~ ØD13~ NK.C16 3 6 3 11 3 NK.S14 2 NK.S18 NE.C2 UW1 UW1 ØDPS~ 13 12 NK.S15 0 NE.C6 ND.14 ØD16 ØD16~ DW10 ØC 5 DW11 ØEOD~ End Of Digit ØB8~ ND.29 TEAL: IME 41 DW12 1 ØEON~ End Of Number Calculator