Schematic · 2014
Casio 121-B Calculator: Reverse-Engineered Schematic
A 10-page schematic of the Casio 121-B of 1970: Hitachi HD3100 PMOS chips, the NEC uPD116C Nixie decoder-driver, Toshiba high-voltage drivers and multiplexed Hitachi CD-71 Nixies.
Schematic · 2014
A 10-page schematic of the Casio 121-B of 1970: Hitachi HD3100 PMOS chips, the NEC uPD116C Nixie decoder-driver, Toshiba high-voltage drivers and multiplexed Hitachi CD-71 Nixies.
Casio 121-B Calculator Contents Section Casio 121-B Calculator Section: Title & Contents Page: 1 Rendition: 2014 Mar 7 Page Title & Contents (this page) 1 Notes 2 Block Diagram & Signals List 3 Timing Diagram 4 Timing & Keyboard 5 Control - 1 6 Control - 2 Registers & Arithmetic 7 8 Display & Power Supply 9 IC Pinouts 10 This schematic has been derived through reverse engineering. This is not the manufacturer’s schematic, nor is it based on the manufacturer’s schematic. Notes ♦ The symbol denotes a physical connector pin. Solid black end is the male side of the connector. White end is the female side of the connector. ♦ The symbol boards. ♦ The symbol denotes a connection between the two main printed circuit Logic Implementation Notes on the Integrated Circuits Most AND gates are constructed from discrete diodes and resistors. Most OR gates and more complex logic elements are contained in integrated circuits. Gate symbols and signal names are presented in accordance with negative logic: logic 0 = 0V, GND logic 1 = V–24 The integrated circuits are from an early family of MOS SSI / MSI technology produced by several Japanese manufacturers during the late 1960’s to early 1970’s. (Note these ICs are not CMOS and should not be confused with standard CMOS series ICs.) • Outputs are open-collector, except SSR0109. • Inferred for HD3103: The 5 elements are not standard logic elements. They appear to be MOS transistors. They function as a bidirectional switch, or as a 2–input OR gate with one input inverted. denotes V–24. ♦ Capacitance in microfarads unless otherwise indicated. ♦ These drawings based on unit with Serial No. ?. ♦ See www.cs.ubc.ca/~hilpert/eec for additional information. The internal construction of discrete gates is shown in the following diagrams. A wire-AND or wire-OR construction is indicated by the input line traversing the width of the gate. In a few instances the load resistor for the gate is itself used as an input. r r a a a a b b Log switch is closed when control input b is TRUE (–24V) ♦ 2006 Dec: Data collection by Mick Metselaar. Care is taken in the logic design to ensure another “wire-ANDed” output does not feed back through the element to affect the state of the signal driving the noninverted input. One location where this situation is somewhat ambiguous is the use of 2-1B5 between signals CXDA and CXEE on page Control 2. ♦ 2007 Jan: Formatting and organisation by bhilpert. Outputs from ICs also generally require an external load resistor connected from the output to V–24. To reduce clutter load resistors are indicated in the schematic by a symbol in a box above the output: 1 = 100K discrete 2 = 220K discrete D = discrete resistor, value undetermined M = modular package resistor – = no load resistor 5 = 56K discrete • Inferred for flip-flops: The flip-flops in this logic family appear to be Master/Slave D-type flip-flops with the clocks for the master and slave sections kept separate. This permits a system design where data capture is done in accordance with the requirements of the logic while all outputs are changed synchronously by a single clock signal. ØC = Capture Input (master section clock) ØT = Toggle Input (slave section clock) The state of the D input is captured when ØC is TRUE (–24V). The Q output is set in accordance with the captured state when ØT goes TRUE. • Inferred for HD3112: This device is a full-blown Serial BCD Adder, performing serial addition, bit carry, tens carry, correction for digit sums greater than 9, negation, etc. ?? = seemingly missing from source drawings In a few circumstances the discrete load resistor may be absent: • When a gate drives only diode inputs (which are later followed by a load resistor), as opposed to driving the gate of a MOS transistor. • The SSR0109 shift register, which appears to have internal resistors on the outputs. logical equivalent S-R Flip-Flops In several instances, S-R type flip-flops are constructed from simple gates, the following structure being the basic form: Gate Identification Gates and logic elements are identified by a name taking the following form: SET r Q nRESET Unresolved Issues & Questions A few issues from the reverse engineering present questions. These are listed here: • No load resistor shown for flip-flop output 2-2V2-4 (Control - part 2). • No load resistor shown for inverter output 2-2V3-9 (Control - part 2). • No load resistor shown for OR output 2-1D1-7 (Arithmetic). • No load resistor shown for OR output 2-U1-11 (Arithmetic). • No load resistor shown for OR output 1-1D2-9 (Arithmetic). • Two load resistors are shown for OR output 1-U1-3 (Control - part 1). • Flip-flop output 2-2V2-5 is controlled by a wired-AND connection (Control - part 2). • Flip-flop output 2-2V3-12 is controlled by a wired-AND connection (Control - part 2). Casio 121-B Calculator Section: Notes Page: 2 Rendition: 2014 Mar 7 The OR gate will be within an IC and provides gain for the circuit. The AND gate is simply one diode for each nRESET input. <board> – <type ID><enumeration> where <board> = 1 (upper PCB ) 2 (lower PCB) <type ID> = A (discrete AND gate) O (discrete OR gate) N (discrete NOT gate) other (within an IC, see ‘IC Pinouts’ page) <enumeration> = 1 to n When possible the names have been obtained from labelling on the PCB’s, however if n≥50 the name has been created for this schematic. Signals List Some signal names are derived from labeling on the printed circuit boards. Others have been created for this schematic. A lowercase “n” at the beginning of a signal name indicates the logical NOT operation. Section Timing Boards Ø1 Ø2 Block Diagram J1 J4 ØK Timing Ø C ØT PowerSupply ØBx bit timing V–24 ØDx digit timing K1 K5 K12 KE Øe V+90 V+180 Keyboard =+ =– x ÷ Control D Register Controls G/P Cycle Generator Keyboard K… G1 G2 P1 CX01 Operation Selection Logic E Register Controls State Registers, Sequencing and Selection Logic Control X0 DP Counter Controls EN 000 =+M ADD N x÷ F ABRW A0 KDATA Decimal Point Counter D Register (displayed, 48 bits) Arithmetic E Register (2nd operand, 48 bits) Z0 Qt PQ N0 A0 W2 W4 W8 Display Latch, Decoder, Driver (4 bits) 12 Digit NIXIE Display F Register (total & quotient, 48 bits) Arithmetic Casio 121-B Calculator DP Counter Signals derived directly from the keys. Function keys. Encoded numeral key bit stream. Numeral key pressed. Counter for generating operation cycle. A single number cycle for executing most operations. Operation selection signals. Begin New Number flag. Multiplication pending. Division pending. Enter Numeral. Enter 3 zeroes. CX… CXAS CXSH CXIQ CXDD CXDA CXEE CXEA CXFF CXFA Other control signals. Add during multiply, subtract during divide. Shift register left during multiply and divide. Increment Quotient in F register. D register receives from D register. D register receives from Arithmetic. E receives from E. E receives from Arithmetic. F receives from F. F receives from Arithmetic. ? ? Negate. Recall total. Multiplication by Constant. Quotient. Product or Quotient. Subtract from total flag. F 12 digit register for the displayed number. 12 digit register for the 2nd operand. 12 digit register for total of multiplications and the quotient. W=0 nABRW Arithmetic sum. Digit numeral data on the way to the display latch. Numeral is zero. Indication of Borrow during a subtraction. A0 W2,4,8 Z0 Digit periods. CP… CPNN CPX0 CPD0 CPEN CP000 CPAM CPADD CPN CPMD CPF CPCM CPQt CPPQ W0 MC D Register E Register F Register Section: Block Diagram & Signals List Page: 3 Rendition: 2014 Mar 7 K… KADD KSUB KMUL KDIV KDATA KNML P Arithmetic Controls Description Uninterrupted repetitive signals. Master clock capture phase. Master clock update phase. Bit periods. End-of-number-cycle pulse G1,2,3 F Register Controls CP… W=0 Schematic Ø… ØC ØT ØBn ØB1 ØB8 ØB8•C ØDn ØD0 ØD4 ØD11 ØD12 Decimal point counter is at 0. 1080 0µS 80 160 240 320 400 480 560 640 720 800 880 0µS 1040 960 80 logic 0 (GND) (50 KHz) ØC logic 1 (V–24) ØT (12.5 KHz) ØB1 ØB2 ØB4 ØB8 ØB8•C (960 Hz) ØD0 ØD1 ØD12 Øe Digit Latch 1-?-12 (µPD116C) D register with 5 in the display. D Digit in Arithmetic Unit 1 1 2 3 4 5 6 Digit being displayed, also ØDn 12 - 1 (LSD) 2 3 4 5 Casio 121-B Calculator Section: Timing Diagram Page: 4 Rendition: 2014 Mar 7 7 8 9 10 11 12 1 1 6 7 8 9 10 11 12 (MSD) - One full number cycle in registers PG 1-? ? ? ? ? ? ? ? ? 1-? ? ? D Bit Timing ? ØC Ø1 ? 16 14 ? Q 11 D 13 1-2V1 1-N2 ? ØC ØT Master Clock D M 1 10 Q ØC ØC ØT ØT ØT 1-A51 D ØB48 9 1-A52 M ØB1 ØB2 ØB24 12 1-2V1 ØC 1-2V3 ØB12 16 1-A53 M ØB18 9 1-2V2 ØB4 D 1-A54 ØB8 ? ? Ø2 ? ? 0 ØT ? 1-N4 ? 1-N1 ? nØB8 nJ4 ? 1-? 0.3 3.3 ?V ? ? 6 1-1D1 7 1-A55 ØC D ØB8•C ØK ? 1-? ? 11 5 12 6 nINIT 1-? ? 10 4 5 D SH ? 9 3 POC ? 8 2 ? Power-On Initialisation 5 1 7 D 1-A56 ØD12 ? ? ØD12 16 8 D 9 2 Øe Øe 1-2V4 13 9 nØD12 nKE 3 4 0 1 2 3 4 1 3 5 7 9 1-2N1 D 1-A58 D 1-A59 D 1-A60 D 1-A61 8 Internal structure presumed 2 3 6 7 9 11 5 6 7 8 4 5 6 7 11 8 3 9 9 Keyboard 6 Digit Timing 0 nINIT KNML 15 M 3 16 1-1B1 14 D Q M 1-A57 4 D 11 D 1-2V5 2 ØB8•C 7 ØT Q M 6 12 D ØC ØB8•C ØT ØT 10 Q 3 5 D 1-2V4 1-2V4 1 M ØC ØB8•C ØT ØT KE 2 7 Q M 14 4 D 1-2V4 Q M 11 13 D 1-2V4 Q M D C 12 KCLR 1-2V2 ØC ØB8•C ØC ØB8•C ØC ØB8•C ØT ØT ØT ØT ØT ØT 1 10 POC ØC T D 000 D += D –= D ØT KTOT K1 K5 K000 ØD12 ØD1 ØD0 ØD2 ØD3 ØD4 KADD 6 D Q M 3 5 1-2V2 ØB8•C ØT 2 7 D Q M 14 4 1-2V2 D Q M 11 13 1-2V2 D Q M 6 12 1-2V3 ØC ØB8•C ØC ØB8•C ØC ØB8•C ØT ØT ØT ØT ØT ØT 1 10 D Q M 3 5 1-2V3 ØC ØB8•C ØT ØT 2 7 D Q M 14 4 1-2V3 D Q M KSUB 13 1-2V3 ØC ØB8•C ØC ØB8•C ØC ØT ØT ØT ØT ØT × D ÷ D KMUL K12 ØD5 ØD6 ØD7 ØD8 ØD9 ØD10 ØD11 KDIV 1-O51 1-O52 Casio 121-B Calculator Section: Timing & Keyboard Page: 5 Rendition: 2014 Mar 7 12 M 14 1-1D1 16 13 D KAS D KMD 1-O53 D KASMD 10 1-1D1 9 KDATA FEC G3 KCLR KT K000 KASMD KNML 1-O54 D 16 1-2V5 ? 11 1-A62 D 9 Q D 12 14 1-2V5 1 Øe Operation Cycle Generation 10 ØT Øe 2 D Q G2 D 13 6 5 2-1D3 7 1-2V5 ØC Øe ØT ØT 1 10 FEC 1-A63 D Q 5 4 G1 2-2V3 ØC Øe ØT ØT G1 3 2 7 G2 ØC ØT G3 G2 P 10 11 1-1B1 9 1-A64 M P K000 G1 KNML P 16 1-A65 KCLR 15 1-1B2 M 14 nAC 000 1-A76 1-A77 G2 1-A66 EN nAC 9 1-U1 8 Øe 1-A67 M 4 D 1-A78 Øe 10 KASMD D nCENPE 1 2 1-1B1 1-A68 M CPNN 3 P 1-A69 M M 3 1-1D1 1 4 3 D Q M 4 2 7 1 CPX0 ØC KMUL CPNN 2 1-U1 3 1-A70 1-A71 10 1-1B2 M 9 D 1-2V1 2 7 ØC ØT D 5 ADD 1-A83 KTOT F 1-A84 14 12 1-1D2 16 13 12 13 1-U1 11 1-A73 KMD x÷ 1-A82 1-A74 M Qt 1-A85 M 5 CPF CPAF KADD M 6 1-1D2 7 CPNN =+M 1-A86 5 16 2-1B4 14 1-A87 6 5 2-1B3 7 RS nAC 1-A75 – P CPAM 15 3 Rendition: 2014 Mar 7 CPADD P 1-A72 nCPNN CX01 CPMD nCENPE CPQt P Casio 121-B Calculator CPN P CPD0 KAS Section: Control - part 1 Page: 6 CPKC P CPCM nAC Q KC N KMD KAS nCPNN M D P ØT 11 P 6 nCENPE P 2 1-2V1 ØT M 4 1-U1 6 1-A80 1-A81 nCPNN nINIT nMC KDIV 5 KSUB 5 1-1B1 7 ØT M 13 CPEN D KCLR 6 KMUL 1-A79 CPNN Operation Selection 1-1B1 12 CP000 2 1-1D2 1 4 1-A88 D PQ nCPAM CPPQ 14 nABRW 1 Øe 10 ØT CX04 CX06 nW=0 CXDA CPPQ nW=0 ØD11 ØB8•C ØD4 CXDD CXSH Q D 13 nBRWC 2-2V3 State Registers & Sequencing CX05 D 2-A21 2-A20 2-A19 2 nBRWC 2 3 2-1D3 1 4 D 2-A55 State Selection Logic ØC D Q 5 5 2-2V3 2 Øe 2 7 CXFF CPPQ 2-A15 1 2-1B3 3 ØT 2-A56 1 CPADD CPMD nW0 CXSH CPPQ CX01 11 2-1D3 9 CX04 1 CPF ØD0 2-A58 1 CX06 CPX0 16 1-2V1 CPQt nCX04 CX01 nX0 9 6 2-A18 D 11 D Q 12 Øe ØT 1 10 nBRWC 2-1B5 2 12 nW0 nBRWC 10 11 2-1B3 1 14 12 2-1D3 16 13 2-A51 1 ØT 2-A7 3 CPEN CP000 CXSH M CX04 M 4 2-1B5 13 nCX04 ?? 4 CX01 D Q CPQt CXSH CXDA 2 7 12 6 D Q 2-2V2 Casio 121-B Calculator Øe ØT 2 7 ØC ØT 10 nW0 2-A52 5 CPKC D 11 2-1B5 9 M 1 2-1B2 3 CX12+13 ØD4 CXSH nCX15 CX15 2-A13 2 16 10 11 2-1D1 9 2-2V1 2-A61 9 D ØT 12 M 2-1B3 13 CX14 CX13 CX15 D Q M 12 14 ØC ØT D 2-1C2 M 13 ØC ØT 1 9 2-2V2 3 2-2V2 1 10 nCX15 Z0 16 Q M 9 2 DPF 2-2V2 10 4 2 2-A24 CXDA 12 5 13 2-1D2 16 14 2-A8 11 CXFF CX12 10 1 ØB8•C nW0 nØD12 Rendition: 2014 Mar 7 CXFA 2 ØT M 4 1-1B2 13 nMC nMC 3 5 2-U1 6 DPA CPCM – 7 M 2 2-U1 3 Decimal Point Counter ØC CXEE 2 2-A14 1 CPPQ Section: Control - part 2 Page: 7 4 CXIQ 2-2V2 Øe 9 F ØD11 ØC 3 1 2-A53 ?? MC 2-1C2 ØT 1 2-A9 5 14 nX0 ØC nAC Z0 W=0 CXDA nCX15 Øe 2-A54 2-1B5 M 2-A60 CXAS 2-2V3 CX21 15 9 M 5 2-1D2 7 12 13 M 14 2-1C2 16 11 CX05 nBRWC CXAS CPQt 2-2V3 6 CPAM CXIQ 11 2-1D2 9 CXDA 16 CXEA 2-A59 CX05 10 2 1 5 2-1B4 7 12 1 13 2-1D1 16 14 2 CX22 2-A17 CXDD 6 CX12+13 2 ØC 1 10 2-1D4 9 CXAS nCX04 CPQt D 2-1B3 14 15 1 11 16 2-A57 16 2-A11 10 2 2 nX0 ØT 6 ØT CX06 D Q M 4 nZ0 6 2-2V1 2 7 ØC ØT nZ0 D Q M 5 11 2-2V1 2 7 ØC ØT D Q M 12 14 2-2V1 1 10 ØC ØT D Q 2-2V1 1 10 ØC ØT M 13 2-A16 CXDD 2-A12 CXDA nCPAM KDATA ØD0 CPEN 1-A89 2 1 M 2-A25 CXDA CX14 2-A23 CXDA 2 DINP 6 DA1 QA4 1 5 12 DB1 2-2J1 10 ENC ØC 2 3 2-1D4 1 4 5 2 6 2-1B2 2-A62 2 QB44 8 2-2J1 10 ØC ØT 2 ØT 2-A65 2-1B1 CXIQ ØC CPKC 2-A67 ØD0 ØT ØD12 CXAS CXDA nMC 2 M 14 2-A22 ØD0 1 ØD12 CX13 M 13 12 2-U1 11 2-A68 4 ?? 12 10 11 2-1B2 9 2 16 M 2-A69 2-1B4 8 nA nSUM M 15 15 2-1B2 2-A75 M 11 nW2 nQ2 M 14 nW4 nQ3 M 16 nW8 A0 A0 ? 1-N6 ? ? nQ1 M 14 13 ØB1 CXDECMSD 2 2-A74 CX13 2 4 5 2-1C2 1 3 M M DCENB 7 2-A66 16 15 ØT nØD12 CX12 CX14 D Register 3 1 2 2-1D2 1 4 2-A4 ? W2 ? 2 1 2-1B4 3 5 6 1-1B2 D 7 W4 1-1B2 D 3 W8 Arithmetic CXEE nCPAM nAC 2-A5 CXEE M 4 2-1B1 13 nØD12 CXEA CX12 CXDD CX14 5 12 2-A26 2 6 M 7 EINP ØC M 2-1B5 2 DA1 QA48 14 2-A64 13 2-1D4 16 ECENB 12 ØT 3 M 11 2-1B1 9 6 4 2-2W1 1 2-A1 10 E Register 2 CXEE ØC 2 ØT CXFF ØD12 CXFF CX12 M nQ4 18 M 5 2-1B1 7 2-A3 M 1 2-1B1 3 nW0 CPMD 2-A70 12 ? 2 4 2-1B2 13 3 5 4 2-1C1 1 2 M 2-A71 2 6 D W=0 10 1 11 2-1B4 9 10 2-1M1 Serial BCD Adder M 2-A2 1 2 2-1C1 7 nB 7 FINP CXFF nCX15 nAC nMC CXFA 2-A6 10 nØD12 M 9 2-U1 8 8 DB1 QB48 2-2W1 5 ØC CX22 6 2-1D4 24 ØT 2-A10 2 1 ØC F Register 2 7 2-A63 M ØT 9 10 20 nØB8 F 5 ØC nØD12 ØT 13 FCENB 21 nX0 11 KSUB nCENPE Casio 121-B Calculator Section: Registers & Arithmetic Page: 8 Rendition: 2014 Mar 7 10 1-1D2 9 1-A90 ?? N0 CXDECMSD CPN CX21 2-A73 2 ØT ØnB8 ?? 19 Øn(DE•B8) 6 2-1D1 7 ØC 7 ØC 14 12 M 10 2-1C1 13 2-1C1 16 11 M 9 9 ? ? nSUB ? nCY 2 M 17 2 1 4 2-1D1 1 3 nABRW nW=0 violet 390 235V 215V 114V 98V ? AMP. POWER DIGIT 12 (MSD) ? 14 ØD12 0.022 ?V 1-2P1 DIGITS 11 to 1 (LSD) 1 ? Hitachi 1 3 5 7 9 CD-71 0 2 4 6 8 . 13 D1 14 D2 16 D4 17 D8 A0 W2 W4 W8 0 1 2 3 4 5 6 7 8 9 1-? 1-E1 ? ? 1-N3 ? ØB8 12 L ? ? ? 18 19 1 2 3 4 6 7 8 9 Digit 12 11 10 9 Driver 1-2P1-14,1 1-2P1-12,3 1-2P1-10,5 1-2P1-8,7 8 7 6 5 1-2P2-14,1 1-2P2-12,3 1-2P2-10,5 1-2P2-8,7 4 3 2 1 1-2P3-14,1 1-2P3-12,3 1-2P3-10,5 1-2P3-8,7 yellow ?VAC 10 ?V 100K 10 ?V 100K brown pink brown ?VAC ? orange ?VAC GND black 220 brown C970 220 ?V 2.2K 100 ?V 1K 5.6K 2.7K 0.3 AMP. ? –24V grey V–24 ? 8 8 12 7 11 7 20 8 5 11 D Q 1-2V5 ØB8•C ØC ØT ØT D 5 ? b-1Bn b-1Cn b-1Dn 2-1M1 2-2J1 2-U1 1-? b-2Vn 2-2W1 1-2N1 b-2Pn HD3104 HD3106 HD3112 HD3117 µPD101C µPD116C TM4351 SSR0109 T1191 T4097 15 15 22 23 3 14 14 11 10 15 6 7 13 ? 4.7K ? ? ? ? nØB8 Casio 121-B Calculator Section: Display & Power Supply Page: 9 Rendition: 2014 Mar 7 4 HD3103 V+90 1-N5 ? V–24 V+180 V+90 8 1K 6 V+90 V+90 ? ? nZ0 V+180 List of Integrated Circuits IC Type IC Type 1-U1 µPD101C 2-U1 µPD101C 1-? µPD116C 2-1B1 HD3103 1-1B1 HD3103 2-1B2 " 1-1B2 " 2-1B3 " 1-1D1 HD3106 2-1B4 " 1-1D2 " 2-1B5 " 1-2N1 T1191 2-1C1 HD3104 1-2P1 T4097 2-1C2 " 1-2P2 " 2-1D1 HD3106 1-2P3 " 2-1D2 " 1-2V1 TM4351 2-1D3 " 1-2V2 " 2-1D4 " 1-2V3 " 2-1M1 HD3112 1-2V4 " 2-2J1 HD3117 1-2V5 " 2-2V1 TM4351 2-2V2 " 2-2V3 " 2-2W1 SSR0109 0.047 16 15 14 13 12 11 10 9 16 15 14 13 12 11 10 16 9 15 –24V Hitachi Hitachi HD3103 HD3104 id: 1B id: 1C 12 11 10 5 6 7 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 16 14 13 ? nØB8 nQ4 nØ(DE•B8) ? nQ3 nSUM nQ2 9 id: 1D 1 ? 15 0V 2 3 4 5 6 7 8 Hitachi Hitachi 1 2 3 4 14 13 12 11 10 –24V –24V DB1 0V In ØC id: 2J id: 1M –24V 1 2 3 4 5 14 13 12 11 10 nB nA nNEG nQ4 nQ1 0V 6 7 8 12 9 8 9 10 11 1 –24V 19 N1 NEC NEC µPD116C µPD101C id: ? id: U 1 14 Toshiba T1191 id: 2N 1 2 12 11 N0 B8 B4 B2 B1 L BCD to Decimal Latch / Decoder / Driver for NIXIE Displays L: Latch clock input Bn: BCD bit inputs Nn: Numeral (NIXIE cathode) outputs 18 17 –24V 0V N2 N3 N4 N5 16 15 7 8 9 10 1 2 3 4 5 6 13 12 11 10 9 8 14 13 12 11 10 9 K6 K5 K4 K3 K2 K1 B4 B2 B1 Kn : Numeral key inputs Bn : Encoded BCD outputs. PRESS : Key pressed output. B8 PRESS K7 K8 K9 K0 –24V IN 1 2 3 4 5 6 1 8 IN 4 OUT 1 1 OUT OUT 2 V+84 3 2 3 4 ♦ Logic 0 = 0V Logic 1 = –24V ♦ Outputs are open-collector, closing to 0V (logic 0) and requiring external pull-down resistor to –24V (logic 1), except for SSR0109. 5 OUT 4 6 7 5 6 7 15 14 13 12 11 10 –24V D Q ØC ØT Q ØT D ØC ØC ØT D Q ØT Q ØC D 3 5 6 2 10 ? SSR0109 T4097 7 Rendition: 2014 Mar 7 IN V+180 IN 2 3 4 id: 2V –2V 7 3 9 TM4351 N9 6 16 2 Toshiba N8 5 id: 2P 13 N7 4 Toshiba 14 N6 3 Casio 121-B Calculator Section: IC Pinouts Page: 10 20 0V 8 QB44 Out QA4 DA1 Out In 0V ØT ? 8 Dual Shift Register (4 & 44 bits) HD3117 Serial BCD Adder ØC 9 HD3106 0D 0V 1 HD3112 13 Hitachi 0V ØT –24V –14V 14 –24V id: 2W 9 4 8 7 Q48 ØT D1 ØC 48–bit shift register 48–bit shift register ØC D1 ØT Q48 1 2 3 4 6 –24V 0V 5 0V 7 8