Schematic · 2024
A 22-page schematic of the Canon 163 Nixie calculator of c. 1968-69, drawn from two working machines: block diagram, timing, the torsional delay line and its amplifiers, TI DTL logic, the 1-2-4-2 serial adder, the multiplexed Nixie display and the +100/+200 V display supplies.
Canon 163 Calculator Schematic Contents Section Title & Contents (this page) Notes & Signals Block Diagram Timing - Bit & State Cycle Timing - Digit Keyboard Control - Function Flags Control - State Machine Control - Misc. Flags Point Counter Input Selectors & Flags PA Register & Comparator PB Register & Decoding Sign Flags Arithmetic Input Selectors Memory Input Selectors Arithmetic Memory Display Power Supply IC Pinouts & Board Orientation IC Types & Tallies Connectors Canon 163 Calculator Section: Title & Contents Page: 1 Rendition: Feb 5, 2024 Page 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 Appendix Section Flip-Flops & Discrete Gate Construction Timing Diagram Memory Organisation Memory Timing State Sequence - Short Procedures State Sequence - Add/Subtract & Multiply State Sequence - Divide & Square Root Procedure Execution Timing Square Root Procedure Sample Page A1 A2 A3 A4 A5 A6 A7 A8 A9 This schematic has been derived through reverse engineering. This is not the manufacturer’s schematic, nor based on the manufacturer’s schematic. Sections and Signal Descriptions Notes A lowercase “n” at the beginning of a signal name indicates the logical NOT operation. ♦ Gate symbols and signal names are presented in accordance with: logic 0 = 0V, GND logic 1 = +5V Section Timing bspp TP0 TP67 Description Read clock, rate at which bits are retrieved from the acoustic delay line (500KHz). The bit clock, rate at which bits are processed (250KHz). Write clock, a narrow pulse to form the bit pulses written to the acoustic delay line. Clock for Point Counters. Clock pulse to define bit 0 of digits. Clock pulse to define bit 3 (W) of digits. Clock pulse to define digit 0 (LSD) of numbers. There are 17 digit periods. Bits of the displayed digits are contained in periods 0 to 15 and displayed during periods 1 to 16. Digit 16 (MSD) clock period. State Cycle phases. There are 5 phases to a state cycle, each being a number cycle of 17 digits. The first bit in a number cycle. The last bit in a number cycle (17•4-1). Keyboard K… The keyboard and numeral encoder. Control CC00::CC17 FST FU FMLT FDIV FRT FME FN FG FJ1 FC0 FRS FOVF FM1,FM2 FV @… The states of the procedure execution state machine. Procedure start. Procedure initiation pulse. Multiply operation. Divide operation. Square Root operation. M2 Add/Subtract or M2-Sum operation. New number in display. For constant mode, indicates a constant operand is in RA. - DP has been pressed during number entry. - Number went negative during subtract, held till EOS. - Delayed action indicator for DP alignment. - 2-iteration loop counter for complementing negative results. - During SQRT, loop counter for double subtractions. Temporary used during DP alignment. Direction of shift during DP alignment. 1 is RIght-Shift (down). Overflow flag. Flags to control the Memory 1 & 2 lamps Flag to control the thousands-separator lamps. Assorted control signals, otherwise unnamed, name derived from IC output pin. Signs SA SB SK SM1 SM2 Sign of A register. Sign of B register. Sign flag that is actually used to determine add or subtract . Sign of Memory 1 register. Sign of Memory 2 register. Memory WA WB BD0 AD0 BD SD Bit stream of A,C,D,M1,M2 registers to be injected into the acoustic delay line. Bit stream of B register to be injected into the delay line. Bit stream of B register from the delay line. Bit stream of A,C,D,M1,M2 registers from the delay line. A 4-bit register, part of the B register bit stream. A 4-bit register used for keyboard input, display output and shifting. Arithmetic RSUM AD Raw (uncorrected) binary sum from the adder. A 4-bit register in which 1242 decimal sum correction is performed, and part of the A,C,D,M1,M2 bit stream. Carry output from the adder. Signals associated with the arithmetic carry flag. ♦ The symbol denotes a physical connector pin where b=board (K,1-8), s=section (A,B,C,D), and pp=pin. Solid black end is the male side of the connector. White end is the female side of the connector. ♦ connection between different sections. connection limited to same section. Arrows indicate direction of signal or energy flow. ♦ The symbol denotes V+5. The symbol denotes V–5. TD16 SCT0-4 ♦ These drawings based on unit with serial number 122900. These drawings should also apply to the Monroe 990. Log ♦ 2005 Jan ♦ 2014 ♦ 2021 Mar ♦ 2024 Jan Initial drawing / bhilpert. Format updates, basic state sequence timing diagram/ bh. Logic presentation improvements - negative logic gates, organisation refinement /bh. Extensive improvements , appendix and Theory of Op documents. To do: convert to ~ NOT notation, complete expander-diode inclusion in gate symbols. Gate Identification FJ2 Gates are identified by symbols taking the following form: bree where b = Board 1 to 8 r = Row 1 to 3 ee = Enumeration 1 to n Signal Names Many signal names were obtained from labels on the printed circuit boards. Not all signals have such labels however, so the following names have been created for this schematic: CPR CPW TDBx SCT01 SCT12 SCT34 nTD0+TB3 K(M+D) KRM(1+2) K(C+CI+CM) FST LDNML F(MQ+DQ) nSUM<0 F(M+D) M F(M+D+R) RSUM F(D+R) CA n(KOP•FU) nENDSP nENDLP <== nEND nENDP <== nEND2 en… @… Signal CPR CPA CPW CPC TB0 TB3 TD0 PASUM PA PB1 PB2 PB=TD ACA CA… PA Register PA DL=PA DL<PA Bit stream output from the PA register. PB… PB=0 PB=TD LP Bit stream outputs from the PB register. Relationshsips between the PA register and the selected number of decimal points. PB Register Canon 163 Calculator Section: Notes and Signals Page: 2 Rendition: Feb 5, 2024 1 when the digit counter hits the decimal point digit. A latched version of PB=TD to turn on the decimal point for the appropriate digit. Timing CP… Keyboard AC -> 7 8 9 R1 RV 4 5 6 C1 C2 1 2 3 C CI 0 • * K ÷ √ + – K… R2 2– TB… Bit timing FMQ flag FMLT flag FDQ flag FDIV flag Power Supply TD… Digit timing –5V SCT… State Cycle timing FKD mono FST flag FRT flag FN flag FJ1 flag FME flag FG flag FJ2 flag FU flag Numeral Encoder +100V +200V display supplies State Machine 2+ K0…K9 +5V logic supplies CC00 CC17 FOVF flag Overflow lamp FV flag Thousands lamps Control K…, F…, CC… AD0 flip-flop G-X CA G-Y Arithmetic (serial adder) Sign Flags Sum Correction SM2 flag WA AD register (4 bits) Magnetostrictive Acoustic Delay Line (670-671 bits) M flip-flop SA flag Negative lamp SB flag WB G-BD BD0 flip-flop SM1 flag Digit Registers BD register (4 bits) SK flag SK G-SD SD register (4 bits) G-PX PCA Arithmetic (serial adder) FM1 flag M1 lamp FM2 flag M2 lamp G-PB PCA PA register (5 bits) PA comparator PL register (5 bits) FP5 flag DL=PA G-PY Decimal Location switch DL<PA Section: Block Diagram Page: 3 Rendition: Feb 5, 2024 D latch (4 bits) 1242 to 1-of-10 decoder FRS flag Position Counters 16 Nixie Displays 6543210987654321. PB register (5 bits) PB comparator FC0 flag Default bit path Canon 163 Calculator PM register (5 bits) LP flip-flop PB=0 PB=TD 100 4.7n 1.000 MHz 56K C641 10K 1.8K 100K C372 C372 10 10n 22K 470p 100p 10K 5.6K 47p 5.6K 1.8K 9 8101 8 5.6K 47p 1 4 5 8102 2 6 8A2 8B18 1K 1K 47p 13 47p 12 8101 11 10 12 13 8102 9 2D20 CPA 22K 3B20 47p 10 5 2103 6 CPA 47p 9 2103 2 47p 47p 1 2103 6B20 to memory 12 13 10 6201 9 6D2 22K 8 47p 4D2 SCT0 6D4 SCT1 6D3 3 13 2103 CPA 22K CPR 6D5 SCT2 4D5 4D4 5D5 5D2 5D3 5D4 7D5 7D2 7D3 22K 2 1 6103 3 47p 5 6103 6 47p 22K 6 9 10 6103 22K 22K 13 6101 11 47p 9 10 12 6102 13 7D6 8 1K 10 9 6101 22K 47p 8 4 5 6101 6D7 6 3D7 nSCT4 4D7 22K 5D7 22K 2 1 6101 13 6103 Canon 163 Calculator 6202 7D10 6D9 7D9 6D8 7D8 11 13 12 6D10 3 12 Section: Timing - Bit & State Page: 4 Rendition: Feb 5, 2024 SCT4 TD16 47p 8 3D6 4D6 12 TD16 47p 6D6 5D6 22K TD16 4 SCT3 7D4 5 4 2 6102 1 4 1 2 2104 5 22K nCPA 4D3 TD16 47p 11 47p 3D4 7B17 2D18 3D17 1K 8 TB0 TB3 8C3 6D20 10K 2B19 10K 12 22K 6 8 13 12 10 2104 9 CPA 5B20 8 4 47p 4B20 10K 1 2 4 6201 5 22K 22K 11 SCT34 SCT12 SCT01 6 2D19 4C12 nTB3 22K 22K 12 13 2302 22K 11 47p 4 22K 10 5 2105 6 47p 22K 4 9 2105 8 47p 10 5 2106 6 47p 47p 9 2106 8 2 1 4 2107 5 2 1 2105 47p 3 12 13 2105 47p 11 2 1 2106 47p 3 22K 22K 6 nTP67 2B8 6B8 12 13 2106 11 CPA 22K 9 10 12 2107 13 8 22K n1 1 n2 2 n4 4 5B8 1K 47p 22K 5 2302 6 TB3 47p 4 TB3 n8 8 2 1 2204 n16 16 3 TD0 2B5 4B5 n16 n4 2D3 4 2D2 n4 2C21 4 2D1 n1 n2 4 3 2303 5 1 n2 13 2 2303 1 2 16 1C21 1D1 D=12-15 8 1 1D2 DIGIT 1 2A20 6 13 12 2204 11 5 2204 10 9 2204 DIGIT 4 DIGIT 5 DIGIT 6 2.2K to display DIGIT 8 DIGIT 9 DIGIT 10 6D11 7D11 2.2K DIGIT 12 DIGIT 13 DIGIT 14 DIGIT 15 2C14 n16 3B5 nTD16 5D1 7A13 TB0 TD0 2 1 2302 13 3 12 2301 11 TP0 2B9 4B9 6B9 1D5 D=16 TD16 5D11 DIGIT 11 1C22 1D6 3D11 4D11 1 n1 2.2K DIGIT 16 2 n2 4 8 n8 Rendition: Feb 5, 2024 2C13 16 n4 Canon 163 Calculator 5B2 6B2 1C20 1D8 1D18 4B2 DIGIT 7 DW=3 2B6 8 2B2 7B2 DW=2 2D7 6 nTD0 6 DW=1 2D5 4 5B5 3 n16 DIGIT 3 DW=0 2C22 12 DIGIT 2 1 4 5 2205 2 2.2K D=8-11 8 2 2.2K D=4-7 n8 n1 1D3 n1 n2 n4 n8 D=1-3 n8 Section: Timing - Digit Page: 5 4A13 2C16 3C16 2C15 3A17 2C18 3C18 2C17 3A18 2C20 3C19 2C19 3C20 2A17 3C22 2A16 3C21 TDB1 nTDB1 TDB2 nTDB2 TDB4 nTDB4 TDB8 nTDB8 10 9 K101 K29 8 3A6 KSH 4A5 5A6 11 of 5.6K 1 2 1 2 3 3 4 4 5 6 5 6 7 7 8 8 1 3 5 7 9 2 3 5 8 9 4 6 7 8 9 5 6 7 8 9 0 2 4 6 8 1 5 4 2 D3 7A6 11 of 5.6K K17 K105 2B11 6 K28 K21 K16 K105 2B12 8 K12 KW3 10 13 12 9 D11 K15 2B13 6 K106 8 2 K103 K7 K104 6 5 K103 3 K20 5C12 9 13 9 K103 11 4C15 K(N+P) 3D15 K35 3B18 – 3C6 K101 K30 12 K102 2 K102 11 4A7 5D19 K37 CM1 4 K101 K24 6 3C14 3D20 nKCM1 4D20 5D20 7B19 nKMLT 7D20 K38 CM2 nKDIV 3D21 nKCM2 4D21 7D21 nKADD 5 4 3 nK(C+CI) nKCM1 nKCM2 nKSUB 3302 5 6 4 3111 6 11 3B15 6B15 nK(C+CI+CM) 4A11 13 nKMLT K(A+S) 12 nKDIV 4 4A6 6 1 4 3 2 of 5.6K KRM1 5D16 AM1 KRM2 WT 10 9 12 13 3 K104 K18 8 3C4 6 K32 7C11 K31 6B16 K1 3D5 K6 6B14 7B16 5.6K 4105 K(M+D) 7D13 4A10 2 4206 5D13 3201 5 5 6 nKSQRT 5 4206 RM1 8 1 13 3C2 RM2 9 4 K102 3B19 11 K19 KP 5C6 nK(C+CI) 7D19 6B19 13 K9 5 3 5B19 12 K23 3D19 4D19 nKM2SUB 6B18 0 10 K103 3D16 K5 K36 5A5 8 K27 5D21 nKN 0 9 10 K102 K101 5.6K C641 5.6K 7C16 DP 5.6K 6A5 + K22 1 nKM2ADD KW1 6 12 0 3A5 ÷ 4 K33 CI 5.6K KW2 1 5 4 2 1 D3 3B9 nKC 5B9 K8 2B14 5.6K nKRV 3B17 6B17 2 √ K14 3D9 M2+ M2– K106 3A22 K34 C 4A22 K11 4 1 2 5 D3 5.6K nKSH KW4 RV 12 10 13 9 D11 3D3 –> K KRM(1+2) K(N+P+RM) COUNT MEM SUM 4C4 5.6K KA nKA KK nKMN 7B18 5.6K K4 3B8 K2 7B10 KMS 5.6K K13 4.7n 3D13 Canon 163 Calculator Section: Keyboard Page: 6 Rendition: Feb 5, 2024 nK(C+CI+CM) nKST nTP67 3 5 2207 4 5.6K 2A8 6 TP67 K3 UP 5/4 DOWN K54 5 2 4 3207 1 K(A+S) nFMQ nFMLT nFN 12 KP 13 3113 FN 5 3113 nFN 10K nKST 10K 4 FKD 13 3101 100n 10K 22K 12 11 5 3101 47p 2.2µ 6 11 13 1 2 nFOVF nK(C+CI+CM) FST (to FRT) 22K 6 4 KSH 10K 6 22K 3112 12 4 5 3301 47p FU 6 3B10 nSCT4 9 10 3101 6B10 2 47p nFKD 5B10 3C5 1 3101 8 3 5C5 4C5 22K SCT4 2 47p nFST (to CPC, FV) 1 3301 3 22K 13 12 9 10 nKADD nKSUB nKRV K(N+P+RM) 9 10 3113 3207 1 8 22K 2 3107 5 nENDSP 4 3107 8 11 3A10 5A10 FN 10K 8 22K 3C9 4C9 3A12 9 47p nFN 4A12 FRT 5A12 SCT4 10 3108 11 FST 9 47p 12 3106 47p SCT4 nKMLT nKDIV nENDLP 13 nKSQRT 12 3108 47p 6 22K 13 3 10 3106 nENDLP 7A12 8 22K 3A11 5A11 nFRT 6A11 7A11 9 FU 10 3105 12 8 13 3105 22K 1 nKMLT 2 3102 47p FMQ 11 2 22K 1 3103 10K nKDIV nK(C+CI) 13 3 3 12 3104 47p SCT4 11 FMLT 3B1 SCT4 5 47p 4 3102 22K 4B1 KMS K(M+D) 9 10 3201 8 3202 6 n(KOP•FU) FU 9 10 3202 11 22K 8 2 3106 47p 6B6 4 3106 nENDP 6B3 3B7 22K 47p 13 12 3102 4 FDQ 22K 5 3103 11 nKMLT nK(C+CI) 3B4 2 3104 47p SCT4 10K 1 6 3 4B4 6B7 FDIV 7B4 nFMLT nFDIV 12 13 3301 3B13 11 9 10 3102 8 22K 4 3104 12 13 3103 10 11 9 3103 5 4 3105 6 nFMLT nFDIV nFRT 2 6 FG 1 3105 1 2 13 3202 3B12 12 5B12 6B12 F(M+D+R) 7B12 10 3 3D18 8 F(M+D) 7B13 nFDIV 22K KK nFME 6B13 5 47p nKC nFRT 4B13 5B13 SCT4 47p 4B7 5B7 7B3 nKDIV FME 7B6 6 22K nFMLT 4B6 5B6 5 47p 7B1 22K 3B3 3B6 3 SCT4 6B1 10 3104 1 8 5B1 9 47p nFMQ 6 5 4 3 nKM2ADD nKM2SUB 4D18 9 3301 nF(MQ+DQ) 3B11 8 4B11 5B11 7D18 nF(M+D+R) 6B11 7B11 Canon 163 Calculator Section: Control - Function Flags Page: 7 Rendition: Feb 5, 2024 nFDIV nFRT 1 2 3201 3B14 3 4B14 7B14 F(D+R) F(M+D+R) nFC0 1 CC16 2 6205 3 FJ2 4 5 CC16 6205 6 FJ1 FU F(M+D) 13 10 12 6205 6205 8 CC13 11 CCX3 9 nFC0 nFME CC15 9 nFJ2 13 10 12 6204 CC00-07 6204 8 CC17 11 1 2 6209 13 11 10 6206 9 n1 n2 n8 12 8 22K 47p 8 1 1 n2 n4 n1 n1 2 n8 FCC1 2 1 6114 3 SCT4 4 5 6210 6C16 12 47p 6 9 4 5 6114 6 3 5 6113 4 10 11 6106 9 2 6211 nKADD nKSUB nKSQRT K(M+D) F(M+D) 2 1 6202 13 12 9 10 6203 8 CC15 3 CCX1 9 10 6212 5 3 6209 4 4 2 1 6203 5 1 2 n4 8 5 6105 10 11 6113 9 8 6 22K 4 5 6211 47p 6 13 12 6211 47p 11 9 22K 10 6208 8 FJ2 5 6208 9 10 6209 11 47p 6 n1 n2 n4 8 FCC2 12 13 6114 11 2 9 6114 8 n2 n1 2 n4 8 4 1 6112 5 1 4 6111 2 9 13 10 6111 12 FCC4 2 1 6104 3 3 4 6106 5 6C14 6 4 6202 6 47p 3 10 6112 nENDLP 22K Canon 163 Calculator Section: Control - State Machine Page: 8 Rendition: Feb 5, 2024 CC02 CCX3 SCT4 12 1 6105 3 6A21 13 6208 11 8 6A18 4A18 6 4A21 CC02•SCT0 9 13 6105 11 CC12 SCT0 CC13 CC13 SCT0 2 1 6110 3 13 12 6108 11 10 6105 8 9 10 6110 8 9 10 6108 8 CC02•SCT4 6A22 6C7 7A22 4B10 7C22 6C22 4C22 6D1 4D1 CC12•SCT0 CC13•SCT0 nCC10 1 2 6208 2A21 7A21 12 4C14 7A18 3 6A16 5A16 CC10 CC17 SCT0 2 4 1 6107 3 5 6107 6 7D1 7A16 CC17•SCT0 8 4 6A17 6 4A17 CC12 5A17 7A17 6 6C19 5C19 6A19 3A19 1 4 2 6108 3 1 13 2 nCC14 6109 6C15 5C15 12 CC121415 CC14 4A19 5 6104 6 n4 n(KOP•FU) (to FME) 1 n2 4 12 13 6104 n1 2 4 FCC8 11 4 3 6109 5 7A19 6 12 10 9 6104 8 2 13 6113 1 6A20 11 n8 3A20 CC15 FME 7A20 12 9 10 6211 8 6C21 4C21 5 CC02•SCT4 4A20 8 SCT4 47p 2 5A21 nCCX3 9 13 6110 22K 5C17 5C14 4 3D10 CC02 SCT0 7C14 5 6110 n1 n2 4 22K 5 FU 10 8 6A10 4A15 8 SCT4 4 CC17 CC02 6A15 7A15 22K 47p CC14 6 6C17 6 3 CCX1 7A14 8 5 6112 2 1 6210 4A14 5A14 8 nENDP CC12 6A14 3 CC00 5A15 SCT4 CC17 5A13 22K 10 6210 3A13 nCC00 4 2 FU nKA nKMN 6A13 11 1 6 4C16 5C16 12 13 6112 10 9 6202 2 1 6106 13 nFJ2 4 6207 1 2 6207 CC16 11 9 6109 10 4 8 5 6108 FJ2 6 6C13 n2 n4 3C12 6C11 3C11 nENDSP CC10 1 4 2 6204 6204 C641 nENDLP 4C11 6 5C11 3 5C13 8 n1 3B2 CC17 5.6K 5 nKC 7C21 6C12 5.6K 5C21 1 2 4 6 3 7C13 6C20 10 9 6107 8 12 13 6107 6C18 5C20 5C18 7D16 11 1.8K CC10-17 CC151617 nENDSP nENDLP 5.6K 13 12 6210 11 C641 6C10 3C10 4C10 5C10 nENDP nENDLP 9 10 3107 12 8 22K 13 3107 11 47p 1 2 3108 3C8 4C8 3C7 4C7 3 FG SCT4 47p F(M+D) 5 4 3108 6 nFG 7C7 22K FMLT CC16 SCT0 nACA KP FN 1 4 2 5208 5 6 1 22K 2 5213 3 nSUM<0 13 5109 2 5212 3 nFJ2 nPB=0 KSH SCT4 4 5 5212 6 FU nKN 12 13 5212 5D12 11 4D12 6D12 FJ1 7D12 SCT4 47p 10 9 5109 nENDLP 1 F(M+D+R) 12 TD16 nK(C+CI) CC17 47p CC17 SCT2 nFC0 8 22K 10 9 5212 8 3 4 5211 5 6 CC15 SCT2 FRT 4 3 3112 5 6 11 9 3112 10 8 1 n@7208-6 11 KSH 3111 2 3 TD16 RSUM 9 10 3109 13 2 3110 1 12 4 3 3110 5 6 10 11 3110 9 8 8 SCT2 nF(M+D+R) CC10-17 CC10-17 CCX1 3 5 5209 4 9 10 5210 CC151617 FRT 6 nCC11 8 nCC14 nFME 13 1 2 CC10 5209 13 1 5211 2 nFJ2SET 12 13 22K 12 5210 11 2 12 1 5206 TD16 BD0 47p 3 5 1 2 5110 4 5D14 6 4D14 nFC0 47p 1 2 5210 3 nCC00 FJ2 22K 10 12 13 5110 9 7D14 8 5D15 4D15 6D15 7D15 CC14 SCT2 6D14 SCT4 CC151617 3D14 n@7103-11 12 13 3111 9 10 11 CC00 SCT4 PB16 3111 8 FJ2 TD16 SD 10 13 12 3206 9 KSH FN nK(C+CI+CM) 47p 11 nFRS nFJ2 22K 8 47p 3 Canon 163 Calculator 3 5 4 3109 6 22K WT LDNML Section: Control - Misc. Flags Page: 9 Rendition: Feb 5, 2024 2 3109 FOVF CPA 2 1 3113 1 12 13 3109 11 3A15 7C12 nFOVF nK(C+CI) nKCM1 nKCM2 2 K(N+P+RM) CC02•SCT0 nFN 1 4301 12 13 4301 5 3 4207 4 TD0 6 nTB3 4 3 SCT0 5 4301 4 5 2 4107 1 6 10 11 nTD0 FRT CC12•SCT0 TD0 9 4301 2 13 4207 1 8 5 4 4108 4D10 6 5D10 PA nG-PX FDIV nFG nPB1 3 PB1 12 FMLT 12 6 PB2 13 4108 FDIV FG nPA 11 10 nKRV 13 12 4206 11 CC02•SCT0 nF(M+D+R) CC16 SCT0 FDIV CC13•SCT0 nFG 2 1 4108 1 13 4208 2 10 11 4207 9 9 4108 PA 12 4208 4C6 7C19 4B18 5B18 6 enSAtoSB (to SB) CCX1 SCT1 CCX3 8 SCT0 SCT3 KRM(1+2) CC02 SCT1 13 12 4105 9 11 4208 10 SCT3 11 CC14 8 PA 2 n(enBtoA) 1 4105 13 4106 2 11 SCT0 2 4 3 1 13 4304 2 12 3 5 4304 4 6 5 CC13•SCT0 K(N+P) CC02•SCT0 FJ1 TP0 FMLT CC15 SCT2 TP0 F(D+R) CC15 SCT0 nFJ2 3 5 PB 4 4303 6 12 PA 13 4303 11 9 PB 10 4303 8 4106 eBD0toWB FJ1 9 4203 DPALIGN 8 FJ2 TP0 FJ2 FRS F(M+D) CC12 SCT0 TD0 4 3 5 4106 PB1 5A20 5 enSBtoSA CC17•SCT0 FMLT PM16 22K 4 4201 2 4201 6 S-PCA 1 6 3 22K FDIV 4C2 2 4 1 4205 5 2 4 1 4204 5 12 9 10 4204 13 6 6 6 8 13 11 12 4203 4D9 5D9 G-PY 11 2 1 4203 3 13 1 4104 2 12 9 10 4304 11 8 13 9 12 4205 10 8 6 CC17•SCT0 FRT 5 3 4104 4 5 4203 TP0 10 7A2 4 6 8 4C20 SCT0 nTD0 FF 4302 PM 1 4303 8 nG-PY1 1 2 4302 10 11 7205 9 nTD0+TB3 nG-PB 1 12 3 9 13 10 4107 12 11 n(KRV•CC02•SCT0) (to G-BD) CC12 CC12 12 4302 4C19 8 3 4 3 5 FRT to 4302-10 (unused) CC12•SCT0 7A4 13 47p 4 3 4202 5 nCC00 47p 6 10 9 4201 8 12 13 4201 DL=PA FP5 3 5 4102 4 5 1 2 4103 4 nFP5 11 DL=PA 22K CC14 FMLT 9 10 4104 11 8 DL=PA SCT4 6 3 FJ2 CC17•SCT0 FDIV 6 9 12 13 4103 10 1 13 4102 2 8 22K 47p 12 9 4101 8 4D16 6D16 TD16 47p 10 9 4105 10 8 12 13 4101 4D17 11 3D8 5D17 22K nFC0 6D17 nCC00 DL<PA Canon 163 Calculator Section: Point Counter Input Selectors & Flags Page: 10 Rendition: Feb 5, 2024 10 11 4102 9 22K 8 47p 4 5 4101 6 2 1 4101 3 4A8 7A8 4A9 3A9 FRS TD16 47p 22K 7A9 nFRS 5B15 4B15 S-PCA Carry 22K 47p 12 13 5101 11 PCA CPC 12 TD0 13 5204 11 9 10 5204 47p 8 10 9 5101 22K 22K Operand Half-Adder Carry Half-Adder 13 2 5202 4 5202 3 12 13 5203 G-PY 9 5202 5 11 6 11 FF 2 5B3 1 5101 47p CPA 8 nTD0 9 10 5203 SPA16? 8 12 3 11 470 6 CPA CPC C641 9 1.8K 10 5201 8 11 5B16 1.8K 2A10 3B16 4B16 4 47p 13 5206 5210 FF 4B3 TD16 10 12 5202 1 5 CC00 SCT3 nG-PX 4 nFST 8 5 5101 6 22K 5C2 1 5203 22K 47p 4 5 2108 4 22K 6 47p PA8 10 9 2108 47p 11 22K 2 1 2108 2C2 6 22K 8 4 5 2109 47p 47p 3 12 9 2109 47p 2 1 2109 11 22K 10 22K PA2 8 47p 3 5 2110 47p 12 13 2109 2C3 4C13 2C6 4A2 6 2 47p 1 2110 11 PA 3 nPA 22K 22K 22K PA1 4 CPC CPC 47p 13 2108 22K PA4 6 CPC CPC 12 2110 5203 3 PA16 CPC 13 nPASUM 5 2 4 5 2208 6 1 2 2208 3 10 9 2208 8 13 12 2208 11 9 2207 10 10 9 2302 8 12 13 10 2206 9 8 D3 2 4 2206 5 1 8 11 13 12 10 9 D11 2205 DL≠PA 10 8 2C12 nDL8 2C10 DL4 2C9 nDL4 2C7 DL2 2C8 nDL2 2C5 DL1 2C4 nDL1 K58 0 2 4 6 8 10 K62 K61 0 2 4 6 8 10 K57 K60 0 2 4 6 8 10 K56 K59 K55 K63 Canon 163 Calculator Section: PA Register & Comparator Page: 11 Rendition: Feb 5, 2024 Presumed wiring for units with odds-included DP switch. 8 DL≥PA 10 12 9 2110 8 2B7 4D13 2A9 4B17 DL=PA 6 nDL>PA 2C11 DL8 9 2301 K58 0 1 2 3 4 5 6 7 8 9 10 12 K62 2 1 13 K61 0 1 2 3 4 5 6 7 8 9 10 12 K63 2207 K57 K60 0 1 2 3 4 5 6 7 8 9 10 12 K56 K59 0 1 2 3 4 5 6 7 8 9 10 12 DL<PA K55 22K 47p 10 9 4209 PL16 8 CPC nG-PB 9 10 4106 47p 8 22K 47p 4 5 4209 PL8 6 CPC 13 12 4209 47p 10 9 4109 PL4 47p 1 2 4209 47p 4 5 4109 PL2 47p 13 12 4109 47p 10 9 4110 PL1 8 CPC 47p 11 22K 22K 6 CPC 3 22K 22K 8 CPC 11 22K 22K 1 2 4109 47p 3 22K 13 12 4110 11 22K PM16 (to 4102-4) 22K 47p 4 5 4110 PM16 22K 6 CPC 47p 10 9 4210 PM8 8 1 2 4110 47p 47p 3 13 12 4210 5 4210 PM4 22K 6 47p 4 5 4305 PM2 47p 1 2 4210 47p 10 9 4305 PM1 8 CPC 47p 3 22K 22K 6 CPC 11 22K 22K 4 CPC CPC 47p 22K 1 2 4305 47p 3 13 12 4305 22K 22K 11 4C17 4A16 3C17 3A16 PB16 (to FOVF) 22K 47p 10 9 3203 PB16 22K 8 47p 4 5 3204 PB8 22K 6 47p 47p 12 13 3203 47p 11 22K 9 3204 22K 8 47p CPC CPC CPC 10 PB4 2 1 3204 22K 4 5 3205 PB2 22K 6 47p 3 22K 12 13 3204 9 3205 4A4 3C3 4C3 3A3 4A3 PB2 8 PB1 CPC CPC 47p 10 3A4 PB1 47p 11 22K 2 1 3205 47p 3 12 13 3205 11 7A3 22K 1 2 4 3206 5 nPB1 3A8 5A8 3D1 7B15 6 nPB=0 3 5 nTDB1 4 3304 6 2 TDB1 1 3304 3 12 nTDB2 13 3304 11 9 TDB2 nTDB4 10 3304 10 8 nTD16 9 3303 8 13 2 1 3302 9 11 3302 10 12 22K 13 TDB4 12 3303 11 1 nTDB8 2 3303 Canon 163 Calculator Section: PB Register & Decoding Page: 12 Rendition: Feb 5, 2024 5 3303 PB=TD 10K 1 2 3203 3 3D2 TB3 3 4 TDB8 47p 8 47p 2B16 5 4 3203 6 22K 6 nTB3 1C17 LP 2 22K 1 5102 3 47p 5 4 5102 6 SM1 SB SM1 nSCT4 47p 13 12 5102 nACA SUBB 1 2 7109 7A7 11 nSB 10 9 5102 8 nSM1 nSM1 22K SA SM1 nKCM1 5C7 nSUM<0 (to FJ1) 3 nSA 2 9 10 5213 22K 1 5104 8 3 47p nSM1 5 4 5104 6 SM2 SB SM2 SCT4 47p 13 12 5104 11 nSB 10 9 5104 8 nSM2 nSM2 22K nKCM2 SB 1 SCT0 10 5206 F(M+D) CC12 SCT2 1 4 2 5205 5 KRM1 CC02•SCT0 4 3 5201 5 KRM2 CC02•SCT0 13 1 5201 2 nSB=SM1 nSB=SM2 nFRT CC12 SCT3 nFJ2 1 2 5 5207 4 FME CC02•SCT0 nFJ2 nF(M+D+R) CC16 SCT3 nFJ2 13 12 9 5207 10 Canon 163 Calculator Section: Sign Flags Page: 13 Rendition: Feb 5, 2024 nKM2SUB 2 5204 FU 13 5105 6 6 6 SA 11 10 9 5105 8 nSA 22K 4 5 5106 enSAtoSB 12 5 6 2 4 5206 22K 1 5107 6 3 47p 6 47p 13 8 K(N+P) 8 5 4 5107 6 SB TD16 CC02•SCT0 5 5204 4 5105 nSB SA 12 5107 11 9 10 5106 8 10 9 5107 8 nSB 22K 12 nSA 13 5213 11 nK(C+CI) 2 5.6K 22K 1 5108 C641 3 47p 8 5 4 5108 6 5C9 7C10 5C8 7C9 SK TD16 47p 13 12 5108 4 3 47p 12 11 1 5 TD16 12 13 10 5205 9 nSA=SM1 nKSUB 8 11 12 9 10 5208 13 3 47p 3 SK nFRT CC12 SCT3 nFJ2 2 5105 enSBtoSA 9 22K 6 nENDP 11 22K 10 9 5108 8 nSK 2 1 5103 3 nSB=SM1 12 13 5103 11 2 1 5106 3 nSA=SM1 12 13 5106 11 4 5 5103 6 nSB=SM2 10 9 5103 8 nF(MQ+DQ) K(N+P+RM) nFN nFG nKRV CC02•SCT0 9 10 4202 11 8 13 1 2 4202 11 10 7301 9 FDIV CC14 SCT2 12 13 10 7201 9 12 10 9 4206 8 n(enBtoA) (to enSBtoSA) 4C18 FJ2 FRS 7C17 CC13 nFMLT nFRT nFG 13 2 1 CC12•SCT0 7209 12 CC10 SCT0 nFJ2 CC12•SCT0 FJ2 CCX1 SCT34 13 12 7210 13 2 7105 1 nKCM1 11 n@7210-11 (to G-BD) 12 9 10 7103 12 13 7103 13 2 7301 1 nKCM2 1 2 7101 13 12 7101 SCT12 3 SCT3 11 SCT4 nF(M+D+R) 11 @7103-8 (to WA) 7D17 3A7 n@7103-11 (to FOVF) nFRS CC15 SCT01 12 CC15 SCT12 nFJ2 CC17•SCT0 KA CC10 SCT3 nF(MQ+DQ) FMLT CC17 SCT1 4 9 10 7212 2 1 4 7112 5 6 8 6 nF(M+D+R) 5 7101 12 13 10 7112 9 2 3 nFJ2 nSK FMLT CC16 SCT1 8 11 AD0 6 9 7101 8 5 7210 6 F(D+R) CC17 SCT1 1 2 7111 9 10 7210 8 5 3 7209 4 6 10 12 9 7211 13 10 11 7209 9 1 2 7208 13 3 5 7207 4 10 11 7207 9 4 3 7208 5 13 12 7111 Section: Arithmetic Input Selectors Page: 14 Rendition: Feb 5, 2024 6 7A5 8C4 7C5 8A4 nG-X FRT nFJ2 nFMLT 6 9 7111 8 8 7C4 6C4 7C3 6C3 12 13 7109 6 SUBA (to arithmetic) SUBB (to arithmetic) (to signs) 12 10 11 nBD0 9 7109 8 5 BD0 8 7C18 6 2 13 7207 1 12 9 10 7208 11 8 2 5 1 7201 4 5 7111 10 11 nAD0 12 10 9 13 3C13 7110 6 FMLT CC16 SCT0 TD16 n@7208-6 (to FOVF) FMLT CC17•SCT0 TD16 TB0 8 CC10 SCT1 nFJ2 TD16 K54 nKMN Canon 163 Calculator 1 D3 D3 4 7110 5 D3 2 4 3 SD 8 3 F(M+D) KA CC16 SCT3 F(D+R) CC16 SCT1 nFOVF 1 7212 8 4 8 nFJ2 SK CC02•SCT4 8 10 FJ1 FJ2 5 7212 n@7301-8 (to WA) 4 CC14 SCT12 FJ2 nFRS FME 9 10 7102 8 12 13 7102 11 5 1 2 7206 4 9 13 10 7206 12 5 2 4 7202 1 D3 12 D11 10 D11 nF(MQ+DQ) 7202 9 FJ2 D11 PB=TD 13 TB0 3 CC17 4 SCT2 7301 5 6 6 8 2 1 6 CC10 SCT4 1 2 7102 4 7109 3 8 6 7108 3 G-Y 4 @7103-8 @7301-8 5 7103 FRS 6 AD 2 1 7103 eAD0CtoWA 3 5 4 7102 F(M+D+R) CC10 SCT2 FRT CC151617 SCT2 KSH CCX1 SCT0 CCX3 SCT0 FJ2 FRS FRT CC12 KRM1 CC02 SCT3 KRM2 CC02•SCT4 10 9 7203 11 2 1 7203 13 3 5 7203 4 10 9 12 7204 13 FRT CC13 SCT4 nPB1 K(N+P) CC02•SCT0 FN Canon 163 Calculator Section: Memory Input Selectors Page: 15 Rendition: Feb 5, 2024 AD0 8 5 4 7104 3 6 2 13 7104 1 12 7C20 8D1 7B5 8B1 nWA 10 13 12 7106 12 BD eADtoWB 11 nTD0 AD nTD0 BD0 2 6 1 7106 9 7106 8 5 4 7105 3 6 9 10 7105 11 8 7B20 4D8 3 nWB eBD0toWB (to G-PY) 8 2 1 7210 3 4 5 7205 3 6 2 1 7205 13 12 4 5 1 2 4 5 2 7204 1 5 1 4 7211 2 nK(C+CI) 7107 5 6 4 7106 6 BD0 eAD0toBD 6 5 4 7108 AD0 eSDtoBD 6 13 D11 12 9 7107 D11 10 8 7B9 8D6 5A3 2B15 nG-BD 12 13 7108 11 9 SD 10 7108 8 9 10 5214 8 6 12 13 7212 11 nCC00 nCCX3 CC02•SCT0 6 8 n@7210-11 n(KRV•CC02•SCT0) CCX3 SCT0 FJ2 nFRS nTD0 AD0 eAD0toWA 9 10 7104 11 5 4 5213 10 11 9 5211 8 BD0 6 CC121415 AD0 CCX1 nTD16 AD0 12 13 5214 11 11 9 5209 10 8 nG-SD SUBA TP0 SUBB Carry Flag 22K 47p 9 10 6207 nTP67 1 13 2 nCC10 nFMLT 13 CC16 12 6207 nFJ2 6206 2 6212 3 4 5 6212 6 4 5 8104 8C19 6 CPA 8 3 4 6206 5 SCT1 1 6C9 8C18 47p 10 nCAIN 9 8104 8 6 12 1 2 8104 8C20 3 6C8 13 6212 11 ACA nCA 22K AINC 8C5 Operand Half-Adder 12 Carry Half-Adder 9 nG-X 13 10 8305 2 11 1 8305 12 8304 1 8 2 8304 3 12 13 8305 G-Y 3 11 nS4 SW S4 nS4 S2 S1 S4 nS2 nS1 10 9 8203 ACA nACA SW 9 10 8302 2 1 8105 4 5 8105 12 8105 6 47p 11 12 8104 nSW 8C17 7C15 nACA (to FJ1) (to SB) nACA SW 5 8106 6 2 13 8205 1 12 9 10 8205 11 8 13 12 8106 11 OK 8C22 10 8 nOK 8C21 S2 nS2 nOK OK 9 8204 22K 8 47p 4 8302 12 13 8204 11 22K 4 5 8203 4 5 8204 6 47p 10 9 8105 6 47p 1 CPA 6 S1 22K 8 22K 2 8302 1 2 8204 3 2 1 8203 10 8303 22K 8 CPA 3 Canon 163 Calculator Rendition: Feb 5, 2024 47p 5 8C6 7C6 4 8303 6 1 2 8303 3 CPA 47p 13 12 8302 3 nS1 9 11 13 12 8303 47p 11 22K 22K 8C7 Section: Arithmetic Page: 16 5A19 11 RSUM (toFOVF) 4 nOK OK 5 13 13 8 3A21 3 10 CPA 3 8304 8A3 6 8 S4 nS4 47p 6 9 8106 nOK OK 22K 10 ACA 2 8106 TB3 11 6 1 12 13 8203 S4 8 3 4 8205 5 9 4 8305 nSW 11 4 5 8304 5 nS2 6C6 8A6 6C5 8C8 AD MAGNETOSTRICTIVE ACOUSTIC DELAY LINE 470 WA 1 100 nWA 2 WB 3 R 4 6 5 39 33K 1n 3 C641 C641 1K 1.8K M C641 470 4 1.8K 1K 10n 1.8K 10n 82 47p 5.6K 33µ 16V 1K 5 CPR 1.8K 4 8101 V–5 4 6 10n 11 100 5.6K 5 8103 22K 3.3K 12 8301 10K 1n 1n 1K 13 nWB C641 33µ 16V 1.8K 5.6K C641 2 8301 3.3K 33K 1.8K 33K 1 100 33µ 16V 4.7n 5.6K 6 5.6K 47p 10 9 8103 12 13 8103 5.6K 8 6 nQ 8D5 9 5C22 AD0 7B8 8201 S Q nS 6 10 8D4 7D7 8D3 2B18 nAD0 5.6K 2 1 8101 3 5 11 12 100p R 2 nCPA 3 4 1K 10 9 8301 2 nM C641 5 8301 nR R CPA 3 4 5.6K 11 5 11 12 M S 8 nR nQ 9 8202 8 3A2 Q nS 6 10 7C2 BD0 5A2 8D2 2B17 nBD0 7B7 22K 1.8K 22p 10K 1.8K 47p 10K 8 CPA C641 nG-BD 47p 22K 4 5 8107 6 CPA 2 8B3 C641 9 8107 47p nCPW 22K 10 1 8103 12 47p 13 8107 3 33K 9 8206 8 CPA 47p 11 22K 47p 22K 10 1 2 8107 47p 5 4 8206 6 1 2 8206 3 8C2 7C8 2B20 3A14 BD CPA 47p 3 12 13 8206 47p 11 22K 22K 22K SD3 nSD3 SD2 nSD2 SD1 nSD1 47p nCPA 1K 22K 22K 4 5 2101 47p 6 CPA 5 2301 2 47p 1 2101 8B2 2A22 CPW Canon 163 Calculator Section: Memory Page: 17 Rendition: Feb 5, 2024 8 6 9 11 2303 10 3 KW1 8 2 2301 12 13 2101 2 1 2203 KW2 3 3 2D12 3D12 5 2102 6 11 LDNML (to FOVF) 2 1 2102 47p 3 22K 5 4 2203 KW3 6 47p 10 9 2102 8 CPA 47p 22K 1 47p 22K 4 CPA 47p 22K CC02•SCT0 TP0 9 2101 CPA 4 nG-SD 47p 22K 10 12 13 2102 11 22K 9 10 2203 KW4 8 13 12 2203 11 7A10 SD V+100 220K 16 22K nFJ2SET 47p n2 10K 2D17 1 5109 10K 5A4 3 SCT4 1D17 10 of C857 0+1 n4 2 47p nFST 4 5 5109 6 K53 LV 10 8 6 4 2 0 15 220K 14 13 K54 K51 K52 12 1C4 1C2 1C3 220K 11 10 9 220K 8 7 C857 6 220K 5 4 3 C857 33K 2 1 C857 33K 33K 22K 22K nBD0 47p V+100 4 5 2201 6 W 2 10K 56K 2D16 TB3 47p BD0 1D16 M1 2+3 nW 2 1 2201 3 SCT3 nW V+200 AD0 5 4 5214 22K nSD3 47p 4 10 9 2201 8 4 n4 SD3 12 13 2201 2D13 10K 2D10 n2 2D9 47p 1D11 Hitachi 0 2 4 6 8 . CD71 1 3 5 7 9 6+7 W 22K 4 5 2202 6 SD2 3 2 n2 22K 47p 47p 1 5111 10K 5C3 3 1C8 LM1 V+100 4 5 5111 6 56K M2 22K 1 2 5214 22K 3 47p C857 12 13 5111 10K 5C4 11 1C6 LM2 CPA nSCT4 V+100 10 9 5111 8 56K 2D8 1D10 NEG 10K 8+9 SB C857 5D8 1D20 LSB V+100 13 12 2202 10K 11 9 10 2202 10K 8 C641 2D15 1D15 EVENS nTD0 TB3 nSD1 10K 4 22K SD1 2 22K 2 1 2202 47p 47p 2 TB3 47p SCT2 DIGITS 15 to 1 (LSD) SCT4 10K 47p from Timing 1D12 n4 22K nSD2 DIGIT 16 (MSD) C857 5 W 11 1D13 4 nW TB3 47p 10K 6 C857 CPA 2.7K 22K 22K 5.6K 56K 680p C641 2D14 1D14 ODDS 22K V+100 Canon 163 Calculator Rendition: Feb 5, 2024 OVERFLOW 10K C857 C857 10K 5.6K LP 680p 30µ 12V Section: Display Page: 18 56K FOVF 3C15 1D19 10K V+200 red 0.5 AMP. 115VAC 17W POWER 10µ 160V 5GS-8C m4.3V 10µ 160V 95 VAC blk yel 1n 1µ 350V B89A V+100 47K 2W 1n whi 1K 470 5.6K blu 2 AMP. grn 4.7µ 50V 220µ 16V 4.7n B337 K25 +5V 1D21 7 VAC blu 2 of 2200µ 10V 2B21 2D21 3B21 4B21 4D22 5B21 5D22 6B21 6D22 7B21 7D22 8B21 8 of 4.7n 5 of 4.7n 5 of 4.7n 5 of 4.7n 9 of 4.7n 5 of 4.7n 5 of 4.7n D77 2 of 33µ 12.5V 5.6K D77 30µ 10V 1.8K 1K 1.8K 220µ 16V 5GS-8C 470 m4.6V 33µ 16V 220µ 16V 2A1 2C1 2B22 2D22 1C1 1D22 K26 4A1 4C1 4B22 3A1 3B22 5A1 5C1 5B22 6A1 6C1 6B22 7A1 7C1 7B22 8A1 8C1 8B22 8D22 –5V 8B19 V–5 14 14 14 14 14 14 14 14 SN3920 SN3925 SN3931 SN4552 SN4553 SN4554 SN4555 SN4556 dual 4-input NAND quad 2-input NAND triple 3-input NAND dual 4-input NAND dual 4-input NAND quad 2-input NAND Clocked SR Flip-Flop triple 3-input NAND 7 7 7 7 7 7 7 7 Unused Gates FRT Canon 163 Calculator Section: Power Supply Page: 19 @4302-11 9 10 4302 5 3201 Rendition: Feb 5, 2024 8 4 6 SN3900 / 4500 Series DTL IC Pinouts 14 SN3920 SN4552 SN4553 13 12 11 10 9 Board Contents SN3900 / 4500 Series DTL Gate Construction Board Contents SN3920 SN3925 SN3931 SN4554 8 Vcc +5V 1.75K 2K 0V GND 1 2 3 4 5 6 1 • display & drivers • numeral decoder 2 • TB & TD counters • display latch • SD register • PA register & comparator 3 • FST, FN, FU, FG, FMLT, FDIV, FRT, FME function flags • FOVF flag & overflow detection • portion of PB register & PB decoding 4 • FC0 & FRS flags • PA & PB input gates • portion of PB register • portion of arithmetic input gating 5 • FF flag & CPC gating • SA, SB, SK, SM1, SM2 sign flags • FJ1, FJ2, FV, FM1, FM2 flags • SD input gate • PA adder & PCA flag 6 • SCT counter • CC state machine (latches, decoding & sequencing) 7 • input gates for arithmetic, memory & BD 8 • clock • memory interface • adder with CA flag & AD sum correction • BD register 6K Output 7 Inputs 3K 14 SN3925 SN4554 13 12 11 10 9 8 Expansion Input Vcc +5V SN4553 0V GND 1 14 2 13 3 12 4 5 11 10 6 9 1K 2.75K 7 8 Vcc +5V 850 1.85K 150 Inputs Output 2K Expansion Input 630 SN3931 SN4556 Odd/Incorrect 0V GND 1 * 14 2 3 4 5 13 12 11 * Vcc +5V 10 6 * 9 7 8 R RD Q SN4555 T S SD Q 1 2 * 3 4 * 5 pin label 5B1 FD16 5C20 01 5B18 12 5A17 SCT2 7C22 SK 7D17 OC13 4110-6 nPC1 0V GND 6 7 * * 800/900-Series DTL Equivalents SN3920 SN3925 SN3931 SN4552 SN4553 SN4554 SN4555 SN4556 930 Fair69.3-116 946 Fair69.3-116 962 Fair69.3-116 Labels actually FMLT CC10-17 CC12 CC12•SCT0 PM16 932 Fair69.3-118 946 Fair69.3-116 *see comment Board Orientation The pinout for SN4555 has been inferred through reverse engineering and by matching the pins utilised in the 163 to the pinout of the following ICs: 831/931, 845/945 & 848/948 DTL clocked flip-flop. The pins marked with ʻ*ʼ are those utilised in the 163. Boards 1 to 8 b is board number X61-670b- 0 3 Component Side Refs: • Motorola Semiconductor Data Book, 4th Edition, 1969, pg. IC-49 • Fairchild 1969, pg 3-5, 3-116::119). Canon 163 Calculator Section: IC Pinouts & Board Orientation Page: 20 Rendition: Feb 5, 2024 bB22 bB1 bA22 bD22 bD1 bC22 bA1 bC1 IC 3920 3925 3931 4552 4553 4554 4556 IC K101 • 4101 K102 • 4102 K103 • 3920 3925 3931 4552 4553 4554 4556 • • 4103 IC 3920 3925 3931 4552 4553 4554 6101 • 6102 • IC 3920 3925 3931 4552 4553 4554 4555 4556 8101 • 8102 • 6103 • 8103 • K104 • 4104 6104 • 8104 • K105 • 4105 • 6105 • 8105 • K106 • 4106 • 6106 8106 • 8107 • 3 2 0 0 0 1 0 • • 4107 • 6107 2101 • 4108 • 6108 2102 • 4109 • 6109 4110 • 6110 4201 • 2103 • 2104 • 2105 2106 2107 • 4202 • 4203 • 6111 • • 6114 • 6201 4205 2109 • 4206 2110 • 4207 • • • • 6203 • • • 4208 6204 • • 4209 • 6205 • 4210 • 6206 4301 • 6207 4302 • 6208 4303 • 6209 • 2205 2206 • • 2207 • 4304 2208 • 2301 • 2302 4305 • 1 8 2 1 2 0 1 3 • • 8305 • 0 11 1 0 1 3 2 • • • • • 6212 • 1 7 5 1 2 10 Board 3920 3925 3931 4552 4553 4554 4555 4556 K 3 2 0 0 0 1 0 2 1 8 2 1 2 7 0 3 1 13 1 1 0 5 3 4 2 14 3 2 0 1 3 5 2 18 3 1 1 0 0 7 5 1 2 10 0 5101 • 5102 • 7101 • 6 1 5103 • 7102 • 7 8 9 8 0 0 • 5104 • 7103 • 8 0 11 1 0 1 3 2 3102 • 5105 • 7104 • Total 18 82 23 6 6 27 2 3103 • 5106 • 7105 • ICs 170 5107 • 7106 5108 • 7107 5109 • 7108 • K 1 18 7109 • 1 36 16 • 3105 • 3106 • 3107 • 5110 3108 • 3109 • 3112 • 3113 • 3201 • • 3204 • 3206 3301 • • 3303 • 3304 • 1 13 • • 7201 • 5 2 • 7202 • 6 2 5204 • 5207 7203 • 7204 • • 7206 • • • • 7211 5214 • 7212 1 0 0 0 5 3 Canon 163 Calculator Section: IC Types & Tallies Page: 21 Rendition: Feb 5, 2024 7 Total 56 122 • 5213 1 4 • 7210 3 11 PS 7208 • 18 8 • 7207 5212 • • • • 7301 • 9 2 7 • 7209 5 13 • • 7205 8 1 17 5203 2 1 28 3 4 5211 • 7111 2 • 5210 • • 7112 5209 • Board T r a n s i s t o r s Diodes • 5208 3205 3302 • 5206 • 7110 • • 5202 5205 3202 3203 • 5201 • 3111 • 5111 • 3110 3207 0 2 • • 8304 6211 3 • 8301 3101 3104 7 14 • • 6210 • 2 • 2303 • • 8205 8303 • • 2204 • 8302 • 2202 • • 8203 8206 • 2201 2203 • 8204 • 6202 • 8201 8202 • 6113 • • • 6112 4204 2108 • 8 0 0 0 13 3 6 N1 C 1 GND 2 A3 3 A2 4 A1 5 6 LM2 7 [] 8 LM1 9 10 11 12 13 14 15 16 17 LP 18 - [->] 19 - [->] 20 DW=0 21 D=8-11 22 DW=1 D 1 D=12-15 2 D=4-7 3 D=1-3 4 5 DW=2 6 D=16 7 8 DW=3 9 10 8+9 11 6+7 12 5 13 4 14 ODD 15 EVEN 16 2+3 17 0+1 18 [nTD0] 19 LOF 20 LSB 21 V+5 22 GND N2 A C GND 1 1 GND - 2 2 nPASUM - 3 3 PA - 4 4 nDL1 - 5 5 DL1 [->] 6 6 n P A - 7 7 DL2 T P 6 7 8 8 nDL2 D L < P A 9 9 nDL4 CPC 10 10 DL4 [ ] 11 11 DL8 - 12 12 nDL8 - 13 13 T D 1 6 - 14 14 n T D 1 6 - 15 15 n T D B 1 n T D B 8 16 16 T D B 1 T D B 8 17 17 n T D B 2 [<-] - 18 18 T D B 2 [<-] - 19 19 n T D B 4 D W = 0 20 20 T D B 4 C02•S0 21 21 D = 8 - 1 1 nCPW 22 22 D W = 1 N2 B D - 1 1 D=12-15 nTD0 2 2 D=4-7 - 3 3 D=1-3 - 4 4 TD0 5 5 DW=2 D=16 6 6 DL=PA 7 7 DW=3 nTP67 8 8 8 + 9 TP0 9 9 6+7 - 10 10 5 KW4 11 11 KW3 12 12 LDN M L KW2 13 13 4 KW1 14 14 O D D nG-SD 15 15 E V E N L P 16 16 2 + 3 nBD0 17 17 0 + 1 BD0 18 18 T B 3 T B 0 19 19 n T B 3 S D 20 20 CPA V+5 21 21 V+5 GND 22 22 GND N3 N4 N5 A C A C A C GND 1 1 [GND] GND 1 1 GND GND 1 1 GND BD0 2 2 nK(A+S) nPA 2 2 nG-PY1 BD0 2 2 n P A S U M nPB1 3 3 PB1 nPB1 3 3 PB1 nG-SD 3 3 L M 1 P B 2 4 4 K(N+P+RM) PB2 4 4 K(N+P+RM) L V 4 4 LM2 nKSQRT 5 5 n F S T [KSH] 5 5 [nFST] K(N+P) 5 5 nFST KSH 6 6 KP KRM1 6 6 nKRVC2S0 KSH 6 6 KP n@7103-11 7 7 n F G nKRM1 7 7 nFG - 7 7 nSUM<0 nPB=0 8 8 FG F R S 8 8 FG nPB=0 8 8 n S K nFRS 9 9 n F N n F R S 9 9 nFN - 9 9 SK F N 10 10 nENDP K R M 2 10 10 [nENDP] FN 10 10 nENDP n F R T 11 11 nENDLP nKRM2 11 11 [nENDLP] nFRT 11 11 nENDLP F R T 12 12 nENDSP FRT 12 12 nTB3 FRT 12 12 nKN CC00 13 13 n@7208-6 TD0 13 13 PA CC00 13 13 CC17 SD 14 14 WT CCX1 14 14 CCX3 CCX1 14 14 [CCX3] n F O V F 15 15 L O F CC02 15 15 K(N+P) [CC02] 15 15 CC121415 PM1 16 16 TDB1 P M 1 16 16 nCC00 CC10 16 16 nCC00 nTDB1 17 17 nPM1 CC12 17 17 n P M 1 CC12 17 17 nCCX3 nTDB2 18 18 TDB2 [CC13] 18 18 n(enBtoA) - 18 18 CC151617 CC14 19 19 TDB4 CC14 19 19 n T D 0 + T B 3 nACA 19 19 nCC14 CC15 20 20 nTDB4 CC15 20 20 e n S B t o S A enSBtoSA 20 20 CC10-17 RSUM 21 21 nTDB8 C02•S0 21 21 CC16 C02•S0 21 21 CC16 nKRV 22 22 TDB8 nKRV 22 22 C13•S0 - 22 22 AD0 N3 N4 N5 B D B D B D FMLT 1 1 PB=TD FMLT 1 1 C17•S0 FMLT 1 1 nTD16 CC17 2 2 L P nTD0 2 2 SCT0 nTD0 2 2 SCT0 n F M L T 3 3 [nKSH] FF 3 3 SCT1 F F 3 3 [SCT1] F D I V 4 4 SCT2 FDIV 4 4 SCT2 - 4 4 SCT2 nTD16 5 5 KK TD0 5 5 SCT3 TD0 5 5 SCT3 F M E 6 6 SCT4 [FME] 6 6 SCT4 FME 6 6 SCT4 n F M E 7 7 nSCT4 [nFME] 7 7 [nSCT4] nFME 7 7 nSCT4 KMS 8 8 nFC0 - 8 8 eBD0toWB [nTP67] 8 8 L S B nKM2SUB 9 9 nKM2ADD TP0 9 9 G-PY nKM2SUB 9 9 G-PY F U 10 10 n(KOP•FU) C12•S0 10 10 nG-PX FU 10 10 nG-PX nF(M+D+R) 11 11 TD16 nF(M+D+R) 11 11 TD16 nF(M+D+R) 11 11 TD16 F(M+D+R) 12 12 LDNML - 12 12 FJ1 F(M+D+R) 12 12 F J 1 F(M+D) 13 13 nKST F(M+D) 13 13 DL=PA F(M+D) 13 13 KRM1 F(D+R) 14 14 FJ2 F(D+R) 14 14 FJ2 - 14 14 F J 2 K(M+D) 15 15 nKDIV S-PCA 15 15 nFJ2 S - P C A 15 15 n F J 2 CPC 16 16 nKMLT CPC 16 16 F C 0 C P C 16 16 KRM2 nKC 17 17 TB3 DL<PA 17 17 n F C 0 [ -> ] 17 17 nFC0 nKADD 18 18 nF(MQ+DQ) e n S A t o S B 18 18 nF(MQ+DQ) enSAtoSB 18 18 nKSUB 19 19 nK(C+CI) - 19 19 nK(C+CI) nKSUB 19 19 nK(C+CI) CPA 20 20 nKCM1 [CPA] 20 20 nKCM1 CPA 20 20 nKCM1 V+5 21 21 nKCM2 V+5 21 21 nKCM2 V+5 21 21 nKCM2 GND 22 22 [V+5] GND 22 22 V+5 GND 22 22 V+5 Canon 163 Calculator Section: Connectors Page: 22 Rendition: Feb 5, 2024 • As viewed from bottom of backplane. • Bold-faced expressions are signal sources. • {signal} : connected on the PCB but not connected on the backplane. • [signal] : connected on the backplane but not connected on the PCB. N6 N7 A C A C GND 1 1 GND GND 1 1 GND - 2 2 nG-PY1 2 2 BD0 - 3 3 SUBB nPB1 3 3 S U B B - 4 4 SUBA nTD0+TB3 4 4 S U B A nKSQRT 5 5 AINC nG-X 5 5 G-Y - 6 6 ACA KSH 6 6 AD - 7 7 C12•S0 n S U M < 0 7 7 nFG - 8 8 nCA FRS 8 8 BD - 9 9 nCAIN nFRS 9 9 nSK n(KOP•FU) 10 10 n E N D P SD 10 10 SK [nFRT] 11 11 n E N D L P nFRT 11 11 KA - 12 12 n E N D S P FRT 12 12 nFOVF C C 0 0 13 13 C C 1 7 [nTD16] 13 13 CC17 C C X 1 14 14 C C X 3 CCX1 14 14 CCX3 C C 0 2 15 15 C C 1 2 1 4 1 5 CC02 15 15 nACA C C 1 0 16 16 n C C 0 0 CC10 16 16 K(N+P) C C 1 2 17 17 n C C X 3 CC12 17 17 n(enBtoA) C C 1 3 18 18 C C 1 5 1 6 1 7 CC13 18 18 n @ 7 2 0 8 - 6 C C 1 4 19 19 n C C 1 4 CC14 19 19 nKRVC2S0 C C 1 5 20 20 C C 1 0 - 1 7 CC15 20 20 n W A C 0 2 • S 0 21 21 C C 1 6 C02•S0 21 21 CC16 C 0 2 • S 4 22 22 C 1 3 • S 0 C02•S4 22 22 C12•S0 N6 N7 B D B D [FMLT] 1 1 C 1 7 • S 0 FMLT 1 1 C17•S0 [nTD0] 2 2 S C T 0 nTD0 2 2 SCT0 nFMLT 3 3 S C T 1 nFMLT 3 3 SCT1 - 4 4 SCT2 FDIV 4 4 SCT2 - 5 5 SCT3 n W B 5 5 SCT3 FME 6 6 S C T 4 FME 6 6 SCT4 nFME 7 7 n S C T 4 nBD0 7 7 nAD0 nTP67 8 8 S C T 0 1 AD0 8 8 SCT01 TP0 9 9 S C T 1 2 nG-BD 9 9 SCT12 FU 10 10 S C T 3 4 K54 10 10 SCT34 [nF(