Schematic · 2024
Canon 163 Calculator: Schematic Appendix
Nine pages of supporting drawings for the Canon 163 schematic: flip-flop forms, timing diagrams, the register and delay-line organisation, state graphs and a worked square root.
Schematic · 2024
Nine pages of supporting drawings for the Canon 163 schematic: flip-flop forms, timing diagrams, the register and delay-line organisation, state graphs and a worked square root.
Flip-Flops & Variations 22K 22K nSE 47p Q Basic Flip-Flop nQ • Q goes 1 if nSE=0 at –edge of T • Q goes 0 if nRE=0 at –edge of T • No change if nSE=1 & nRE=1 at trigger • Undefined if nSE=0 & nRE=0 at trigger T 47p nRE D Q 47p D Flip-Flop T • Q follows D at –edge of T 47p 22K nQ 22K 22K nSE RT 47p nRE 22K D Q 47p ST Separated Triggers LD • Q goes 1 if nSE=0 at –edge of ST • Q goes 0 if nRE=0 at –edge of RT T Q 47p nQ 47p 22K nD nQ Gated Load • Q follows D if LD=1 at –edge of T • No change at trigger if LD=0 22K 22K 22K Q 47p T Toggle Flip-flop TE • Q inverts on –edge of T T Gated Toggle Q 47p Variation on Gated-Load: Q follows nQ if TE=1 at –edge of T 47p 47p 11 nQ nQ 22K 22K And with Synchronous Reset. • Q toggles if TE=1 at –edge of T • Q goes 0 if nRE=0 at –edge of T nRE AND Gate AND Gate with ʻwiredʼ input Wired-AND Gate Discrete Gate Construction A few gates are constructed from discrete diodes and resistors. A wire–AND construction is indicated by the input line traversing the width of the gate. Canon 163 Calculator Section: Appendix - Flip-Flops & Discrete Gates Page: A1 Rendition: Feb 1, 2024 Bit & Digit Timing 0µS 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 (500KHz) CPR CPA CPW 0 TB0 1 2 3 TB3 Digit & Number Timing 0µS 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 256 272 16 32 CPA 0 1 2 3 TB0 TB3 TD0 16 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 0 1 TD16 TP0 TP67 CPC (active during FF) State Cycle Timing 0µS 272 544 816 1088 1360 TB0 TD0 SCT0 0 1 2 SCT1 SCT2 SCT3 • CPW measured as 0.5 µS. SCT4 Canon 163 Calculator Section: Timing Diagram Page: A2 Rendition: Feb 1, 2024 FF 1 State Cycle 3 4 272 Figure M1 Register-Level Functional Model AD0 AD M2 Register SCT4 M1 Register SCT3 D Register SCT2 C Register SCT1 A Register SCT0 BD B Register SCT0::4 BD0 Figure M2 Delay-Line Storage Organisation with Idle-State Bit Paths at Time TB0 of TD0 of SCT0 Acoustic Delay Line 1341µS 1086µS 258µS 129 bits 1346 2 16 1 272µS 803 136 bits 1088 2 1 0 16 1 W 272µS 136 bits 816 1 D 0 16 1 W 272µS 136 bits 544 D C 0 16 1 W 255µS 12µS 6 bits 272 C A 0 16 1 W 128 bits A 16 4 260 10 8 A B A B A 16 16 16 15 15 2 1 1 W W B A B A 0 0 0 0 4 4 2 2 WA WB Adjustable 274 270 B 16 W 262 258 B 16 2 B 16 1 B 16 2 B 16 1 BD SD <register> = A,B,C,D,1,2 = 0 (LSD) … 16 (MSD) <digit> = 1, 2, 4, W <bit> Canon 163 Calculator Section: Memory Timing Page: A3 Rendition: Feb 1, 2024 B 16 W B 16 W B 16 4 R 6 266 B 16 4 B B 16 16 4 2 Display Latch 4 Adjustable Head Adjustment Screws ∆delay: ~ 80 ns / turn R: CW +delay WB: CCW +delay 1360 1356 1352 1348 1344 2 2 2 2 16 16 16 16 W 4 2 1 AD 6 B 16 1 4 0µ A A 0 0 2 1 M AD0 6 2 B BD0 0 1 Figure M4 Delay Line Read Timing Figure M3 Acoustic Delay Line Timing –1348µS 0µS 4 8 1084 –1344 –1340 –1336 –260 1088 0µS –256 1092 4 –252 1096 8 –248 1336 248 –8 1340 252 –4 0µS 1344 256 0 1348 260 4 1352 264 8 1356 268 12 1360 272 16 1364 272 20 M reset input (CPR) 1µS 2µS M reset M reset (500KHz) CPR delay line read head R CPA ~ 20-30mV CPW WA delay line WA current A1 M set A6 ~ 0.5µS M set input A2 A7 B1 WB B6 M B2 delay line WB current B7 A3 delay line read 2µS window for pulse reception B3 M reset A4 M Figure M5 Decimal Encoding A5 AD0 B5 BD0 Canon 163 Calculator Section: Memory Timing Page: A4 B4 Rendition: Feb 1, 2024 Value W421 0 0000 1 0001 2 0010 3 0011 4 0100 - 0101 - 0110 - 0111 - 1000 - 1001 - 1010 5 1011 6 1100 7 1101 8 1110 9 1111 Clear KC,KCI: during ST: 0=>B, 0=>PB, 0=>SB etc. CC00 Clear Memory CC00 KCM1,KCM2: during ST: 0 => Mn Numeral Entry CC00 KN KP & FN: 1 => FJ1 KP & FN~ CC00 KSH CC01 CC01 CC03 CC03 CC03 CC02 Shift A <–– KNML => A[LSD] PB += 1 if FJ1 (DP pressed) 1 => FN Recall Memory CC00 CC02 1 => FN 1 => FJ1 M2 Add/Subtract CC00 KRM1,KRM2 KRV CC00 CC01 Reverse CC00 Idle, display B. Undo Entry DP Entry 1=>FME KM2ADD,KM2SUB Shift B ––> one digit PB –= 1 CC02 Queue Multiply / Divide KMLT: 1=>FMQ, 0=>FN KDIV: 1=>FDQ, 0=>FN if KMS: 1=>FME KMLT,KDIV CC00 CC01 CC01 CC01 DP-Align RM1,2 CC01 if FME: DP-Align RM1,2 CC03 CC03 CC03 DP-Align RB CC03 if FME: DP-Align RB CC02 2 CC02 2 CC02 A ==> B B ==> A Canon 163 Calculator Section: State Sequence - Short Procedures Page: A5 Rendition: Feb 1, 2024 CC02 Mn => B 1st: M2 ±= B 2nd: if M2<0: 0–B=>B 0=>FME if FME: 1st: M2 ±= B 2nd: if M2<0: 0–B=>B 0=>FME Add / Subtract CC0 Align M1&M2 to DP Set. CC11 KA,KMN Multiply KADD, KSUB Idle, display B. CC0 Idle, display B. Align M1&M2 to DP Set. CC11 KADD, KSUB & MQ KA,KMN KMUL,KDIV & F(M+D) CC13 Align B to DP Setting. CC13 0 => D 0 => C CC12 Align A to DP Setting. CC12 Swap A <=> B registers. 0 => PL CC16 Build product A – D16:1 => A B +=> C CC16 CC17 2 2 if Accumulate (KA=1): 1st iteration (FJ2=0): B +=> M1 2nd iteration (FJ2=1) & SUM<0: 0–M1=>M1, SM1=SM1~ 1st iteration (FJ2=0): B +=> A 2nd iteration (FJ2=1) & SUM<0: 0–A=>A, SA=SA~ A<0 CC15 Shift A <–– 1 +=> PL Undo excess addition & decrement A + D16:1 => A C – B => C CC17 PL=16 PB<>0 Move C => D by shifting up CC14 PB=0 CC10 2 1st iteration( FJ2=0): A=>B, B=>A 2nd iteration (FJ2=1): if KMN: 1 +=> M2 Canon 163 Calculator Section: State Sequence - Add & Multiply Page: A6 Rendition: Feb 1, 2024 CC10 2 Move D => B Accumulate if KA: B +=> M1 Divide Idle, display B. CC0 Align M1&M2 to DP Set. CC11 CC15 Shift C<–– PB+=1 KA,KMN Square Root KADD, KSUB & DQ Idle, display B. 0 => FJ2 CC0 Align M1&M2 to DP Set. CC11 KA,KMN KSQRT CC13 0 => D 0 => C CC13 0 => D 0 => C B <–– CC12 ? CC12 B => A 0 => B CC16 Subtract divisor from dividend, increment quotient if OK. C – B => C if C>0 : D+=1 CC16 Subtract root from radicand, increment root. C – B => C if FJ2~: D += 1 FJ2~ => FJ2 CC17 Undo excess subtraction A + D16:1 => A PB=DL Align ? to DP CC14 CC10 2 Move D => B Accumulate if KA: M1 + B => M1 Canon 163 Calculator Section: State Sequence - Divide & Square Root Page: A7 Rendition: Feb 1, 2024 FJ2~ 2 CC15 FJ2 Shift C <–– if FJ2~: Shift D <–– PB += 1 FJ2~ => FJ2 CC17 2 FJ2=0 PB=DL Align ? to DP CC14 CC10 Undo excess subtraction(s). C + B => C if FJ2~: D –= 1 FJ2~ => FJ2 2 Move D => B if KA: Accumulate B +=> M1 Example Procedure Execution - Subtraction • DP switch =2 • M2 mode switch = Count • Accumulate to M1 = ON • Current Total (RM1) = 20.00 • Last Result (RA) = 5.00 • New number entered (RB) = 8 • Press –= KEY (subtract) 0 mS 1.36 2.72 4.08 5.44 6.80 8.16 9.52 10.88 12.24 13.60 14.96 16.32 TD0 4 0 1 2 3 4 0 1 2 3 4 4 0 1 2 3 4 0 1 2 3 4 SCT4 KSUB~ => KST~ FKD ~ 4.5mS FST FU CC11 CC00 CCnn CC13.0 CC13.1 CC13.2 FC0=0 DL=PA FJ2 CC12 CC16.0 CC16.1 CC17.0 CC17.1 CC10.0 CC10.1 CC00 RM1–=RB nil RA–=RB RA=0–RA RA=RB RB=RA RM2+=1 Idle 12.00 5.00 8.00 12.00 99997.00 –8.00 FC0=1 DL=PA DL=PA DL>PA FC0 FRS Idle Actions Register contents after end of state cycle: Canon 163 Calculator Section: Procedure Execution Timing Page: A8 Rendition: Feb 1, 2024 M1= A= B= 20.00 5.00 8 Assess PM 20.00 5.00 8 Assess PB 20.00 5.00 8 RB<–– PB+=1 20.00 5.00 8.0 RB<–– PB+=1 20.00 5.00 8.00 Assess PA 20.00 5.00 8.00 12.00 5.00 8.00 12.00 3.00 –8.00 12.00 8.00 –3.00 12.00 8.00 –3.00 12.00 8.00 –3.00 Square Root Procedure Sample √2 Radicand FJ2 - 0 16 0 2 - 1 16 1 1 - 1 16 0 0 - 2 16 1 -2 + 2 17 0 0 + 1 17 1 1 1 15 0 10 10 15 1 100 - 10 16 0 90 - 11 16 1 79 - 11 16 0 68 - 12 16 1 56 - 12 16 0 44 - 13 16 1 31 - 13 16 0 18 - 14 16 1 4 - 14 16 0 -10 + 14 17 1 4 14 15 0 40 140 15 1 400 - 140 16 0 260 - 141 16 1 119 - 141 16 0 -22 + 141 17 1 119 141 15 0 1190 1410 15 1 11900 - 1410 16 0 10490 - 1411 16 1 9079 - 1411 16 0 7668 - 1412 16 1 6256 - 1412 16 0 4844 - 1413 16 1 3431 - 1413 16 0 2018 - 1414 16 1 604 - 1414 16 0 -810 + 1414 17 1 604 Canon 163 Calculator Section: Misc. Page: A9 Root State 2 Rendition: Feb 1, 2024 0