Manual / Guide · 1965
Friden EC-130 Three-Counter Service Manual Supplement (December 1965)
The 26-page supplement covering the three-counter EC-130 (serial 8501 on), which drops the B counter.
Manual / Guide · 1965
The 26-page supplement covering the three-counter EC-130 (serial 8501 on), which drops the B counter.
FRIDEN ELECTRONIC CALCULATORS EC-130 SERVICE MANUAL SECTION 5. SUPPLEMENT 1 INTRODUCTION. ...... 4 EB ER RE Ew 8 5-1 THE ENTRY ENCODERS & 4 i 3.8 8 6 10) 8 4 es S*1 THE TIMING CHAIN. ......2.4.6. ee ag ee 5-1 THE PHASE’ COUNTER: & 3 6% be eww eae 5-2 DATA: EUOW 2¢ pick @ ES SABRES ER Bi Sw s 5-2 NORMAL DATA FLOW... 2... 2s eevee 5-2 SHIPE LEET™ «ie: 9: ueh nce oy ee Gel ee a) © SH 5-2 SHIPT UP is: a a ie x cae He ww Ve) M8 wm Ow es 8 5-5 SHIELD DOWN 42 ss Gage Gee SRR we H BSA Ss 5-5 ADD PUNCTION. 265 £28 .5 $3 S62 ASR HE BG 5-9 SUBTRACT: FUNCTION :«: 6 ise ee Bo wwe oe ee 5-10 CHANGE SIGN OF Riba a csi 6 swe ee ew KH Bw 5-11 MULTIPLY FUNCTION «©: i ce gee ere ee 5-12 DIVIDE FUNCTION £8 6% HER BEBE R DES ws 5-14 DIVIDE FLOW CHART: «wee eee eee . 5-14 DECIMAL ALIGN....... ee ee ee ... 5-14 CHANGE SIGN OF Rliii sn cs wigs wie dees ws 5-14 SHIFT DOWN R1 to RMD.......-2.24240464 5-14 SUBTRACT IN DIVIDE FUNCTION. ........ 5-15 SEED TO PSS: uo ie ua we eee seu Ge Oe ee Ko SO 5-15 INCREMENT [R2j: i as ee et a ane ee ww wie 5-15 RESTORE OVERDRAFT (ADD IN DIVIDE). ... . 5-16 SHIFT R2 LEFT. ... 2... 2 ee eee een ves 5-16 OVERFLOW IN DIVIDE. .... 2+ 22s ee ees 5-16 SHIFT RL-EEPT. «ccs wes ee ee ee ew 8 5-16 SHIFT DOWNINPS7....... Swasimweare s BLS CONCLUSION AND SUMMARY.........-.. 5-17 DECIMAL POINT COUNTER.........+4.++--. 5-17 DISPIEAMS co: «: iy ces 6s uss & el oe ee 5-17 SEGMENT GENERATOR ..... 2 ee ese eee 5-17 SEGMENT SWITCHES. ..... 2... eee swe 5-20 HORIZONTAL STAIRCASE GENERATOR ..... 5-20 COMPARE AND INTENSIFICATION ...... .. 5-22 Courtesy of The Old Calculator Museum http://oldcalculatormuseum.com viti FRIDEN ELECTRONIC CALCULATORS EC-130 SERVICE MANUAL FIGURE PAGE 5-1 ENTRY ENCODER TRUTH TABLE, ......-..eee2. Srl 5-2 MASTER OSCILLATOR... 21 ee ee eee ere ere eene 5-2 5-3 DIVIDE FLOW CHART 663 bbe bee ewe Be ee ew 5-4 5-4 SHIFT DOWN-DATA ORGANIZATION ........+4.266-. 5-5 5-5 SHIFT DOWN- TIME RELATIONSHIPS ............ 5-6 5-6 SHIFT DOWN-SHIFT UP THE SYNC PULSE......... 5-6 & 5-7 5-7 SHIFT DOWN-EXAMPLE WITH DIGITS ..... a ae aE me 5-7 5-8 MULTIPLY FLOW CHART (FOLDOUT) ........... 5-23 5-9 DIVIDE FLOW CHART (FOLDOUT) ..........244.4. 5-25 5-10 DECIMAL POINT COUNTER LOGIC .......++.24.. 5-18 (FOUR COUNTER EC-180) 5-11 DECIMAL POINT COUNTER LOGIC .......-.-++.4.-. 5-19 (THREE COUNTER EC-130) 5-12 SEGMENT GENERATOR .... 2.10 ee eee eeves ... 5-20 5-18 SEGMENT SWITCHES, «i wis cis wes Ges eeweae S21 5-14 HORIZONTAL STAIRCASE GENERATOR. .......... 5-21 Courtesy of The Old Calculator Museum http://oldcalculatormuseum.com 12-15-65 A. INTRODUCTION This article is written as a primary training device and presupposes a thorough understanding of the detailed logic of the EC-130 Calculator. It is intended that the student, using only this article and the associated block diagram, will be able to grasp both the logic and the circuitry of this ma- chine by drawing upon his background of training and experience on the EC-130 Calculator. Because this is not a new machine but a rede- sign of the existing EC-130, many basic circuits are identical or nearly identical to existing cir- cuits in the EC-130. These areas will be passed over lightly or not touched upon at all. This will limit the subject to the differences in logic and circuitry between the Three Counter EC-130 and Four Counter EC-130. This limitation has two advantages. First, it reduces the size of the vol- ume to a small package of vital information and, second, it avoids the discouragement which nor- mally accompanies the thought of plowing through a massive volume of already familiar information to find the desired information. B. THE ENTRY ENCODER The Entry Encoder is a scale of eight binary counter which has only parallel inputs and parallel outputs. It consists of three flip-flops, and re- places the Change Sign, Shift Down, Store, Recall, Repeat, and Add or Sub flip-flops. The Entry En- coder is used in the Change Sign, Clear Entry, Store, Recall, Repeat, Add, and Subtract functions, and the appropriate keyboard switches are used to set the Entry Encoder flip-flops. The keyboard is the same as the one used in the Four Counter machine so there are necessarily some changes in the keyboard interface to permit one switch to set the proper binary code into the Entry En- coder. The enclosed Encoder Truth Table (Figure 5-1) shows which Encoder flip-flops are set by each of the seven keyboard switches listed. The Encoder flip-flops are reset after each function ENTRY ENCODER TRUTH TABLE FLIP-FLOP 1/2 {4 RECALL 1/0/0 CHG SIGN 0o;}1/1{0 REPEAT 1 1 | 0 CLEAR ENTRY | 0/011 ADD SUB 1; 0]14 STORE 0} 1 1 Figure 5-1 FRIDEN ELECTRONIC CALCULATORS EC-130 SERVICE MANUAL SECTION 5 Supplement 1 so it isnot necessary to reset any flip-flops with a keyboard switch. It is necessary only to set the appropriate flip-flops; however, because each flip-flop can be set by more than one switch, the switch outputs are applied to the flip-flops through diode OR gates. For example, the EEN2 FF can be set by the Change Sign switch, the Repeat switch, and the Store switch. These switch outputs are applied to an OR gate, and the output of the OR gate is integrated to provide the DC enable signal for the AC AND gate which sets the EEN2 FF. Note, also the connection between the Add switch and the Subtract switch. This connection exists for the same reason as on the Four Counter machine, The Subtract switch must enable the Sign Control FF to be reset and the Add switch must not, but both switches must enable the EEN1 FF and the EEN4 FF to be set. Hence, a diode is connected to isolate the two switches in one direction and connect them in the other direction. The Clear Entry switch is not used as an input to the OR gate which sets the EEN4 FF because the output of the Clear Entry switch must be used to reset the Overflow FF as well as to set the EEN4 FF; whereas it is not desired to have the outputs of the Add, Subtract, or Store switches enable the re- setting of the Overflow FF. , The Encoder is reset at the end of each function by ERFS3 (the same signal which resets the func- tion flip-flops in the Four Counter machine). C. THE TIMING CHAIN There are a few changes in the timing chain, but all are relatively simple. The emitter follow- ers have been removed from the set outputs of the D, E, F, and G flip-flops because there is in- sufficient loading of these signals to warrant the additional drive. The P flip-flop has beenelimin- ated and R1 will not be intensified. The clock flip-flop has been eliminated, and the output of I-169 is used as the clock signal and triggers the A flip-flop. Since the clock frequency must stay at about 333KC, the master oscillator frequency is cut in half by using .0056 pf and .0033 yf capacitors in the tank circuit in place of the 1500 pf and the 820 pfcapacitors. The emitter fol- lower and the inverter in the oscillator circuit have also been changed to provide the risetime and falltime necessary for the clock signal. The new oscillator circuit is shown in Figure 5-2. An extremely important point to remember is that the A, B, and G flip-flops are still preset so that the sync pulse ALWAYS comes off the delay line in B3 R38 CO time. This is true irregardless of the position of data in the delay line with re- o-1 Courtesy of The Old Calculator Museum http://oldcalculatormuseum.com spect to the sync pulse. (This is also true in the Four Counter machine but this point bears re- emphasizing.) Much will be made of this later. Two other changes involve the decoded timing signals. Since TC04 is needed as well as TC03, TCO03 is now an input to an inverter (I-301) to generate TC04. Also, C15 is no longer developed as a separate signal. So the OR gate that develops TCX5 (I-229) has four timing signal inputs which define C15 time. The same signals are also used at two other OR gates to define C15 time. All in all, the timing chain has not been changed much. D. THE PHASE COUNTER Only one very small change has been made in the Phase Counter. Since M1AD3 is no longer de- veloped, MSU3 is used to inhibit stepping the counter to PS6 from PS5 in divide. This will also inhibit stepping from PS4 to PS5 so an AC AND gate is used to set the PCl FF in PS4 of divide. AC AND gate 1171 is enabled by MSU3 and HOME 1 is the trigger. So, when the Phase Count- er is in PS4 of Divide A-1171 enables HOME1 to step the counter to PS5, but does not enable it to be stepped to PS6 until MSU3 is lost. This poses an interesting question. Is MSU3 detrimental to the operation of the counter in subtract? No, it is not, because MSU3 is not developed until PS7 of subtract, and although MSU3 inhibits stepping the counter to PSZ, PS73 and HOME1 reset the CF FF and the Phase Counter is pulled to PSZ by the override reset. PSZ3 is no longer decoded because it is no longer needed. 5-2 SECTION 5 FRIDEN ELECTRONIC CALCULATORS 12-15-65 Supplement 1 EC-130 SERVICE MANUAL -12V a, g 33K 3 1.5K TOSC4 .047uf 1.5K {|v 1 1.5K 3.3K Figure 5-2 E. DATA FLOW 1. NORMAL DATA FLOW In this machine, data flow in machine idle is serial from the delay line to the A Counter, par- allel from the A Counter to the C Counter, and serial from the C Counter to the delay line. Hence, “normal” data flow uses only twocounters instead of three as in the Four Counter machine. The B Counter has been eliminated in this machine. 2. SHIFT LEFT Elements 121 and 122 actually enable SAD9 to be generated, and elements 128 and 129 actually enable SDC9 to be generated. To enable SAD9, one of the inputs to OR gate 121 must be logic 1 (0 volts). To enable SDC9, one of the inputs to OR gate 128 must be logic 1. The inputs to these two OR gates come from Inverters I-094, I-101, I-096, and I-105. I-105 will not be discussed be- cause the logic used to complement R1 is the same in both machines. To enable SAD9 in Recall or Repeat, the output of I-094 must be logic 1, so the input to I-094 must be logic 0 (negative). The output of AND gate 093 will be negative when any input is negative. To enable SDC9 in Recall or Repeat, the output of I-096 must be logic 1, so the input to I-096 must be logic 0. The output of AND gate 093 will be negative when any input is negative. The development of SAD9 and SDC9 to shift left, shift up, and shift down is controlled by I-101. To enable SAD9 and SDC9, the output of I-101 must be logic 1, so the input must be logic 0 (negative). This will occur when any input to AND gate 100 is negative. Courtesy of The Old Calculator Museum http://oldcalculatormuseum.com >) 12-15-65 In further description of the logic to enable SAD9 or SDC9 to be developed, the signal will be considered developed when an input to AND gates A-093, A-100, or A-092 has been proved to be negative. a. DIGIT ENTRY. Shift left is done the same as in the Four Counter machine. For example, in a digit entry, OR gate 060 and Inverter 061 develop MEIL3 which develops M1L4. M1L4 is an input to OR gate 097 to develop SADY and SDC9 at the end of R1 time. b. DECIMAL ALIGN. Align shift R1 left is devel- oped the same way as entry shift R1 left except that OR gate 053 and inverter 054 develop MAIL3 which develops M1L4. c. ENTRY AND ALIGNSHIFT LEFT OVERFLOW. ‘If an overflow occurs in entry-or-align-shift-R1<. .. left, the overflow is determined by AC AND gate 1224 at the input of the Overflow flip-flop. CDZ4 is the DC input, andECD2is the AC input. If there is a digit other than zero in R1 C14, and another digit is entered into R1, then the digit that was in R1 C14 is shifted into D at B15 R1 C14 time in PS7 and no more SAD9 pulses are generated. So the digit stays in the D Counter andis there when HOME1 resets the Common Digit flip-flop. ECD2 transitions positive and sets the Overflow flip- flop. \If there is an overflow in align shift R1 left in PS1, it is necessary to terminate the function at the end of PS1. If the function were allowed to continue with an overflowed number, errors could develop. If there is an overflow in PS1 of a func- tion AC AND gate 1103 resets the Common Func- tion FF at the end of PS1. Ifthe overflow FF sets in PS1, AOFL1 is positive and enables A 1103. When the Phase Counter steps off of PS1 to PS2 or PS6, the output of OR gate 029 goes positive and resets the Common Function FF, thus ter- minating the function. The overflow which results from align shift R1 left, or shift R2 left in Multiply or Divide is sensed by OR gate 108. Four timing signals at the input of OR gate 108 define C15 time. TFG1 is a,convenient signal which transitions to 0 volts in time, and EDPS2 assures that allthe mul- tiplier or dividend has been operated upon before RSLO3 can be developed. PS73 and PS12 define PS1 or PS3 or PS5. The output of this gate is used to develop RSLO38 in C15 time of PS1 in an align shift R1 left, in C15 time of PS3 in a multi- ply problem, and in C15 time of PS5 in a divide problem if R2 is being shifted left. MSU3 is ap- plied to OR gate 108 to assure that RSL03 won’t be developed in PS5 of divide unless R2 is being shifted left. Thus, as long as the machine is sub- tracting in PS5 of Divide, the gate is inhibited, but when a carry overflow stops the subtract FRIDEN ELECTRONIC CALCULATORS EC-130 SERVICE MANUAL SECTION 5 Supplement 1 cycle and shift R2 left begins, MSU3 permits RSLO38 to be developed. Although RSLO3 will be developed every PSI, every PS3, and every PS5, it will not interfere with the machine operation in the wrong function. For example: Every time the machine goes into PS1, either nothing is done, or MA1L3 (align shift R1 left) is developed. If MA1L3 is developed, the DPS FF must be set, so RSLO3 is generated. If the DPS FF is already set when the machine goes into PS1, and MAILS3 is not developed, RSLO3 is still generated, but has no effect because the machine does nothing if MA1L3 is not developed. Every time the machine goes into PS3, either nothing is done (as in the case of a divide prob- lem) and no harm is done by generating RSL03, or R2 is shifted left (as in the case of a multiply problem) and RSLO3 will be generated if the DPS FF is set. Every time the machine goes into PS5ina mul- tiply problem, either nothing is done, or a count of 1 is added to R2. neither case, it doesn’t mat- ter that RSLO3 may be developed. Every time the machine goes into PS5 in a divide problem, either RMD is subtracted from R1, and a count of 1 is added to R2, or RMD is added to R1 and R2 is shifted left. If the machine is subtracting in PS5 of Divide, MSU4 inhibits RSL03 to avoid any inter- action. If the machine is adding RMD to R1 and shifting R2 left, RSLO3 will be developed if the DPS FF is set. d. MULTIPLY SHIFT R2 LEFT. OR gate 048 generates the signal to shift R2 left in a multiply problem, so naturally one input to OR gate 048 is EMU2. Three other inputs, PC12, PC22, and PC41, . define PS3. The twotiming signals TFE2 and TFF1 define R2 time, and TCX5 limits the columns in- volved in the shift R2 left to C2 through C14. The only time the output of OR gate 048 goes negative (logic 0) is in PS3 of Multiply, and only during the R2 times between C2 and C14. The output of OR gate 048 is applied to AND gate 100 and in- verter 101 to enable the generation of SAD9 and SDC9. e. DIVIDE SHIFT R2 LEFT. OR gate 039 is used to generate SAD9 and SDC9 to shift R2 left in Divide. EDV2 is, of course, one input to OR gate 039. Another input is ACOF2. The Carry Overflow flip-flop is set in Divide at the endof the subtract cycle because there is an overdraft. Per the Three Counter machine Divide Flow Chart in Figure 5-3, the next thing to be done is shift R2 left and add RMD to R1. OR gate 039 takes care of shifting 5-3 Courtesy of The Old Calculator Museum http://oldcalculatormuseum.com SECTION 5 FRIDEN ELECTRONIC CALCULATORS 12-15-65 Supplement 1 EC-130 SERVICE MANUAL DIVIDE FLOW CHART (3 COUNTER EC-130) C) DEC ALIGN RESET DPS (2) SET DPC TO 2 SHIFT R1 DOWN mm! (3) NOTHING ‘ YES 7 NO =0? f { —_Pc=07 > Y a DPs SET? °° 1 SET DPS @ SET DPC To 16'S COPLEMENT OF DEC POSITION a4 G) [| Ri-RMo | YES NO ———{ cor ser? )*° G) R2+1 R1-RMD y YES — NO {cor set? = mel G) R1+RMD SHIFT R2 LEFT ' helt i =o? \NO —~{__ppc=0? ~~» 7 G) NOTHING | © SHIFT R1 LEFT INCREMENT DPC d @ SHIFT DOWN STEP TO PSZ Figure 5-3 5-4 Courtesy of The Old Calculator Museum http://oldcalculatormuseum.com 12-15-65 R2 left in PS5. TFF1 and TFE2 define R2 time, and TCX5 defines C2 through C15 times. 3. SHIFT UP Shift up in the Three Counter machine is much the same as in the Four Counter machine. With normal (idle) data flow from the A Counter to the C Counter, to shift up, the data must be shifted from the A Counter to the D Counter, and from the D Counter to the C Counter. Timing is the same in this machine as in the earlier model EC-130. There are three ways to utilize the shift up feature; Repeat, Recall, and the first entry of a digit entry. a. REPEAT FUNCTION. The Entry Encoder code for Repeat is a binary three. This is reflected in OR gate 090, which is used to generate SAD9; and OR gate 091, which is used to generate SDC9. Both these gates have EEN12 and EEN22 as inputs. (Actually, these two signals alone define a code of three or a code of seven, but since the code seven isn’t used, it isn’t necessary to have EEN41 on the gates.) The only other input on OR gate 090 is PS64, so SAD9 will be generated every R time in PS6. PS64 is also an input to OR gate 091. But, OR gate 091 also has three other inputs. TCO3 assures that SDC9 will not be generated in CO time (which would create sync pulse prob- lems), TFG1 inhibits SDC9 during RS and RMD times, and TR13 inhibits SDC9 during R1 time. Thus, data is preserved in RS, RMD, and Rl times, and R2, R3, and R4 datais shifted up. This logic is nearly identical to that in the earlier machine. b. RECALL FUNCTION. Recall is gated by an Entry Encoder code of one. So the two OR gates FRIDEN ELECTRONIC CALCULATORS EC-130 SERVICE MANUAL SECTION 5 Supplement 1 used to develop SAD9 and SDC9 in recall will have EEN12, EEN21, and EEN41 as inputs. OR gate 089 (used to develop SAD9) has two other inputs; PS64 defines PS6, and TR03 inhibits the development of SAD9 in RMD time. OR gate 088 also has two other inputs. PS64, as in OR gate 089, and TC03, which inhibits SDC9 to preserve the syne pulse in B3 R3 CO time. This logic is nearly identical to the Recall logic in the Four Counter EC-130. c. SHIFT UP IN THE DIGIT ENTRY OPERATION. Shift up in a digit entry is gated by OR gate 099. Since the Entry Encoder is not set in a digit entry, no Encoder signals are applied to OR gate 099. Thus, the logic for OR gate 099 is identical to that in the earlier EC-130. 4, SHIFT DOWN Shift down in this machine is radically differ- ent from the method used in the Four Counter machine. A shift down in the normal sense of the word cannot be done because there is no counter which can be bypassed. Shift down in the new EC-130 is a rather more complex idea and a cor- rect concept of timing becomes of paramount importance. Figure 5-4a shows a portion of the data ina machine as organized on the delay line. Figure 5-4b shows the same data AFTER shifting down R1, R2, R8, and R4. Note that the data that was in R1, R2, R38, and R4 is now 48 ps closer to the sync pulse than before the shift down. In fact, whether a digit is in RS, RMD, R1, R2, R3, or R4 depends solely upon its proximity to the sync pulse. Ccop———— Gi C2 C3 >-— R3 R4{1RS RMD RI R2 R3 R47ERS RMD Ri R2 RS RA RS _/ | ofo]i f2]3i4] ) ; Figure 5-4a R3 R4 RS RMD RI R2 R3 R4 RS RMD RI_ R2 R3 loli f2[3]4[o] | Figure 5-4b 5-5 Courtesy of The Old Calculator Museum http://oldcalculatormuseum.com SECTION 5 FRIDEN ELECTRONIC CALCULATORS 12-15-65 Supplement 1 EC-130 SERVICE MANUAL Look at Figure 5-5a. If a single pulse is 480 ps pulse. Hence, it MUST be in RMD C2 time. It — from the sync pulse, it MUST be in R1 C2 time, has been shifted down. Now a general (but im- The act of shifting Rl down merely moves that portant) statement can be made. TO SHIFT pulse 48 ps closer to the sync pulse. In Figure DATA DOWN, IT IS NECESSARY ONLY TO 5-5b, that pulse is only 432 us from the syne MOVE THAT DATA 48 pps CLOSER TO THE SYNC PULSE, RS R44RS RMD RI R2 RZ R4]RS RMD ARI R2 RS R4{9RS , ] | j — 480us >| Figure 5-5a RS R4 RS RMD RI R2~ RB R4 RS RMD RI R2 R3 R4 RS , | l / —- 432us _ Figure 5-5b Would the result be the same if the syne pulse were moved closer to the data? At first glance one would say, no! But, look closely at Figure 5-6a which shows the sync pulse in B3 R3 C0, a pulse in B3 R1 C2 (480 ys from the sync pulse), and a pulse in B3 R2 C2 (528 ys from the sync pulse). Now suppose the sync pulse is shifted up to B3 R4 CO, as drawn in Figure 5-6b. This time the syne pulse is moved 48 ds closer to the data instead of vice versa. It appears that there is no change in the position of the data, but now the first pulse (in B3 R1 C2) is only 432 ys and the second is only 480 ys from the sync pulse. When these three pulses count back onto the delay line CO Cl 4 G2 CS R3_—R4 | RS RMD RI R2 RBZ R417RS RMD RI Re. RS R49RS , / | il H 480 | J pS —e 528 ps > Figure 5-6a RS R4 RS RMD RI R2 R3 R4 RS RMD RI R2_ R3 R4 Rs | — | | / 432s —s! | | 480ps > ~ Figure 5-6b 5-6 Courtesy of The Old Calculator Museum http://oldcalculatormuseum.com 12-15-65 they maintain this time relationship. When the sync pulse counts back off the delay line it is re- established in B3 R3 CO (Figure 5-6c) time. So the nearest pulse, only 432 ys later, MUST be in R3_ R4 RS RMD RI R2_ R3 FRIDEN ELECTRONIC CALCULATORS EC-130 SERVICE MANUAL SECTION 5 Supplement 1 RMD C2 time, and the second, 480 ys from the sync pulse, MUST be in R1 C2 time. Clearly, shifting up the sync pulse has the same effect as shifting down data. R4¢_ RS RMD RI R2 RS R44 RS | Ul / J | | 432s 480 ps | ! Figure 5-6c The problem now is that shifting up the sync pulse shifts down ALL data including RS. Fortun- ately, it is a simple matter to correct this. If RS is shifted up to RMD in the same line pass that the sync pulse is shifted up, then in the next line pass when all data is resynchronized 48 ps early, the original RS data will still be in RS time. For example, suppose there is data in C2 as shown in Figure 5-7a, and R1, R2, R8, and R4 are to be shifted down in a Clear Entry function. Shift down in Clear Entry is done in PS6, soin PS6 when the syne pulse counts off the delay line, it synchronizes the timing chain, thus establishing itself in B3 R3 CO time, and establishing All data in their proper times. Then the sync pulse is shifted up (delayed 48 ps) into R4 CO time. Since the timing chain is already running, this has no effect on the data as it counts off the delay line. As this data comes off the delay line, all RS data is shifted up (de- layed 48 us) into RMD time (see Figure 5-7b). When the sync pulse counts off the delay in the next line pass (PS7), it resynchronizes the timing chain so that all data is shifted down, and the RS data that was shifted up into RMD is once again in RS time Ri, R2, R3, and Ré4 data are shifted down as shown in Figure 5-7c. CO Cl Ge 1C3 R3 R4 |] RS RMD RI R2 R3 R44RS RMD RI R2 R3 R4 TRS / | 6/o}1]/2/13}4] » 384ps > ® 480us Figure 5-7a R3 R4 RS _ RMD RI R2__R3 R4 RS RMD RI R2 R3 _ R4 RS_ | Ol6}1}213]14] / I 384 al ras i Figure 5-7b R3 R4 RS _ RMD RI R2 R3 R4 RS RMD RI R2 R3 R4 RS__/ 6/1 };2}| 3,4] O] ! _] / _, 432us i Figure 5-7c Courtesy of The Old Calculator Museum http://oldcalculatormuseum.com SECTION 5 Supplement 1 a. SHIFT DOWN R1, R2, R38, R4 IN CLEAR EN- TRY, ADD, SUBTRACT, MULTIPLY AND DI- VIDE. This, then, is the basic theory of shift down. The operation just described occurs in PS6 of Clear Entry. But the same thing happens in PS6 of the Add, Subtract, and Store functions as well as in the Clear Entry function. The two OR gates that are used to shift up the sync pulse and RS are OR gate 310 and OR gate 304. OR gate 310 is used to generate SAD9 and SDC9 in CO time to shift up the sync pulse in the Clear Entry, Add, Subtract, and Store functions. PS64 is one input to OR gate 310 and enables the sync pulse to be shifted up only in PS6. EEN42 is another input because the only time EEN4 FF is set is in any one of the above functions. The third input to OR gate 310 is TC04. Thus, OR gate 310 enables SAD9 and SDC9 to be developed in R3 CO and R4 C0. OR gate 304 enables SAD9 and SDC9 to be developed in RS and RMDofallC times to restore RS to its original position with respect to the sync pulse. There are three inputs to OR gate 304 EEN42 gates for Add, Subtract, Store, or ‘Clear Entry, and PS64 gates for PS6. TFG2 inhibits the OR gate during R1, R2, R3, and R4 times. So OR gate 304 enables SAD9 and SDC9 during RS and RMD times. This will put RS data in RMD time and leave RMD data in the D Counter. If this is left in the D Counter, it will be placed in the next R$“time when the next SAD9 and SDC9 are devel- oped, Hence, CRD9 must be developed to clear RMD out of the DCounter. OR gate 305 will enable CRD9 when its output is logic 0 (negative). Two inputs to O-305 are EEN42 and PS64, the same as on 0-304. TR14is the third input to O-305. This means that when O-304 is gating SAD9 and SDC9 to shift RS up, O-305 enables CRD9 to reset the RMD data out of the D Counter in the following R1 time. The net effect of the operation of OR gates 310, 304, and 305 is that R1, R2, R3, and R4 are shifted down, and RS remains in RS in the Add, Subtract, Store, and Clear Entry functions. b. SHIFT DOWN R1 IN MULTIPLY AND DIVIDE. To shift down R1, R2, R3, and R4in PS7 of Multi- ply or Divide, OR gates 308, 302, and 303 are operated. OR gate 308 enables the sync pulse to be shifted up only in PS7 of Multiply or Divide. OR gate 302 is responsible for enabling SAD9 and SDC9 in RS and RMD of all column times to shift up RS in PS7 of Multiply or Divide. (TFG2 is negative during RS and RMD times). As before, the RMD data must be cleared out of the D Counter each column time, and OR gate 303 enabled CRD9 to be generated at the end of each R1 time in PS7 of Multiply or Divide. To shift down R1 and clear R1 to zero in PS2 of Multiply or Divide, it is necessary to shift up 5-8 FRIDEN ELECTRONIC CALCULATORS EC-130 SERVICE MANUAL 12-15-65 the sync pulse, then shift up RS, R2, R3, and R4 causing that data to remain in synchronization to keep it where it was. This puts Rl in RMD. Two OR gates are used to accomplish this. OR gate 306 enables SAD9 and SDC9 in eachRtime of PS2 except R1 time. (Remember that the only time the machine steps to PS2 is in Multiply or Divide, and we ALWAYS want to shift R1 down to RMD in PS2.) This means that all R times except R1 time are shifted up with the sync pulse. This puts all R times except R1 in their original positions with respect to the sync pulse. R1 is 48 Ms closer to the sync pulse, which is effectively a shift down of Ri, however, the method described has a drawback. SAD9 and SDC9 are generated for each R time except R1. At the end of RS time, SAD9 and SDC9 are generated, and RS data goes to the D Counter. Whatever was in the D Counter goes to RS time in the C Counter, At the end of RMD time SAD9 and SDC9 are again generated: RMD data goes to the D Counter, and RS data goes to RMD time in the C Counter. SAD9 and SDC9 are inhibited in R1 time so the RMD data stays in the D Counter, At the end of R2 time SAD9 and SDC9 are again generated; R2 data is shifted into the D Counter, and the contents of the D Counter (RMD data) is shifted into R2 time. This means that in the next line pass when the results of shifting up the syne pulse are seen, R1 will have been shifted down to RMD as expected, but RMD will have been shifted up into R1. This is grossly wrong! R1 must be cleared out so that the multiplier or dividend in R2 can be shifted into R1, digit by digit. If RMD is shifted into R1, it will appear to the machine that the RMD data is the most sig- nificant part of the multiplier or dividend. Clearly, RMD must not be allowed to reach R1 time. The easiest way to stop it is to reset the D Counter to zero when RMD data is present in the D Counter. Then when SAD9 and SDC@9 are generated at the end of R2 time, zeros will be shiftedinto R2. The RMD data is shifted into the D Counter at B15 RMD time and the next SDC9 will occur at B15 R2 time. Between these two times, the D Counter must be reset to zero. The obvious time to do this is B15 R1 time. OR gate 050 enables CRD9 in each R1 time in PS2. The three Phase Counter signals define PS2, and TR14 defines R1 time. No other signals are necessary because the only time the machine is in PS2 is in Multiply or Divide. ce. STORE FUNCTION. Shift down in Store is a little different because R1 data must be advanced twice. This means that the syne pulse must be shifted up twice in addition to shifting up other R times to keep them in the right position with respect to the sync pulse. OR gates 310, 304, and 312 are used to accomplish this. You are already familiar with the operation of OR gates 310 and 304. They areused to shift down Courtesy of The Old Calculator Museum http://oldcalculatormuseum.com 12-15-65 R1, R2, R3, and R4 in Add, Subtract, Clear Entry, and Store. These two gates put R1 data in RMD time, R2 data in R1 time, R8 datain R2 time, and R4 data in R38 time. R4 is left empty. This takes one line pass and is done in PS6. The only thing remaining to be done is to put the data now in RMD into RS, but it is equally important NOT to further shift down all the other R times. Since shifting the sync pulse up is the same as shifting ALL data down, in addition to shifting up the sync pulse, we must shift up all R times except RMD. OR gate 312 performs this operation in PS7 of Store. EEN42 and EEN 22 define the Store function, PS74 gates for PS7, and TR03 inhibits the output during RMD time. Hence, OR gate 312 enables SAD9 and SDC9 for the sync pulse, RS, R1, R2, R3, and R4. In conclusion, shift down is not difficult to un- derstand as long as the student thoroughly under- stands basic data organization. F. ADD FUNCTION To begin the Add function the Entry Encoder must first be set to a binary code of five. This is the code for both the Add and Subtract functions and corresponds to setting the Add or Subtract FF in the Four Counter machine. 1. ENTRY ENCODER LOGIC When the Add switch is closed, 0 volts is ap- plied to OR gates 322 and 324. This 0 volts en- ables AC AND gates 1663 and 1681 to set EEN4 FF and EEN1 FF, respectively. EKBD3 is the AC input to all the gates which set the Entry En- coder flip-flops, so after about 6 ms the Entry Encoder is set to a binary code of five. When the Phase Counter steps to PS1, OR gate 053 will develop MAIL3 until R1 is decimal a- ligned, then the Phase Counter will jump to PS6. 2. SIGN CONTROL LOGIC In PS6, two things are done: (a) The Sign Control FF checks the signs of R1 and R2 to determine if the ultimate opera- tion will be an addition or subtraction. The Sign Control FF is normally clamped inthe set condition during machine idle by ERF3 applied to ASC1 as an override set. If the flip-flop is still set at the beginning of PS7, the machine will add; if it is in the reset condition at the beginning of PS7, the machine will subtract. OR gate 007 samples the signs of R1 and R2, and to do this it must have several inputs. EEN12 and EEN42 gate for an Add or Subtract function. TC14 and PS64 limit the sampling to C1 time of PS6. TFF1 further limits the Courtesy of The Old Calculator Museum FRIDEN ELECTRONIC CALCULATORS EC-130 SERVICE MANUAL SECTION 5 Supplement 1 sampling to Rl and R2 times, and XRDL4 provides the actual sign information from the delay line, If all these conditions are met, and there is a minus sign inRlorin R2, the output of OR gate 007 will go negative (logic 0) for about 1 us. This negative transition is inverted by I-008 and will reset the Sign Control FF. If the Sign Control FF remains reset, the machine will subtract. But if there are minus signs in both Ril and R2, there will be two transitions at the output of OR gate 007; the first will re- set the flip-flop, and the second will set it again, and the machine will add, Ifboththe signs of R1 and R2 are positive, there will be no transitions to reset the flip-flop and the ma- chine will add. It will be assumed that the Sign Control FF is in the set condition at the end of PS6. (b) The second thing which occurs in PS6 is the shift down of R1, R2, R3, and R4. Recall that this is accomplished by shifting the sync pulse up, which is the same as shifting every- thing down. Then RS is shifted up to put the RS data back in RS time. Since both are done in the same line pass, it appears (and indeed is true) that the sync pulse is shifted up to B3 R4 CO, and that each RS data is shifted up into RMD time. But when the sync pulse counts off the delay line in PS7, it is re-established in B3 R3 CO time (48 ps earlier thanit was in PS6 after the shift up), and thus ALL data is re- established 48 ps earlier in PS7. This amounts to a shift down of R1, R2, R3, and R4. OR gate 310 enables SAD 9 and SDC9 when its output is negative. Its output will be negative in CO time of PS6 in Add or Subtract. OR gate 304 enables SAD9 and SDC9Yineach RS and RMDtime of PS6 in Add or Subtract. (Additional shift down infor - mation can be obtained under Topic E4). 3. DEVELOPMENT OF MAD4 In PS7 the actual addition is done. Once again assuming that the Sign Control FF was in the set condition at the end of PS6, ASC2 is negative and ASC1 is positive. Because ASC1 is positive at the input of OR gate 023, MSU4 cannot be generated, but ASC2 is negative and is an input to OR gate 021. When the output of OR gate 021 goes negative MAD4 will be generated. The other three inputs to OR gate 021 define PS7 andthe Add or Subtract functions. In either an Add or Subtract function, the Entry Encoder is set to a binary code of five, hence the use of EEN12 and EEN42. So the only time the output of OR gate 021 will be negative is in PS7 of an Add or Subtract function when the Sign Control FF is set. ASC2 assures that the function is Add instead of Subtract. When the out- put of O-021 goes negative, it causes MAD4 to be developed by 1-020. 5-9 http://oldcalculatormuseum.com SECTION 5 Supplement 1 4, OVERFLOW If the addition yields an overflow, the overflow is sensed by the setting of the Carry Overflow FF, ACOF1 is the AC input to AC AND gate 1221 on the Overflow FF. The DC input to 1221 is MA1S38. Anytime the Carry Overflow FF sets in an Add function, the Overflow FF will be set by AC AND gate 1221. (Note: OR gate 311, which generates MA1S3 in a Divide, cannot cause MA1S3 to be generated before the Carry Overflow FF is set (ACOF2 negative). This means that ACOF1 has already transitioned positive BEFORE MA1S3 can go positive. Hence, in a Divide, the trigger occurs before the DC enable, and AC AND gate 1221 cannot set the Overflow FF.) G. SUBTRACT FUNCTION The basic Subtract functionis the same asin the earlier EC-130, however, there are some changes, mainly caused by using the Entry Encoder. 1. ENTRY ENCODER LOGIC The Entry Encoder is set exactly the same way as in Add. When the Subtract switch is closed, the diode connecting it to the Add switch becomes forward biased to permit EEN4 FF and EEN1 FF to be set by EKBD3. The Subtract switch output is also used as a DC enable to AC AND gate 1143 (Sign Control FF). When EKBD3 transitions posi- tive, A-1143 will reset the Sign Control FF. If the Sign Control FF stays reset, the machine will subtract. Whether the Sign Control FF stays re- set will depend upon the result of checking the signs of R1 and R2 in PS6. When the Phase Counter steps to PS1, an align shift R1 left will be generated if necessary by OR gate 053. After the alignment is completed, the Phase Counter jumps to PS6, 2. SIGN CONTROL AND SHIFT DOWN LOGIC In PS6 two things will be accomplished. The Sign Control FF checks the signs of R1 and R2 to determine whether the ultimate operation will be an addition or a subtraction. Recall that the Sub- tract switch reset the Sign Control FF at the be- ginning of the function. If the Sign Control FF is in the reset condition at the end of PS6, a subtract operation will be performed; if it is in the set condition at the end of PS6, the machine will add. There are six inputs to OR gate 007 to gate for the signs of Rl and R2. EEN12 and EEN42 define the Add or Subtract functions. PS64 limits the sampling to PS6 time and TC14 further limits the sampling to column one. TFF1 is negative only during R1 and R2, so the only time the output of FRIDEN ELECTRONIC CALCULATORS EC-130 SERVICE MANUAL 12-15-65 O-007 can possible go negative (logic 0) is during R1 or R2 of C1 time in PS6or an Add or Subtract function. If there is a pulse in R1 Cl time it means that the sign of R1 is negative. If the sign of R1 is negative, XRDL4 will transition negative in Rl Cl time and the output of O-007 will go negative. This is inverted by I-008 whose output is applied to the T input of the Sign Control FF. Since the flip-flop is already reset, the output of the inverter will set the flip-flop. Ifthe Sign Con- trol FF stays set, the machine will add. If, how- ever, there is a minus sign in R2 as well as in R1, the output of I-008 will transition positive twice, resetting the flip-flop with the second pulse, and the machine will subtract. R1, R2, R8, and R4 are shifted down. The ma- chine does this by shifting up the sync pulse and RS. The sync pulse is shifted up by gating to enable SAD9 and SDC9 during each R time of CO time. OR gate 310 accomplishes this. EEN42 gates for the Add, Subtract, Clear Entry, or Store functions. TCO4 enables the OR gate in all R times of CO time, and PSG4 limits the operation of the gate to PS6 time. So the output of the gate is negative in R83 or R4 of CO time in PS6 of Subtract. When the output of O-310 is negative, SAD9 and SDC9 are enabled and this results in the shift up of the sync pulse. OR gate 304 is used to enable SAD9 and SDC9 in RS and RMD to shift up RS. EEN42 and PS64 gate for PS6 of an Add, Subtract, Clear Entry, or Store function. TFG2 is negative during RS and RMD times. So the output of O-304 will be nega- tive to enable SAD9 and SDC9 in each RS and RMD times. At the end of RStime RS is shifted to the D Counter. At the end of RMD time, RMD is shifted to the D Counter, and RS is shifted into RMD time at the C Counter. This leaves RMD in the D Counter. If the RMD data is in the D Counter at the end of the next RS time, this data will be shifted into RS time. To avoid this, the D Counter is reset each R1 time. This is done by OR gate 305, EEN42 gates for Add, Subtract, Clear Entry, or Store. PS64 and TR14 gate for each R1 time in PS6, and the output of O-305 will go negative for 48 ps at this time. Any negative input to AND gate 309 will cause CRD9 to be developed by elements 144 and 145. So, OR gates 310, 304, and 305 are operated to shift down R1, R2, R38, and R4 in PS6 of a Sub- tract problem. (For additional shift down informa- tion, see Topic E4.) 3. THE DEVELOPMENT OF MSU4 The actual subtract operation is done in PS7. Again it must be assumed that the Sign Control FF is in the reset condition. If it is, then ASC2 is 5-10 Courtesy of The Old Calculator Museum http://oldcalculatormuseum.com 12-15-65 positive to inhibit the generation of MAD4. ASC1 is negative. This signal is one of three inputs to OR gate 023 and enables 0-023. PS74 gates for PS7, and ACOF1 must always be negative at the beginning of PS7. (The reason ACOF1 is there is because in this machine if itis necessary to com- plement R1, the complement is done in PS7 instead of in PSZ as in the Four Counter EC-130. Since MSU3 must be inhibited ifthe complement is being taken, ACOF1 is used to in